Hi,

On 15/03/18 14:26, Martin Lucina wrote:
> Hi,
> 
> On Thursday, 15.03.2018 at 13:52, Andre Przywara wrote:
>>> Still running at 648 Mhz and haven't seen the BUG again, but am only
>>> moderately loading the board with building and running self-tests for the
>>> project I'm working on [1] out of tmpfs.
> 
> Running for an hour or so now and "BUG: bad page state in process ..." has
> reappeared so I suspect we're not out of the woods yet.
> 
>> Do you have access to an original BSP image from Olimex? My
>> understanding was the "boot0" blob used in there is tailored to each
>> board, as it contains the proper delay values for each DRAM line as laid
>> out on the PCB. We took the values from the Pine64 boot0 for the SPL.
>> I don't really know if those blobs are *really* board specific or if
>> people just copy from each other, but at least it's worth a try.
>>
>> So if you send me (or point me to) the blob, I can bake a patch which
>> uses those delay values and you could give it a test.
>> I just need the part from 8KB to 40KB of an SD card image. It should
>> have some eGON signature in the first line of a hexdump.
>> It should look something like this:
>> https://github.com/longsleep/build-pine64-image/blob/master/blobs/boot0.bin
> 
> Here you go: https://gist.github.com/mato/c0f64eeb139cad6a98c7cdc7c86c70d0

So I looked at this a64-olinuxino.dts you referenced in that other mail,
which has those values spelt out in the "dram" node. Interestingly they
are somewhat different from the values in this boot0, also different
from the values used in the SPL (taken from the Pine64 boot0).
We can cover up for some values in U-Boot rather easily (by providing a
new file in U-Boot's arch/arm/mach-sunxi/dram_timings/ directory), but
that would not cover the delay lines, which - at the moment - are
hardcoded in the DRAM driver and are per-SoC. So it smells we need some
rework of the driver, and also find a way to feed in DRAM parameters in
a more sane way.
I will try to hack something up tonight so that you can have a SPL
tailored to the Olinuxino, so you could give it a try to see if that
fixes your issues. If it does, it would be worthwhile to look at
refactoring the driver. I think that also opens up the possibility of
clocking the DRAM at 800MHz, as the chips and the controller should be
able to do that.

Cheers,
Andre.

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