----- Original Message -----
From: "David Cary" <[EMAIL PROTECTED]>
To: "Multiple recipients of list proteledausers"
<[EMAIL PROTECTED]>
Sent: Wednesday, February 21, 2001 11:37 AM
Subject: RE: [PROTEL EDA USERS]: Best layer arrangement


>
> >From a cost standpoint, it doesn't matter how you re-stack the board. A 6
layer
> board is a 6 layer board, no matter if the power planes are inside or
outside.
> And a 6 layer board is always going to be more expensive than a 4 layer
board.
> If you can really go from a 6 layer board (standard) to a 4 layer board
(with
> unusual stackup), I would go for it. I already know of one case where it
was
> cheaper to buy one 6 layer board and one 2 layer board (the same size, so
they
> would stack) than to make the 6 layer board about 50 percent larger and
put
> everything on that one board -- even after factoring in the cost of the
> connectors and assembly time.
>
> Hmm -- how about putting the ground plane on an outside layer, and the
power
> plane immediately adjacent on the next internal layer ? That would give
you the
> same interlayer capacitance as your original stackup. Although I suspect
this
> "interlayer capacitance" idea is a red herring -- what's really important
is the
> impedance of the power planes, which doesn't much depend on where they are
in
> the stackup.

<...snip>

An unbalanced layer stack??  It pays to have a symmetrical build as far as
copper area goes.  If you have a build such as; plane, plane, signal,
signal, signal, signal, as suggested (??) above, then the top two plane
layers have significantly more copper than the remaining 4 signal layers.
This results in various stresses building in the fabricated board and you
may end up with a bunch of bananas.  A better approach is to build the
layers out from the centre with reasonably "balanced" copper areas on
opposing layers, eg. signal, plane, signal, signal, plane, signal, OR
signal, signal, plane, plane, signal, signal.

As for the "red herring", when you're dealing with high speed/fast rise time
signals, inter-plane capacitance does become significant.

Hmmm, bananas, seafood.  It's lunchtime, I'm hungry, sun's shining, no
clouds, I'm going outside!

Regards
Brendon.


> > -----Original Message-----
> > From: TSListServer [mailto:[EMAIL PROTECTED]]On
> > Behalf Of Georg Beckmann
> > Sent: Tuesday, 20 February 2001 5:34 PM
> > To: Multiple recipients of list proteledausers
> > Subject: [PROTEL EDA USERS]: Best layer arrangement
> >
> >
> > Hi to all,
> >
> > This question is more a general one,
> >
> > I have to do a redesign of a 6 layer board. The layers sequence
> > from top to
> > bottom is,
> > Top routing, second routing, GND, VCC, third routing, fourth routing.
> > Top layer has all IC's. The bottom layer has the resistors, cap aso.
> >
> > If I change the GND and VCC to the top and bottom layer, there is
> > more space
> > for routing.
> > Even more space I could get with the use of blind vias.
> >
> > What does you mean is the better solution: six layer standard or 4 layer
> > with planes at top
> > and bottom and perhaps blind vias.
> >
> > Georg Beckmann
> > [EMAIL PROTECTED]
> ......
> > # INTERNET:             http://www.BuE.de #
> .....
>
>
>
>
>
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