(Copied from message below):
> same interlayer capacitance as your original stackup. Although I
> suspect this
> "interlayer capacitance" idea is a red herring -- what's really
> important is the
> impedance of the power planes, which doesn't much depend on where
> they are in
> the stackup.

Don't you believe it!

The interplane capacitance is far and away the highest performance
capacitor available on a board. An 0603 size, 1000pF capacitor will
have a self resonant frequency in the order of 70MHz (assumes a
self inductance of about 5nH).

Any switching circuit needs bypassing which is effective to _at_least_
the tenth harmonic (even a perfect 50% duty cycle square wave has
harmonics rolling off at only 1/n - i.e. the tenth harmonic is one
tenth the power of the fundamental). Real clocks tend to have far more
power in the high oreder harmonics than one might expect.

Provided that you can get a low inductance connection to the plane
(e.g. multiple vias), the interplane capacitance will outperform
any discrete component you could place on the surface!

(I'm working on mixed-signal circuits with 80MHz clocked digital stuff
next to 30MHz, 770MHz, 3.3GHz, 4.4GHz and 5GHz low noise analog sections
- getting effective bypassing is the hardest aspect of the design)

Cheers,

John Haddy

PS "High Speed Digital Design" by Howard W Johnson and Martin Graham
is a good read for anybody doing boards above 30MHz or so.

I can also recommend courses by Lee Ritchey on HSDD and by John B Howard
on Designing for EMC - both these guys taught me heaps about stuff that
I thought I already knew. (Usual disclaimers - just a satisfied student)



> -----Original Message-----
> From: TSListServer [mailto:[EMAIL PROTECTED]]On
> Behalf Of David Cary
> Sent: Wednesday, 21 February 2001 9:38 AM
> To: Multiple recipients of list proteledausers
> Subject: RE: [PROTEL EDA USERS]: Best layer arrangement
>
>
>
>
>
>
> Dear Georg Beckmann,
>
> Thanks for telling us about your interesting variation of the
> "Pad Cap board"
> idea: put GND and VCC on outer layers.
>
> Pros:
>   more routing area. (Large footprint pads now eat area out of
> the power planes,
> rather than the signal planes).
> Cons:
>   Less interlayer capacitance.
>   slightly more crosstalk interference.
>   more difficult to access signal traces.
>
> The first 2 cons are irrelevant unless you're at really high
> speeds. The 3rd con
> -- well, already over half of the signal traces on a standard 6
> layer board are
> already inaccessible. So it doesn't make it much worse if *all*
> of the signal
> traces are inaccessible. (Pad Cap boards have no signal traces on
> the outside
> layers, only pads and vias and the short stub between them. These
> boards don't
> even have a solder mask).
>
> >From a cost standpoint, it doesn't matter how you re-stack the
> board. A 6 layer
> board is a 6 layer board, no matter if the power planes are
> inside or outside.
> And a 6 layer board is always going to be more expensive than a 4
> layer board.
> If you can really go from a 6 layer board (standard) to a 4 layer
> board (with
> unusual stackup), I would go for it. I already know of one case
> where it was
> cheaper to buy one 6 layer board and one 2 layer board (the same
> size, so they
> would stack) than to make the 6 layer board about 50 percent
> larger and put
> everything on that one board -- even after factoring in the cost of the
> connectors and assembly time.
>
> Hmm -- how about putting the ground plane on an outside layer,
> and the power
> plane immediately adjacent on the next internal layer ? That
> would give you the
> same interlayer capacitance as your original stackup. Although I
> suspect this
> "interlayer capacitance" idea is a red herring -- what's really
> important is the
> impedance of the power planes, which doesn't much depend on where
> they are in
> the stackup.
>
> I don't know much about blind vias. Tell us what you find out
> about the price of
> 6 layer through-hole vs. 4 layer blind vias, OK ?
>
> Advanced Circuits
> http://4pcb.com/
> has nifty on-line quote price calculator
>
> > -----Original Message-----
> > From: TSListServer [mailto:[EMAIL PROTECTED]]On
> > Behalf Of Georg Beckmann
> > Sent: Tuesday, 20 February 2001 5:34 PM
> > To: Multiple recipients of list proteledausers
> > Subject: [PROTEL EDA USERS]: Best layer arrangement
> >
> >
> > Hi to all,
> >
> > This question is more a general one,
> >
> > I have to do a redesign of a 6 layer board. The layers sequence
> > from top to
> > bottom is,
> > Top routing, second routing, GND, VCC, third routing, fourth routing.
> > Top layer has all IC's. The bottom layer has the resistors, cap aso.
> >
> > If I change the GND and VCC to the top and bottom layer, there is
> > more space
> > for routing.
> > Even more space I could get with the use of blind vias.
> >
> > What does you mean is the better solution: six layer standard or 4 layer
> > with planes at top
> > and bottom and perhaps blind vias.
> >
> > Georg Beckmann
> > [EMAIL PROTECTED]
> ......
> > # INTERNET:             http://www.BuE.de #
> .....
>
>
>
>
>
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