Brian Guralnick wrote:
> Here is my successful 6 layer 200Mhz design with high speed digital on top &
> bottom, and analog on top.  1.5 ns typical rise & fall times, >75db
> isolation from digital to analog section.
> 
> Top            -> High speed digital & Analog
> MidLayer1 -> Mid speed digital
> MidLayer2 -> Split VCCINT 1.8v & AGND
> MidLayer3 -> DGND
> MidLayer4 -> VCCIO 3.3v
> Bottom       -> High speed digital

Personally, I would use a setup more like

 Top         -> Low speed digital (& AGND pours as needed)
 MidLayer1   -> High speed digital (& Analog)
 Innerplane1 -> DVCC (& AVCC if needed)
 Innerplane2 -> DGND (& AGND if needed)
 MidLayer4   -> High Speed digital (& Analog)
 Bottom      -> Low Speed digital 

With the following caveats:
  1) NO digital signals EVER cross a plane gap
  2) No analog signals are routed without an associate AGND plane
  3) AGND and AVCC do not overlap DGND or DVCC anywhere
  4) Core voltage (1.8V) routed on top and bottom with large (low 
      impedance) traces on bottom
  5) Assumes VCCIO (3.3V) "is" DVCC
  6) Analog signals can tolerate a via (if not they are routed
      top layer with AGND poured on Midlayer1)

I am sure I have missed some important rules, but off the top of my
head, these are the top priorities without referring to my checklist
(You DO have a checklist don't you?).

David W. Gulley
Destiny Designs



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