Dear board designers,

> "Brendon Slade" <[EMAIL PROTECTED]> on 2001-02-20 05:08:25 PM
> An unbalanced layer stack??  It pays to have a symmetrical build as far as
> copper area goes.
> various stresses building in the fabricated board and you
> may end up with a bunch of bananas.

You're right, I completely forgot about board warps. Whoops. [blushes].

Um, forget my misconceived notion, and let's return to the original idea from
Georg Beckmann:
Put the power planes (board-sized filled polys) on the outside (plane, signal,
signal, plane). That is OK from the perspective of board warps, right ?

I stumbled across someone else doing the same thing:
``we decided to put the power planes (or the ground planes) on the outside of
the board'' --

but they don't have a good explaination for it.
> As for the "red herring", when you're dealing with high speed/fast rise time
> signals, inter-plane capacitance does become significant.

> "John Haddy" <[EMAIL PROTECTED]> on 2001-02-20 05:35:46 PM
> PS "High Speed Digital Design" by Howard W Johnson and Martin Graham
> is a good read for anybody doing boards above 30MHz or so.
> I can also recommend courses by Lee Ritchey on HSDD and by John B Howard
> on Designing for EMC - both these guys taught me heaps about stuff that
> I thought I already knew. (Usual disclaimers - just a satisfied student)

Thanks for the recommendations.

I agree with just about everything else John Haddy says:
> From: David Cary
>> I
>> suspect this
>> "interlayer capacitance" idea is a red herring
>Don't you believe it!
>The interplane capacitance is far and away the highest performance
>capacitor available on a board. An 0603 size, 1000pF capacitor will
>have a self resonant frequency in the order of 70MHz (assumes a
>self inductance of about 5nH).
>Any switching circuit needs bypassing which is effective to _at_least_
>the tenth harmonic (even a perfect 50% duty cycle square wave has
>harmonics rolling off at only 1/n - i.e. the tenth harmonic is one
>tenth the power of the fundamental). Real clocks tend to have far more
>power in the high oreder harmonics than one might expect.
>Provided that you can get a low inductance connection to the plane
>(e.g. multiple vias), the interplane capacitance will outperform
>any discrete component you could place on the surface!

You're absolutely right. I don't know what I was thinking.
Yes, you're right that this interplane capacitance is crucial.
Eliminating power planes entirely is a bad idea.

  Voltage Guidelines for Pentium(r) Processors with MMX(TM) Technology
makes the surprising statement that
``Data collected through these experiments showed that only noise components
less than 20 MHz were reduced on the die by decoupling capacitors added
Does this mean that noise above 20 MHz is there to stay, no matter how many
discrete capacitors I add ?

Moving the power planes from the center to the outside of a 4 layer board
(power, signal, signal, power) reduces the capacitance between them by a factor
of 3. Is that significant ? I speculate that it is not significant -- at very
high frequencies, the impedance of that capacitor is close to 0 Ohms. After I
multiply 3 * 0 Ohm, it is still negligible compared to the resistance and
inductance of the complete loop. (right ?)
So, at high frequencies, reducing the inductance leading to the capacitor is
more important than a large capacitance value.

Moving the power planes to the outside keeps the inductance of each circuit loop
(say, between a power pin and a ground pin on a CPU) is about the same. (The
inductance of 1 full via (or 2 half vias) + a short trace + 2 IC pins).

Other web pages I've recently seen that look relevant:

vias have about 0.7 nH inductance
a 10 mil wide, 100 mil long trace has about 1.6 nH inductance

Mobile AMD-K6

 Processor: Power Supply Design (1999)

 AMD-K6 Processor: EMI Design Considerations

David Cary

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