On 11:31 AM 3/28/01 -0500, matt said:
>Leaving CMOS logic inputs floating is bad design practice . The inputs are
>high impedance and wideband and pick up noise that translates in outputs
>toggling state randomly at high speed . This has nothing to do with pcb
>layout and is an electrical design issue.

Yes and no. of course it it's an electrical design issue. And it also has 
everything to do with the PCB layout, as a layout which doesn't account for 
open pins is subject to the associated error condition, which in itself is 
clearly an electrical design issue. (Maybe you meant an architectural or 
systems design issue?)

>  You shouldn't have to deal with
>this type of problem unless you're also the person who _designed_ the
>schematic and are not just doing the capture and layout. Protel schematic is
>not intended as a digital design tool .

While I agree that in principle, engineers are ultimately responsible for 
flaws in their designs, we ALL ultimately have to deal with it. Further, in 
case you're not aware, this software isn't just for PCB layout designers, 
nor is it used for that task only by PCB layout designer, in much the same 
way that little or no drafting is done anymore by "draftsmen". As a modern 
engineer. I not only design circuits, but I also draft them, and I lay out 
PCBs, design electro-mechanical interfaces, and perform other functions not 
strictly related to my job title, unlike many of my older "brothers" in the 
field, who often still can't even use a simple schematics capture program, 
and when asked to, quickly respond that it's someone else's job...In other 
words, the tech that blindly and in total ignorance follows engineer 
instructions is little better than hiring a monkey.

That the post was made should be sufficient reason to answer the content of 
the question,  without implicitly questioning the query itself by entering 
into a discussion of who is and isn't responsible.. IMO and IME, regardless 
of their legalistic accuracy, answers like that from the engineering 
community do nothing more than to subtly dissuade people from advancing 
their skills and knowledge-base, not to mention sometimes leaving the 
engineer and his/her company in the position of eating a whole bunch of 
environmentally unfriendly pieces of wasted time and money, which could 
have been caught by an energetic up-and-comer going beyond their narrowly 
specified sub-sub-sub task.

Bite me for asking, but at ten posts (hmm..now it's 11) and counting, maybe 
this has gone on long enough to move it to the OT group?


Andrew J Jenkins. NCMR @ NASA-GRC

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