Hi Nicholas,


> In a post about a month ago Mr. Lomax mentioned that leaving a CMOS input
> open could cause problems on a board.  Are there any references that will
> help me learn the details that might cause problems like this in
commercial
> devices

See "High Speed Digital Design: A Handbook of Black Magic"
by Howard Johnson, Martin Graham

If you vary the input voltage on a CMOS gate while measuring the current
drawn at Vcc,
you will find that the current is at a minimum when the input is High or
Low,
but goes through a definite peak when the input voltage is Midway.

The reason is simply that the CMOS output stage has two Fets in series.
Normally one is On and the other is Off. However at Mid Voltage they go
through a region where both are switched on at the same time and thus draw
lots of currrent.

Another reason is that a floating CMOS pin is much more vunerable to being
zapped by static charges........

I hope this helps a little.

.................................. Zim


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