Three possible failure modes come immediately to mind: oscillations leading
to excessive power consumption (at best!), latchup (aka 'halt and catch fire
mode') and static/ESD damage.
Don't leave CMOS inputs floating, whatever the temptation, it'll cause
problems sooner or later (believe me on this!)
Unused inputs should ideally be pulled to Vdd via a suitable resistor
(opinions vary, but 10k-100k should suffice). A number of inputs can be
linked and pulled up by the same resistor to cut the number of resistors
needed (if cost/space is critical) but watch out for pull-up traces running
long distances. You might get away with connecting them directly to Vdd,
but there are two main implications:
1) in the case of spare gates, it's harder to cut/link later when someone
wants to use the gate(s) to fix a problem
2) power pins are usually more tolerant of over voltage than inputs - the
resistor limits input current in such cases.
Hope this helps.
Regards
Andy Gulliver
> -----Original Message-----
> From: Nicholas Cobb [mailto:[EMAIL PROTECTED]]
> Sent: 28 March 2001 15:15
> To: [EMAIL PROTECTED]
> Subject: [PEDA] Reference
>
>
> In a post about a month ago Mr. Lomax mentioned that leaving a CMOS input
> open could cause problems on a board. Are there any references that will
> help me learn the details that might cause problems like this in
> commercial
> devices? Up to this point I have been making circuit boards that will be
> used only by me. I am just starting to work on some that will be mass
> produced. Any sort of help would be appreciated.
> Thank you,
> Nick Cobb
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