thanks guys,

i'm going to rework the schematic to one net per node.  i'm going
to lose the equivalent look and feel between the schematics, but
as they say, "any port in a storm."  no pun intended.  ;-)

thanks again, miker

> -----Original Message-----
> From: Brad Velander [SMTP:[EMAIL PROTECTED]]
> Sent: Thursday, August 30, 2001 6:38 PM
> To:   'Protel EDA Forum'
> Subject:      Re: [PEDA] nets and ports ??
> 
> Mike,
>       I am not sure what exactly you are expecting from your description.
> I think I understand what you are trying to say but I am not sure I am on
> the right track. For what it is worth, having used about four different
> CAD
> systems over the years I have never seen one that will list different nets
> that eventually tie together. Some net is always dominant when it comes to
> the schematic netlist, this is usually the one that the netlister came
> across first during it's processing of the schematics. Other differently
> named nets that ultimately connect to the same point get amalgamated into
> the initial net name.
>       I know that PADS now has a "Tie-Point" type function but up to the
> time I last used PADS I had not used that function and do not know how it
> actually netlists. Ideally I would think that that function kept nets
> separate until the one point in which they are tied together, but that is
> pure conjecture on my part.
> 
> Brad Velander,
> Lead PCB Designer,
> Norsat International Inc.,
> #300 - 4401 Still Creek Dr.,
> Burnaby, B.C., V5C 6G9.
> Tel. (604) 292-9089 direct
> Fax (604) 292-9010
> website www.norsat.com
> 
> 
> > -----Original Message-----
> > From: Robison Michael R CNIN [mailto:[EMAIL PROTECTED]]
> > Sent: Thursday, August 30, 2001 3:05 PM
> > To: 'Protel EDA Forum'
> > Subject: Re: [PEDA] nets and ports ??
> > 
> > 
> > well, from looking the netlist over and comparing it to the schematic
> > i did, it looks like you're not allowed to have more than one net name
> > per node.  that is gonna hurt.  i tried to reproduce the schematic in
> > protel as close as possible to the original to reduce errors.  so now 
> > i've got an 11 page schematic that is filled with multi-netted nodes
> > which are not being interpretted in protel as i meant them to be.  
> > 
> > miker 

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