Thanks to all.

Actually, my problem was a more classic error.  When creating the library
part for the schematic, I forgot to flip a pin to the correct orientation
relative to the part outline - so it was backwards.  I also did not have a
label name on it and never noticed the inconsistent position of then pin
number on the schematic - so it wasn't actually being connected to anything!
Hence the strange startup conditions that failed the simulation in the GMIN
stepping.


regards,
Tim Hutcheson
[EMAIL PROTECTED]




> -----Original Message-----
> From: John Haddy [mailto:[EMAIL PROTECTED]]
> Sent: Monday, April 15, 2002 7:29 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Timestep Too Small
>
>
> This is a classic Spice error!
>
> I often run into this if I don't have a DC path to a node, to allow
> initial conditions to stablise. My first approach to solving this
> issue is to add a 100megohm or larger resistor across the capacitor
> (which is usually the cause of the error).
>
> Hope this helps.
>
> John Haddy
>
> -----Original Message-----
> From: Tim Hutcheson [mailto:[EMAIL PROTECTED]]
> Sent: Tuesday, 16 April 2002 2:14 AM
> To: Protel EDA Forum
> Subject: [PEDA] Timestep Too Small
>
>
> The circuit I am simulating simulates fine with a ua741 sim
> device but when
> I attempt to sim with the subckt model from the TI website for
> the OPA548, I
> get the "timestep too small" error.  My recollection is that this
> is caused
> by too high a transient on startup (fails in the GMIN stepping)
> for the sim
> to follow but can't remember the details.  Anyone know the right
> approach to
> fixing this?  tnx in advance.
>
> regards,
>
> Tim Hutcheson
> Institute for Human and Machine Cognition
> 40 S. Alcaniz St.
> Pensacola, FL 32503
> 805-202-4461

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