I'm using Altera FPGAs exclusively, since the tools are an effort in
itself. I also find the handling of MaxPlus2 rather awful, Quartus2
is a bit better.
The functionality they provide is far beyond just a schematic editor.
They allow me have graphic modules ( forget the VHDL for now)
to make a hierarchical design. Beside the TTL family there are 
wizards that allow me to generate a N-bit adder/fifo/whatever, 
with/without clockenable/inputenable/outputenable.

How do I get that functionality in Protel ?

Since I do many projects that are not really specified,
but I estimate the future digial functionality to be implemented
with say 64 Flipflops, I take a 3064 without having an idea about
the inside. While the pcb is being manufactured I start thinking 
about the inside. Many times, the final content of the FPGA is
adapted after experiments on the customers site.
This all is also simpler when it doesn't involve Protel.
On the board the FPGA is a chip with some connections.


Rene

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Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net



TheLight wrote:
> 
> One reason to get the drawing in Protel and then export it to the Xilinx
> tools is that the schematic editor of Xilinx is not, how shall I put it,
> particularly convenient. I myself have done some designs in it while the
> rest of the board was done in Protel. This got me out of my hum on more
> than one occasion.
> I did attempt to write a server for Protel99SE that created the netlist,
> however this proved to be cumbersome as the netlists of the individual
> primitives needed to be included in the main netlist too. Can be done, but
> I never finished it.
> 
> As to all functions offered by Xilinx; their tools are reasonably
> documented and can be executed from either from within such a server, or
> just seperately and then have an external netlist (the Protel one) as input
> to the tools.
> 
> Presently I also use Atmel FPGAs for which I did write a server to create
> EDIF netlists as well as manage the 'user macros' and be a interface toward
> the Atmel FPGA tools.
> The advantage for me is that I can use Protel (with which I am familiar) so
> I can concentrate on the design, not the tools.

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