At 09:35 PM 7/31/2002 -0700, Michael Reagan (EDSI) wrote: >Abdul wrote >AND WELCOME BACK!
Thanks. China is quite a place.... not what I expected. > > Suppose the worst designer reading this list knows how to accomplish the > > task? Should he keep it to himself? > > >No that automatically requalifies the worst designer as the best of the >best Let's put it this way. If the worst designer tries to help others, he or she will probably develop rapidly. Nothing brings the real experts out of the woodwork better than bad advice given publicly. Of course, if this designer is not willing to admit errors or to learn better ways, not much is going to be learned. But what this arrogant and ignorant designer says might still be correct and useful. Even a stopped clock is right twice a day. >.>It is generally not necessary to pour in more than one direction......... > >That we havent tried. I might have mentioned this is a backplane.... I saw >it for the first time today, it has 42,000 pads I think we now know why the pour is taking a bit long. > > If one desired pour track to pass between pins with a narrow width, it is > > not necessary to set the entire pour to that width. Instead. Make a > > pass-through pattern for a part and copy that pattern over the part with > > the pour already done. Protel will assign these copied tracks the proper >net. > >That is too risky and cumbersome of a solution if we have to edit the >design, but thanks It seems to not have been understood that any mistakes in placing the pass-through track (if you even need it, you might not) will be caught by DRC. So it is not at all risky. As to cumbersome, that depends on how it is done. > > First, route the ground (if that's the net being used) with track entirely >.......etc > >Abdul, >we decided to "BAG" ( our terms means Sh- can ) the merge system becuase >the we can not control verification on a board that cost 10K a pop . POP >means each for you down under. We will attempt dividing the design into 4 >quadrants and pour separately. It may have been overlooked that a merge plot as I described it is verified by DRC. In fact, I first developed this method in order to check negative planes on an old Calma system, which otherwise could be done only by painstaking visual inspection. The tie track guarantees connection. And no connections are made to the plane except with the tie track. So such a plot is more fully verified than is an inner plane in Protel 99SE. As you know, via blowouts can easily isolate an area and DRC cannot detect this. But if a plane is built by using negative blowouts and then adding pads and tie traces (i.e., the usual top layer, if this is a top layer pour), any islands will be detected by DRC. (Such an island is nothing more than an incomplete route). Typically one creates a pour with greater air gap than the board minimum, to improve manufacturability. But a tie track can approach pads at the board minimum, so it can pass between pads whose blowouts might touch and otherwise create a break in the copper. It is with multiple, split planes that visual check becomes crucial, since the correct isolation of each plane section is not guaranteed. Likewise the isolation of non-plane track on the layer being poured is not checked by DRC. But (1) the isolation is the result of a process that treats the whole layer at once, so it is not necessary to check each individual piece of track. (2) incorrect isolation will stand out like a sore thumb if the layer is appropriately viewed. I used this technique with Tango many times without problems; however, once or twice I modified a complex split plane design without going through the full process. In other words, I'd recommend, if you change anything on such a merged plane, start from scratch, don't try to re-use the stuff generated by the process I described. The tie track, of course, can be kept, and plane split track (isolation) can also be kept; one only needs to take care that tie tracks do not cross a split, since they would short the split sections together. Again, this can be verified with ease visually if one has the appropriate display settings. Note that a tie track can cross into the area of an isolation trace as long as it maintains clearance from the *other* side of the isolation area. But such tracks make it more difficult to check such a plain because they will stand out when seen with the same settings that make violations visible. Note also that it is not necessary to check (in Protel) the blowouts of the pads and vias, since these are correctly created by generating the solder mask, and a trace cannot cause a short by crossing these blowouts without also creating a DRC (short or clearance) error. Basically, merged split planes are easier to verify thoroughly than are Protel inner planes, and I haven't noticed Protel designers refusing to use inner planes because they are not completely DRCd. Both should still be looked over in CAMtastic or whatever. If the board were a through-hole board with only one plane which covers the entire board, and no routing track on that layer, there would be no need to verify it, since it would be completely verified by DRC. But SMT components require fanouts and thus it gets a little more complex. It would be fairly simple to write a utility that would create the blowout track necessary to isolate the fanout or other routing track on the layer from the pour. It is almost trivial if there is only one net for the pour, because it would only be necessary to create blowout track for all tracks which are not part of the poured plane net. This is, as I described, what one does using global edits, in the absence of a utility. ************************************************************************ * Tracking #: 817743620A24024E898D815FB16D36BB976B33DA * ************************************************************************ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
