On 07:50 PM 19/09/2002 +0100, Rich Thompson said:

>On 09:36 AM 19/09/2002 +0200, Ian Wilson said on PEDA:
>
> >snip<
>
>The P99SE DRC system does not consider multi-layer entities as also
>existing on the various copper layers.  This is why Kulajew's rule does
>not
>work.  I have raised this with Altium on a number of occasions.  It is a
>
>structural issue I gather.  It is not a bug but a limitation of the
>underlying architecture.  To us users, though, it is annoying.
>
> >> very annoying, and its STILL the same on DXP!  What gives Atium?  We
>do mostly single/PTH boards, and very rarely mulilayer.  My library has
>overy large bottom layer pads (for single sided boards) and very small
>top layer pads (to encourage solder to flow up pth wall and stop shorts
>etc on top)  this means however that when I route on top layer it
> >loooks< as though im going to short (because I see the biggest pad,
>bottom) and not the extra space around the top pad)  Arrrgh!

I just tested this in DXP - it seems to work OK at least DRC allowed me to 
bring the top tracks close to the top pad size while bottom layer tracks 
were controlled by the size of the bottom layer pad size.

In fact I thought this worked OK in P99SE as well.  The clearance DRC, I 
thought, is smart enough to use the different pad sizes according the 
tracks layer.

I must be missing something here.  Can you explain more?  Can you email me 
(directly not to the list - [EMAIL PROTECTED]) a small sample file 
showing the issue?

My problem with multilayer entities is really restricted to the calculated 
layers like paste and mask layers.

Ian

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