Brock,
        thanks for the suggestions. The real problem is not the nets
toggling which is similar to duplicate pin numbers but in this case why is
it continually generating these duplicate nets? Once the duplicate nets are
generated then the nets vacillate back and forth between each duplicate with
each successive update. (i.e. disconnect pinX from net y, connect pinX to
net Y, the second net Y is the duplicate.) As well if you look at the
netlist in PCB there are two nets of exactly the same name in the net list
for these 14 nets. Unless of course I took the time to delete them in the
update preview screen. However, I want to get rid of them rather then
continually have to delete them during each successive update as the design
progresses.
        Loading using the old netlist load technique does not exhibit this
problem but shows several others that I am working on to find their cause.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com
Norsat's Microwave Products Division has now achieved ISO 9001:2000
certification 



> -----Original Message-----
> From: Brock Russell [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, October 03, 2002 12:20 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] P99SE SP6 Problem with Update PCB generating
> duplicate nets or ot her errors.
> 
> 
> 
> >    Duplicate designators aren't an issue unless they have 
> some manner of
> >getting past the ERC check for that situation.
> 
> Duplicate pin number errors are not always caught at the schematic
> level ERC and can cause the alternating net connection on update.
> Seems an unlikely cause since you have 14 nets toggling.
> 
> Did you catch all of the components that were placed off the 
> work space?
> I have had strange update errors with components located very 
> far below
> the absolute origin. Never have figured out how they get placed there.
> 
> Brock

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