Abd ul-Rahman & others,
        Ok guys, through all of your comments it is becoming very clear what is going 
on now. Thanks for the suggestions and assistance. I hadn't intended for someone else 
to do the testing and work out the definition of my problem but my efforts have been 
concentrated on getting the boards out and not what detailed testing would define the 

        Abd ul-Rahman, I am not relying on ports or sheet symbols to name nets, I just 
want the connectivity between the sheet symbols and ports. I am not thinking that 
sheet entries should be global. There is also no multi-channel connectivity happening 
here. It is simply two different discrete filter circuits both placed onto one 
subsheet because of a lack of room on the upper sheet. A sheet symbol should connect 
to an equivalent port on a subsheet, that is not expecting anything to be global.

        It is now clear that ports global does not make any connection between sheet 
symbols and ports, don't know who was the genius that thought this one up but why 
would two entities that are intended to make a trans-sheet connection not work because 
of the Ports global option. This makes them useless and as Craig pointed out, they 
just don't work in this case. In my mind and experience a sheet symbol with a matching 
port on the subsheet should make the connection regardless of the connectivity option, 
in my mind they are intended to connect by their very definitions. There may be some 
obscure case where this would be a desired operation but I can't think of it at the 
moment. If you used a sheet entry on the top schematic, you obviously wanted it to 
connect somewhere, not just sit there as a non-functional blob inserted into your 
schematic for no reason.
        Anyway what I have now works. I have the sheet symbol with suitably named 
sheet entries, matching ports on the subsheet. This gives the appearance of a 
component that is defined further on the subsheet and identifies which sheet contains 
the detailed circuitry. I also have squeezed in net labels onto each of the connecting 
lines on the top sheet and subsheet to give my connectivity for netlisting. I could as 
Abd ul-Rahman suggested use two (four for both circuits) ports on my top sheet and 
draw a box around them to obtain approx. the same result.

        Thanks for the testing Abd ul-Rahman, your results and definition was very 
clear. I would have gotten there in a day or two when the pressure to get these boards 
out subsided, but thanks again.

Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010

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> -----Original Message-----
> From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]
> Sent: Thursday, July 24, 2003 10:12 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] P99SE Sheet Symbol & Port connectivity across
> sheets.
> Brad, you are assuming that "Net Labels and Ports Global" 
> will cause *Sheet 
> Entries* to be global....
> Anyway, I couldn't stand it, I had to test this.
> It turns out to be pretty simple.
> It appears that with Net Labels and Ports Global scope, Sheet 
> Entries are 
> *ignored.* Further, Ports do not create nets that connect to 
> net labels of 
> the same name. Ports connect to Ports of the same name, Net 
> labels connect 
> to Net labels of the same name.
> Ports do not appear to create net names at all. Net labels create net 
> names. This is *very* useful.
> If I have a Port on one sheet and a Port on another sheet, 
> both named TEST, 
> with Ports global, what is connected to the two ports will be wired 
> together. A TEST net label will not be connected to this net, it will 
> create its own net called TEST. The net of the Ports will 
> have the default 
> name assigned to it by Protel, usually derived from the 
> component pin first 
> connected to it, unless, of course, there is a net label on that net.
> Now, about the Sheet Entries. I took a schematic, I'll call 
> it toplevel, 
> and placed a pin, E1-1 on it, and wired this to a sheet entry 
> called TEST 
> on a sheet symbol for a sheet named SUBSHEET. I then created 
> the subsheet 
> using Design/Create Sheet from Symbol. On this sheet I wired the 
> automatically created TEST Port to E2-1.
> Creating a netlist with Sheet Symbol/Port connections 
> connected the two 
> pins as expected. The net was named NetE1_1.
> I then created another netlist with Net Labels and Ports Global. Two 
> separate nets resulted, NetE1_1 and NetE2_1.
> I then placed a Port named TEST on the toplevel sheet and 
> connected it to 
> the wire and regenerated the Net list, Net Labels and Ports 
> Global. There 
> was now once again a single net, NetE1_1.
> I deleted the Port named TEST on the toplevel sheet and 
> replaced it with a 
> net label TEST. There were now two nets, TEST containing E1-1 
> and NetE2-1.
> With Net Labels and Ports Global, sheet symbols perform only 
> the function 
> of calling a named schematic file into the full schematic document.
> >         However, in my case I did not even rely on any global 
> > connectivity tricks of the ports, I wired the desired 
> signals directly to 
> > the sheet entries and directly to the ports on the 
> subsheet. The ports 
> > and sheet entries only had to perform their expected 
> connectivity between 
> > the master sheet and the subsheet, it failed to do this. I 
> still don't 
> > know why but according to Craig from Altium, it just plain 
> won't work.
> Right. It doesn't work because Sheet Entries are not Ports, 
> they don't 
> function like Ports, they only work with Sheet Entry/Port 
> Connection scope.
> >  Possibly he misunderstood my issue and therefore his 
> answer was not 
> > correct but he seemed pretty sure of the fact that it 
> didn't work because 
> > the only way to make ports work was by not having any form 
> of nets global 
> > in the connectivity setting.
> Yes. That's how it works.
> >  Not going to happen, I don't need to spend hours 
> connecting multiple 
> > sheets together on a top level master sheet that nobody 
> will even want to view.
> It's much easier than you think, and it makes for much more readable 
> schematics. And *less* work and fewer errors, particularly if you use 
> repeated blocks of circuitry.
> >  Thus I typically use a flat hierarchy and global nets. 
> This case was 
> > special because they tried to jam too much circuitry into a 
> an existing 
> > schematic where my only option was to connect through a 
> sheetsymbol in 
> > place of the former integrated device schematic symbol.
> No, your option was not that at all, for the simple reason 
> that it doesn't 
> work. Your option, if you don't want to change your scope, is 
> to place two 
> ports (actually, four ports, since you had two of these 
> subsystems). If you 
> want to make them look like a component symbol, put down a 
> rectangle to 
> enclose them. You could also use net labels, as you ended up 
> doing, but 
> ports, especially with a dummy symbol outline, would look better.
> At some point, however, I do suggest learning how to use 
> Sheet Symbols and 
> hierarchical schematics. I wouldn't leave home without them....
> I don't usually have a top level schematic just for the 
> purpose of tying 
> together the other sheets. Rather, my top level schematic 
> will normally 
> include quite a bit of explicit circuitry. It might have I/O, 
> everything 
> connecting to the outside world. Then the internal signal 
> processing of the 
> project might, as appropriate, be placed on subsheets. It's 
> easy to create 
> the subsheets, and one does not have to worry about net name 
> duplication. 
> You can have a CLK on one sheet that is not connected to CLK 
> on another 
> sheet, a Net Label only refers to the sheet on which it 
> appears; this is 
> *much* easier to manage. You can take pieces of schematics, 
> say a memory 
> subsection, from another project, and plop it into your new 
> project without 
> having to rename the busses, you just have to control the 
> sheet entries/ports.
> Now, working with busses and sheet entries/ports can be a 
> little tricky, 
> but it boils down to the problem that sheet entries and ports 
> do *not* 
> create or associate with net names. They are merely 
> non-net-naming devices 
> for connecting between sheets. That they have names at all is 
> only so that 
> you can associate them together, those names have *nothing* 
> to do with net 
> names.
> If you want a sheet entry or port to become a certain net 
> name, you must 
> place a net label on the topmost occurrence of the net.
> So connecting a bus to a sheet entry (say A[0..7]) does not 
> create a bus, 
> i.e., a series of net names. You have to place an explicit 
> net label to do 
> that. This used to drive me nuts.... I did figure out how to 
> do it, i.e., 
> to place the net labels, but until now I did not really 
> understand why this 
> was necessary. Like you, I assumed that sheet entries and 
> ports *were* net 
> names, even after I had realized that sheet entry/port 
> connections did not 
> name the nets, I had not absorbed the full implications.
> In this thread, there was a report that DXP allows 
> Entries/Ports to name 
> nets *as an option.* It could be argued that this could be a serious 
> problem, since someone might enable the option when modifying 
> a schematic 
> where it was not enabled, and this could create serious chaos.
> Better: good documentation that explains the difference 
> between Ports And 
> Sheet Entries and Net Labels. Hmmm.... Does the documentation 
> explain this. 
> Maybe I should read the manual and find out! ... :-)

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