Hi Ian,
        well you may or may not have seen more posts on my problem but basically your 
assumptions are right. I used the alternate pairing of input sheet entries with output 
port symbols. The reason I did this is because years ago on other systems, this was 
necessary to pass ERC. You couldn't have an input port connected to an input and get 
past the ERC because the input had no driving source, thus you got a lot of possibly 
unnecessary ERC warnings or errors. I don't know if this is true in Protel, haven't 
had much time to test, gotta get the boards out.
        So anyways, I jury rigged it by doing as you do, putting netlabels on both 
ends of the nets, voila connectivity. However, I should not have had to and they are 
squeezed in between the sheet symbols and the next component, not pretty.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com


> -----Original Message-----
> From: Ian Wilson [mailto:[EMAIL PROTECTED]
> Sent: Wednesday, July 23, 2003 7:14 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] P99SE Sheet Symbol & Port connectivity across
> sheets.
> 
> 
> On 05:23 AM 23/07/2003, Brad Velander said:
> >Hi all,
> >         well I finally had to break my normal pattern of 
> flat hierarchy 
> > this morning. I am having difficulties getting sheet 
> symbols to connect 
> > to the subsheet ports. Everything netlists and updates to 
> the PCB just 
> > fine except for the 4 points that connect between sheets. What am I 
> > missing here?
> >
> >I have checked that the ports seem to connect to the wire at 
> the correct 
> >point. This is not the easiest, nor am I sure of this one, 
> because the 
> >electrical snap grid doesn't work consistently. It doesn't 
> always show me 
> >the enlarged dot when I try to connect to the port, 
> sometimes it does but 
> >not always.
> >I have 4 ports, IP1, OP1, IP2 & OP2.
> 
> OK I assume that IP1 is a signal going into that net and OP1 
> is an output 
> on the subsheet?  Is this correct?  The stuff below assumes 
> that IPx is an 
> input to the *sub-sheet* and OPx is an output from the 
> sub-sheet.  You will 
> need to change things if you IPx is an input on the higher 
> level sheet.
> 
> >In my sheet symbol they are set as input, output, input & 
> output respectively.
> 
> Yes this is what I would do.
> 
> >On the subsheet I have the ports set as output, input, 
> output & input 
> >respectively.
> 
> I would have the sub-sheet ports set as for the sheet entries 
> - that is an 
> input Sheet Entry needs a driving signal and it maps over an 
> underlying 
> port which is also an input.  I view the matching port and 
> sheet entry as 
> different views of the same thing.
> 
> I gather you are thinking more that they are different ends 
> of a special 
> component that is an input on the higher level sheet (sheet 
> entry) and is 
> an output on the lower level ports, which then drives the input pin 
> (residing on the sub-sheet).  Is that right?
> 
> So for an input on net XYZ I would have an input pin "driven" 
> by an *input* 
> port, which matches an *input* sheet entry.  Somewhere in the 
> hierarchy I 
> should have, on the same net XYZ, a suitable *output* pin driving an 
> *output* port which matches an *output* sheet entry.  I know 
> it may be odd 
> having an input port driving a pin, but I prefer to think of 
> what the port 
> is doing on the side not connected to a wire.  So I answer 
> "No" to the 
> question about swapping directions when you create a sheet 
> symbol from a 
> sheet.  But this view of the world is just my preference - the system 
> should not care (assuming the ERC matrix is set up appropriately).
> 
> >When synchronizing I have ports and nets set to global.
> 
> Shouldn't this be Ports Only or Sheet Symbols/Sheet Entries?
> 
> 
> >         The only thing that doesn't connect are the 4 port 
> connections. 
> > What am I missing guys?
> 
> In P99SE, ports and sheet entries don't name nets (this is 
> optional in 
> DXP).  Do you have net labels on the nets?  I usually make 
> sure that the 
> net label, port name and sheet entry name all match precisely 
> (unless it is 
> a full hierarchical design). Even when I do nets global I 
> will usually 
> fully wire up ports and sheet entries and have a top level 
> sheet showing 
> the interconnections.  At all levels I have net labels on 
> every wire and 
> bus, and the *same* name (identically) for any associated 
> ports and sheet 
> entries (the INS key is great time saver here, if you are 
> placing a net 
> label, port or sheet entry and you hit INS while hovering 
> over a net label, 
> port or sheet entry, just the text is copied, not the whole 
> object, so it 
> is easy to make a net label with the right name by "morphing" 
> from a sheet 
> entry for instance).
> 
> This scheme means that it makes no difference whether I use 
> Nets and Ports 
> Global or Ports Only - in fact I sometimes will update a PCB 
> with both net 
> scopes and confirm nothing odd happens.  But this scheme 
> won't work in 
> multi-channel designs where you are attempting to use a full 
> hierarchical 
> net list (with duplicated sub-sheets).  But if you are doing 
> this DXP is 
> light years ahead anyway - P99SE is pretty broken in this case.
> 
> Ian


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