Re: [PEDA] 3D Models Online
Hey Jason, See my answers to your questions below. Q1: Is it worth doing? I've thought about the benefits of this previously. In my case however, I don't think it would be worth it. Having dealt with alot of offshore suppliers etc., we try to hedge our bets so to speak. We've been burned a few times when a plastics shooting company doesn't give the necessary clearances around components etc. As a result, when I model 3d components I generally model them as MMC + 0.4mm per side and MMC + 0.2mm height. This ensures that we get at least a minimal amount of clearance. Another issue (which could be overcome) is the level of detail of a part. For instance, I downloaded a model from Molex for their ZIF flex socket (51374) that has every feature modelled to the point where it can be opened and closed. For my purposes, this is far more detail than necessary and only slows down my CAD system. I only need the basic outer dimensions and enough detail for any mating parts (in the case of connectors etc.) It would also be far more beneficial to have the models in native CAD format rather than a generic format like .stp or .igs so that features can easily be removed or added. I typically like to set up my models so that they can be placed manually or used in an IDF conversion program. Therefore, I build them using the same reference locations as used for the part footprints in Protel. Q2: What do you think is a good price for a model of the following? I'll pass on this question for lack of experience. Q3: Would you use the service? Though I think it would be a beneficial service for some, I would prefer to keep our 3d modelling under my own control due to the uniqueness of the issues we face. However, I can see certain situations (such as a time crunch) where being able to download the model would be useful. I think the need for this service would increase if the Protel - 3d (IDF) conversions worked better (I've trialed IDF modeller, and use Qualecad, but only for Protel 99SE). Hope that helps, Darcy Davis Design Engineer, Dynastream Innovations, Inc. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] v large pcb document
If my memory serves me right, there is another trick here. I beleive Protel takes into account hidden comment and designator strings on the PCB when it attempts to find the boundary of your design. At least this has been my experience using Protel 99SE. The solution? If you can afford to turn on all designators (use a global change) you should be able to then see them and move them back into the board space and rehide them. If you've done much work organizing which comments and designators are hidden/shown than you won't want to do this. You could do a global select on all components where comment and designator are hidden. Again, use a global change to show all comments and designators and then fix the problem component. Once complete, rehide the comments/designators that are selected. Or, if you've got too many combinations of shown/hidden comments and designators just copy the design (or PCB) to another name and turn on all designators. You can then use this to determine which components are the problem and fix them selectively in your original design/PCB. By the sounds of it, you'll know the commands/menus to check and fix this if this is the problem. If you need more detailed instructions let me (or the list) know. Darcy Davis Design Engineer, Dynastream Innovations, Inc. -Original Message- From: Dave Courtney [mailto:[EMAIL PROTECTED] Sent: September 2, 2004 7:58 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] v large pcb document Thanks for the interesting thought but I don't think that is the problem. I did check for off sheet primitives with all layers on but nothing showed up. When I select 'View | Fit Document' the board becomes a small patch at the bottom left hand corner and the coordinates of the top right are X:9mil Y:99760mil. This would suggest that the document size has been maximized for some reason. The 'View | Board' and 'View | Sheet' options work fine. Can I move the layout onto a new board to fix this? Regards, Dave -Original Message- From: H. Selfridge [mailto:[EMAIL PROTECTED] Sent: 02 September 2004 06:37 To: Protel EDA Forum Subject: Re: [PEDA] v large pcb document This is a problem that crops up regularly in all versions of Protel. It is likely that, at some point in laying out your PCB, some primitive or component accidentally has been moved or placed outside your work area. It may even be on a layer that you have turned off, such as a mechanical layer used for notes or mechanical layout. First use turn on used layers to make sure all is visible. If you can't see the culprit, try using deselect all then select outside and draw your selection box around the perimeter of your desired board layout area. Now use shift delete to delete all selected items. Whatever is outside the selection box should be deleted. You can also try the same select outside and then drag the selection into visual range so you can delete it. At 03:42 PM 9/1/04, you wrote: I am using DXP +SP2 and have a PCB design where the document size is very much bigger than the board. Because of this I can't get a print preview or generate Gerber files. In the latter case I get a 'film too small' error. I don't know how the document size got changed but I would very much appreciate a way to reset it to the same as the sheet so I can make some output files. All suggestions welcome. Regards, Dave snip * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Missed messages (Was P99SE installation)
Has anybody else noticed that they're missing messages from the list server? I often read a response to a message I never got in the first place. For instance, I got John Ross's response to Alfonso's message below, but I never received the original message from Alfonso. In some cases, I haven't even seen my own message redistributed by the list server. I've taken this up with the administrator before, but wanted to find out if its a common occurance before I bring it up again. Darcy Davis Design Engineer, Dynastream Innovations, Inc. -Original Message- From: John A. Ross [Design] [mailto:[EMAIL PROTECTED] Sent: August 5, 2004 4:10 AM To: Protel EDA Forum Subject: Re: [PEDA] P99SE installation -Original Message- From: Alfonso Baz [mailto:[EMAIL PROTECTED] Sent: 05 August 2004 06:47 To: [EMAIL PROTECTED] Subject: [PEDA] P99SE installation I'm curious if anybody else has noticed the following when installing P99SE SP6 on either WIN2K or WINXP. Recently I upgraded my PC. I noticed after a clean OS install followed by installation of my usual software packages, windows Start-Help and Support didn't work. Also right-clicking My Computer on the desktop and selecting Manage failed to respond. Thanks to XP's system restore, I found the offending software installation. P99SE Alfonso I have XP here for some time now on all workstations (I suspect most others users now have XP also) and the ones with P99SE are fine, 2 of them also have DXP2004SP1 installed as well as other applications. Mixture Dell4500/4600 and 8200/8250/8300/8400's different PU speed and meory types (SD/RIMM/DDR) Never seen the issue you report. Sorry I cannot help, except to say that it should work. John * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] stopping second instance of 99SE
Hey Dennis, I can certainly understand your motivation here. We have a similar situation here, although I sometimes like being able to start more than one instance of 99SE as it allows me to reference one design on one monitor, and another on the other monitor. Forgive me if you were already aware of this, but instead of double-clicking the .ddb file, you can drag and drop it right into whichever instance of Protel you're working out of. Works great so long as you can override your instinct to double click. Darcy Davis Design Engineer, Dynastream Innovations, Inc. -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED] Sent: July 26, 2004 11:15 AM To: Protel EDA Forum Subject: Re: [PEDA] stopping second instance of 99SE i couldn't find the thread you mentioned either i wrote protel support about this we will see if they answer, so far not yet what is driving this in part is that we have a zillion projects all over the place in fairly complex directory structures we often open mnay DDBs for either design reference or to swipe details or parts if you use protel to drill around to open files, then aside from a lot of worthless time spent, it leaves protel pointing to the wrong folder for the next operation we have a couple of good file managers that will pop us to the right spot with minimal fuss so the working method here is to locate the file then apply it to the app, works great for autocad and PDFs and most other progs Dennis Saputelli [EMAIL PROTECTED] wrote: Steve, I think you may have misunderstood me. IFF my memory serves me correctly, the discussion was about disabling only the second execution, not dis-associating the .ddb extension from Protel or otherwise compromising the natural windows double-click execution of a program based on association(s). Though admittedly, is there isn't another method, then what you're suggesting is probably the only thing that Dennis can do to stop the second (or third...) instance from occurring when a .ddb file is double-clicked... aj -Original Message- From: Steve Wiseman [mailto:[EMAIL PROTECTED] Sent: Friday, July 23, 2004 6:49 PM To: Protel EDA Forum Subject: Re: [PEDA] stopping second instance of 99SE 23/07/2004 16:51:09, [EMAIL PROTECTED] wrote: I think I remember someone once-upon-a-time (Like Ian maybe?) saying that multiple instances was a defeatable within p99, either thru the ini files or perhaps a registry setting.. It's easy enough to just stop .ddb , .sch, .prj, .pcb and whatever else you're likely to double click on being associated with Protel. Fire up regedt32 (from task manager, if you can't find it elsewhere), then go to HKEY_LOCAL_MACHINE, SOFTWARE, Classes, and delete (click on, then hit 'DEL') .ddb and all the others you fancy killing off. That'll stop them launching Protel when you double-click, but Protel will still be entirely happy to open them. job done, without all this messing about with application launcher, counting copies, and the like. The icons may no longer be as pretty in file manager. Tough. Steve -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Board warpage?
Further to Steve's point on mechanical stresses on the components... The feasibility of the suggestion from your assembly house may depend on where in the process the boards warped. If the bare board was warped when the solder solidified on the components, then straightening the boards without reflowing the solder will place the components under stress. This will be the case even if no external force is applied to the board (ie, even if they are just soaked on a flat surface at 150F). If the bare boards warped as they cooled after reflow/wave, then it is likely that the solder solidified before the boards warped, causing the components to be under stress as we speak. If this is the case (unlikely), then straightening the boards would actually releive the stress. I haven't been in this business long enough to know how hard on components it would be to reflow them a second time. From a mechanical perspective, the best solution would be to reflow the solder, straighten the boards while the solder is still molten and then hold it straight till the boards cool. You might still need to go through a soak period at 150F before the boards would stay straight. Of coarse, running the components through an oven twice could do much more harm than good, not to mention the difficulty in straightening a board at 400 degrees. As Dennis suggested, be careful. Almost anything you do to these boards will shorten their life. Its just a question of how much, and what is the risk if they fail. Darcy Davis Design Engineer, Dynastream Innovations, Inc. -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Sent: July 20, 2004 9:55 AM To: [EMAIL PROTECTED] Subject: Re: [PEDA] Board warpage? In a message dated 2004-07-20 11:46:57 AM Eastern Daylight Time, [EMAIL PROTECTED] writes: A partner in a manufacturing effort is sending us full populated boards (ICs and passive components) that are badly warped. We sent them back and rather than get the boards remade and repopulate them, they want to heat the boards up (fully populated) for three days at 150 degrees Fahrenheit in order to straighten them out. These boards perform an extremely important job and I'm worried about the stress on both the electrical components and the boards themselves. Should I allow them to do this or should I demand the boards be remade? My answer would be, It depends. 150F is 65C, and most commercial spec electronics components are rated to operate up to 70C, and often rated to survive even hotter when unpowered. If all they want to do is let them sit on a flat surface at 150F for three days, and you've got a reliable test procedure for the boards before they go into a higher-level assembly, and you can spare the extra three days, I'd say quietly thank them for the extra burn-in. If they plan to apply some force to encourage the boards toward flatness, I'd be a lot more concerned, particularly given that trying to bend the boards with the solder already solidified will place some fairly large stresses on component leads, and at that temperature the plastic cases will be somewhat more yielding - possibly transferring the stresses to the internal bond wires. You might get some internal opens that way, but what would really worry me would be the possibily of getting an almost open, that would later fail under normal usage vibration. There would be a lot of other factors involved, like the potential cost of later field failures, product liability, your future relationship with this manufacturing partner, etc., that only you could evaluate. Steve Hendrix * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] SOT-23 pinout
I wasn't going to stick my neck out but...What works for us is to have a common PCB footprint (We use the same as Mira and others) and then we create a unique schematic part for each part# we use. The pins of the schematic part are mapped to the generic pad numbering in the layout footprint. While reviewing, I no longer bother to try figure out the mapping. I just pull up the datasheet and the PCB layout and check if the physical connection goes where I want it to. On a side note...until I started this process, we had to do the dead bug thing more than I care to admit. The worst part is that legacy [incorrect] footprints still exist in older designs waiting to strike the next time we rev a board. Don't get me going on the lack of clear datasheet mechanical information! Overconstrained parts, missing dimensions, lack of regard for controlling units etc. all make me see fuzzy. Technical drawings aren't that hard are they? ;-) Darcy Davis Design Engineer, Dynastream Innovations, Inc. -Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED] Sent: July 15, 2004 10:46 PM To: Protel EDA Forum Subject: Re: [PEDA] SOT-23 pinout On 02:15 PM 16/07/2004, Dennis Saputelli said: ..snip.. BTW remember the To92's that were ECB ? (or was it BCE ?) just get out a bit of sleeving and your solder sucker and you were all set quite a bit harder to deal with in the case of SOTs though I have seem prototypes with SOT-23 upside-down with the gull-wing legs bent to meet the board. It would have been done in a small production run except reverse pinned versions were available. Worse think about this was that another design done shortly after suffered the *same* problem - I couldn't believe the lack of care and attention to detail. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] SV: Licenses
I'd use mylar and tape if I could turn boards as fast and as cost effectively as with Protel. Unfortunately, doing 6 mil trace and space could be somewhat frustrating ;-) Ultimately 2004 has to pay for itself eventually if its going to be worth upgrading. From what I've read thus far, it would be awhile (if ever) before I could turn boards any faster in 2004 than in 99SE. Once I get up to speed, then it has to save me ~100 hours (depending on your loaded labour rate) or a couple board spins due to mistakes. Just to do the math for you, if it improved my efficiency by 10% (a pretty large improvement), it would take 900 hours on DXP2004 (1000 on 99se) for it to pay itself off. At 40 hours a week, thats 22.5 weeks. If you only use it 50% of the time, it would take a year for it to pay off (at which point we'd be deciding whether to upgrade to the next latest version). That's a somewhat simplified view, but it doesn't take into account the initial productivity hit while learning the new tool. For most companies, its a pretty difficult metric to gauge without actually trying it. The point remains...If I knew Altium was putting its resources into making the basic features better, I could be better assured that it would improve my productivity and therefore would be more likely to upgrade. I can't say whether its a good choice for Altium or not, but I can certainly tell you that for me, the new features just add to the cost without adding to productivity Darcy -Original Message- From: Protel Hell [mailto:[EMAIL PROTECTED] Sent: June 30, 2004 9:02 AM To: [EMAIL PROTECTED] Subject: Re: [PEDA] SV: Licenses I wouldn't agree with that, FPGA is kinda like Windows was in the mid 90's, the CAD that didn't make the transition either died or suffered. That's probably the main reaon PADS is #1, they were the first to be a true Windows ap. The others that didn't do it died, the ones that didn't do it quick enough floundered. Some stiil haven't done it right. With you guys refusing to move off your precious 99SE to DXP there wouldn't be anybody that wants DXP other than those who want it for it's FPGA capability. DXP is not efficient enough for board layout only, it has to offer SOMETHING other than it's low cost to hook people. They are trying to be a complete solution for the 21st century but you guys are stuck in the 1980's. Bring back the DOS version! may as well bring back mylar and tape! PH From: - [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Subject: [PEDA] SV: Licenses Date: Tue, 29 Jun 2004 22:03:32 +0200 If Altium/Protel had spent their development resources on their core business (SCH + PCB design tools) instead of believeing they could conquer the market providing all other dev. tools (simulation, fpga etc), they would have been no. 1 today. Regards A former Protel reseller -Oprindelig meddelelse- Fra: Protel Hell [mailto:[EMAIL PROTECTED] Sendt: 29. juni 2004 21:47 Til: [EMAIL PROTECTED] Emne: Re: [PEDA] Licenses Altiums Protel will never be number 1, it is just too cumbersome. Fine for people who have plenty of time but little $$ PH From: Joe Sapienza [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Subject: Re: [PEDA] Licenses Date: Tue, 29 Jun 2004 13:56:57 -0400 Mike, I doubt that PADS schematic can overtake anythingend comment With regard to Orcad yes in it's day (DOS) it was the absolute best, hands down. Something happened when it went to Windows then Cadence bought them and well.. Joe - Original Message - From: Mike Reagan [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Tuesday, June 29, 2004 1:48 PM Subject: Re: [PEDA] Licenses That is pretty interesting data gathered here. The interesting part is that Cadence has been successful in trashing OrCAD from number 1 to a has been. I doubt if PADs schematic has overtaken OrCad. Mike Reagan EDSI Frederick MD -Original Message- From: Tom Hausherr [mailto:[EMAIL PROTECTED] Sent: Tuesday, June 29, 2004 1:30 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] IPC-2581 IPC-7351. Bill, I just talked to Mentor Graphics PADS division and they say that since the 1st release of PADS Software in 1985 they have logged 85,000 licenses. PowerLogic (schematic) and PowerPCB (layout) are separate licenses. There are currently 18,000 PADS-PowerPCB seats on yearly maintenance. It's my personal guess that there are about 35,000 PADS-PowerPCB seats in use. There are many people using old licenses that are not on yearly maintenance due to financial hardships over the past 4 years. Tom Tom Hausherr PCB Libraries CEO, Director of Technology 858.592.4826 Phone 847.745.0450 Fax E-Mail: [EMAIL PROTECTED] Website: http://www.PCBLibraries.com
Re: [PEDA] SV: Licenses
Amen to that! I haven't used Protel that long, but overall, have been fairly happy with it. I basically learned Protel99SE completely on my own and find it to be a fairly intuitive package. Unfortunately, we're in the same boat as many others on the list, where we are evaluating the upgrade to DXP/2004 and trying to determine whether its worth it for us. Due to the kind of designs we layout, we primarily use the schematic capture and manual PCB routing features. We manually route all our designs due to the high density components and the need to lower production costs by using the oldest technology feasible. I would have liked Altium to spend its time improving these basic features rather than adding all the useless extras. The only two features I've found that I like so far in 2004 are the control of design varients, and the 3d modeling (since I have to do that entirely by hand as well). Darcy Davis Design Engineer, Dynastream Innovations, Inc. -Original Message- From: - [mailto:[EMAIL PROTECTED] Sent: June 29, 2004 2:04 PM To: Protel EDA Forum Subject: [PEDA] SV: Licenses If Altium/Protel had spent their development resources on their core business (SCH + PCB design tools) instead of believeing they could conquer the market providing all other dev. tools (simulation, fpga etc), they would have been no. 1 today. Regards A former Protel reseller -Oprindelig meddelelse- Fra: Protel Hell [mailto:[EMAIL PROTECTED] Sendt: 29. juni 2004 21:47 Til: [EMAIL PROTECTED] Emne: Re: [PEDA] Licenses Altiums Protel will never be number 1, it is just too cumbersome. Fine for people who have plenty of time but little $$ PH From: Joe Sapienza [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Subject: Re: [PEDA] Licenses Date: Tue, 29 Jun 2004 13:56:57 -0400 Mike, I doubt that PADS schematic can overtake anythingend comment With regard to Orcad yes in it's day (DOS) it was the absolute best, hands down. Something happened when it went to Windows then Cadence bought them and well.. Joe - Original Message - From: Mike Reagan [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Tuesday, June 29, 2004 1:48 PM Subject: Re: [PEDA] Licenses That is pretty interesting data gathered here. The interesting part is that Cadence has been successful in trashing OrCAD from number 1 to a has been. I doubt if PADs schematic has overtaken OrCad. Mike Reagan EDSI Frederick MD -Original Message- From: Tom Hausherr [mailto:[EMAIL PROTECTED] Sent: Tuesday, June 29, 2004 1:30 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] IPC-2581 IPC-7351. Bill, I just talked to Mentor Graphics PADS division and they say that since the 1st release of PADS Software in 1985 they have logged 85,000 licenses. PowerLogic (schematic) and PowerPCB (layout) are separate licenses. There are currently 18,000 PADS-PowerPCB seats on yearly maintenance. It's my personal guess that there are about 35,000 PADS-PowerPCB seats in use. There are many people using old licenses that are not on yearly maintenance due to financial hardships over the past 4 years. Tom Tom Hausherr PCB Libraries CEO, Director of Technology 858.592.4826 Phone 847.745.0450 Fax E-Mail: [EMAIL PROTECTED] Website: http://www.PCBLibraries.com http://www.PCBYellowPages.com -Original Message- From: Brooks,Bill [mailto:[EMAIL PROTECTED] Sent: Tuesday, June 29, 2004 9:50 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] IPC-2581 IPC-7351. I wonder just how many licensed seats there are of Protel in the world is that published anywhere? Also I wonder if Pads has published the same info? I didn't participate in the poll so it's at least off by one. LOL... I would venture to say Protel may have more seats that Pads... but they are mostly not in the Southwest of the U.S. How about it Altium... how many active seats of Protel are there? Bill Brooks PCB Design Engineer , C.I.D., C.I.I. Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 http://pcbwizards.com -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Sent: Tuesday, June 29, 2004 5:28 AM To: [EMAIL PROTECTED] Subject: Re: [PEDA] IPC-2581 IPC-7351. According to what statistical method? -Original Message- From: Tom Hausherr [mailto:[EMAIL PROTECTED] Sent: Monday, June 28, 2004 7:09 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] IPC-2581 IPC-7351. Ian, We took a poll and Protel is number two in worldwide installations (behind PADS). _ MSN Movies - Trailers, showtimes, DVD's, and the latest news from Hollywood! http://movies.msn.click-url.com/go/onm00200509ave/direct/01
[PEDA] 3d viewers.
Hey Guys, As a consumer products development company, we're continually trying to shrink our pcb into a smaller form factor. Therefore, it would be really nice to be able to export 3d files that we could assemble into 3d plastics models in order to do clearance checking etc. This is a necessity for us, however right now I do this manually. I know there are a couple products available as add-ons for Protel99SE. Has anybody used either View3d, or Protel IDF 3d Modeler from Desktop EDA? What do you think of them? Darcy Davis Design Engineer, Dynastream Innovations, Inc. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Warning and Violation count in DRC (Long post)
Hey Guys, I think this may have been discussed previously, but I couldn't find anything in the archives. When I run a manual DRC, I often get the line Violations Detected: 8, or sometimes a warning count instead, even though no violations are listed. Does anybody know what the violation/warning count refers to? I've pasted an example DRC report below. Thanks, Darcy Davis Design Engineer Dynastream Innovations, Inc. Protel Design System Design Rule Check PCB File : XX.pcb Date : 13-May-2004 Time : 08:53:43 Processing Rule : Component Clearance Constraint (Gap=-100mil) (Is in component D500 ),(Is in component D501 ) Rule Violations :0 Processing Rule : Clearance Constraint (Gap=0mil) (Is in component J202 ),(Is in component J202 ) Rule Violations :0 Processing Rule : Clearance Constraint (Gap=0mil) (Is in component J301 ),(Is in component J301 ) Rule Violations :0 Processing Rule : Short-Circuit Constraint (Allowed=Allowed) (Is on net AGND ),(Is on net GND ) Rule Violations :0 Processing Rule : Clearance Constraint (Gap=6mil) (Is a Via ),(Is a Smd Pad ) Rule Violations :0 Processing Rule : Hole Size Constraint (Min=0mil) (Max=200mil) (On the board ) Rule Violations :0 Processing Rule : Pads and Vias to follow the Drill pairs settings Rule Violations :0 Processing Rule : Width Constraint (Min=6mil) (Max=30mil) (Prefered=6mil) (On the board ) Rule Violations :0 Processing Rule : Broken-Net Constraint ( (On the board ) ) Rule Violations :0 Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board ) Rule Violations :0 Processing Rule : Clearance Constraint (Gap=10mil) (On the board ),(On layer BottomLayer And Is a Polygon ) Rule Violations :0 Processing Rule : Component Clearance Constraint (Gap=25mil) (On the board ),(On the board ) Rule Violations :0 Processing Rule : Component Clearance Constraint (Gap=0mil) (Is in component J301 ),(On the board ) Rule Violations :0 Processing Rule : Component Clearance Constraint (Gap=0mil) (Is in component J202 ),(On the board ) Rule Violations :0 Processing Rule : Clearance Constraint (Gap=460mil) (Is a Polygon ),(Is a Keep-Out ) Rule Violations :0 Processing Rule : Clearance Constraint (Gap=6mil) (On the board ),(On the board ) Rule Violations :0 Violations Detected : 8 Time Elapsed: 00:00:56 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DataBase Size too big!
This message is in MIME format. Since your mail reader does not understand this format, some or all of this message may not be legible. Click on the down arrow to the left of the file menu then go to design utilities. Click on the compact tab and browse to your database. AFAIK, access databases don't actually delete information until manually compacted. BTW, the design must be closed in the main explorer window for this to work. Darcy -Original Message- From: Michael Biggs [mailto:[EMAIL PROTECTED] Sent: May 10, 2004 9:20 AM To: Protel EDA Forum Subject: [PEDA] DataBase Size too big! After designing a PCB in 99SE SP6 and my database file keeps getting bigger. Of coarse I always save different file names of my design every so often. But here is my question, after I have deleted all the extra files and deleted my recycle bin files why is my database file still very large? I could start a new database with the extracted .pcb file and it seems to keep all the rules and preferences, but is this the only way? I know this has been discussed somewhere, I just couldn't find it in the archive. Thanks, Lomax always has good answersnay quick answers? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Need more software
Mike, I'd be really interested in more information on this if you're willing to share it. Darcy Davis Design Engineer, Dynastream Innovations, Inc. -Original Message- From: Mike Reagan [mailto:[EMAIL PROTECTED] Sent: April 14, 2004 9:15 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Need more software Mike wrote: [Snip] We found a way to create virtual components which are used as component keep outs to fool 99SE into thinking it was 3D. It works both online batch in 99SE. [Snip] Mike Reagan * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A DXP annotation feature?
I don't have an answer for you regarding the DXP stuff. However, I am running P99SE on WinXP. What did you mean by won't work? Darcy Davis Design Engineer, Dynastream Innovations, Inc. -Original Message- From: Ray Mitchell [mailto:[EMAIL PROTECTED] Sent: March 17, 2004 3:05 PM To: [EMAIL PROTECTED] Subject: [PEDA] A DXP annotation feature? I don't use DXP myself but a coworker here has no choice since 99SE won't work on WinXP. Anyway, when it came time to annotate his schematic to get rid of all the question mark designators he went through the standard procedure. When it was done he found that several schematic symbols had been arbitrarily moved to other pages and plopped down right in the middle of nowhere! In addition, some existing symbols had been duplicated and placed in arbitrary places on arbitrary pages. Therefore, his solution is to simply go through all 12 pages of his schematic every time he annotates in order to correct DXP's errors (or should this be considered a feature?). Has anyone seen this behavior? Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Placing Components on top of each other
Hey Guys,
I just thought I'd add my support that you can place components on top of
each other. We do it all the time for various different reasons. I typically
use a 0mil clearance instead of a negative value however. Additionally, I've
found that in order for the DRC to work correctly, I sometimes have to run
it a couple times. I made a sample file so I could verify that it still
works (you never know!). I'm assuming I can't distribute it via the list,
but anyone who is interested can let me know.
Darcy
-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]
Sent: March 2, 2004 2:52 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Placing Components on top of each other
On 08:17 PM 2/03/2004, Jason Morgan said:
You need to use a negative component clearance rule distance.
e.g.
IsFootprint('Footprint1') and IsFootprint('footprint2')
Clearance = -5000mil
You need to enable 'Full' clearance rule checking which can be slow.
Trent,
Looks like Jason is using DXP queries as shorthand, but there is footprint
scope in P99SE so it is should be easy enough to convert.
Jason,
Negative component clearance checking has never worked for me in P99SE or
DXP. I would love a simple example PCB that shows negative component
working. This has been a pain for me for ever. Any chance of making up a
sample design, Jason?
Thanks,
Ian
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Re: [PEDA] PCB ascii files.
Yeah, I've got ~100 GBs free right now. The design used to be stored on a network drive (though the incriminating file was a local temp file). I just tried moving the design to a local folder and got the same result. I'm wondering whether its a limitation that windows puts on the profile for each user. I'm going to see if I can redirect Protel to use a different folder for its temporary files. BTW, it may be a silly question to an experienced user. But, on a list, you never know the users skill level. Even then, it could have been a simple answer I overlooked...I've learned by experience that If it doesn't work...check that its plugged in. Darcy -Original Message- From: Terry Creer [mailto:[EMAIL PROTECTED] Sent: February 25, 2004 9:19 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] PCB ascii files. Silly question, I know - but have you got enough hard-drive space available? TC -Original Message- From: Darcy Davis [mailto:[EMAIL PROTECTED] Sent: Wednesday, February 25, 2004 4:27 PM To: [EMAIL PROTECTED] Subject: [PEDA] PCB ascii files. Hey Folks, I've been getting an error while trying to save a PCB file in ascii format in Protel 99SE sp6. I get the message Design Explorer Error! File C:\\Temp\xxx.tmp is too large. When I track down this file, I find it to be 53,259,703 bytes. (50.7Mb). I know this process works on smaller designs. I can delete polygons etc from the design and eventually it will work, but it certainly isn't a good design practice. I've already tried things like using a different computer, closing all other programs/files, cut/paste into a new pcb file. I can't seem to find a clean way around this problem. I'm currently running Protel 99SE under windows xp on a P4 2.8GHz with 1Gig of ram, so I don't think its a lack of resources. Any ideas? Does Protel DXP solve this problem? Thanks, Darcy * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
