changeset f15f02d8c79e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f15f02d8c79e
description:
mem: Split the hit_latency into tag_latency and data_latency
If the cache access mode is parallel, i.e. "sequential_access" parameter
is set to "False", ta
sit:
http://reviews.gem5.org/r/3502/#review8995
---
On oct. 27, 2016, 11:25 matin, Sophiane SENNI wrote:
>
> ---
> This is an automatically generated e-mail. To re
rc/mem/cache/tags/fa_lru.cc 4aac82f10951
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using --Debug-flags=Cache
Thanks,
Sophiane SENNI
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rc/mem/cache/tags/fa_lru.cc 4aac82f10951
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using --Debug-flags=Cache
Thanks,
Sophiane SENNI
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e-mail. To reply, visit:
http://reviews.gem5.org/r/3502/#review8960
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On oct. 24, 2016, 2:56 après-midi, Sophiane SENNI wrote:
>
> ---
> This is an automatically generated e-m
iff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using --Debug-flags=Cache
Thanks,
Sophiane SENNI
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ms to me this code is not right, as it checks if the data is
> > technically written now, but we only need the data at time T.
> >
> > Should we not rather add the dataLatency to the blk->whenReady and then
> > do the plus or max opteration?
>
>
> On juil. 25, 2016, 1:18 après-midi, Nikos Nikoleris wrote:
> > Ship It!
>
> Sophiane SENNI wrote:
> How can I commit the patch ? I am not sure I have the commit access ?
>
> Nikos Nikoleris wrote:
> You can't commit it youself, one of the maintainers w
> On juil. 25, 2016, 1:18 après-midi, Nikos Nikoleris wrote:
> > Ship It!
>
> Sophiane SENNI wrote:
> How can I commit the patch ? I am not sure I have the commit access ?
>
> Nikos Nikoleris wrote:
> You can't commit it youself, one of the maintainers w
812689280e7a8fa842
src/mem/cache/tags/base_set_assoc.hh 4aac82f109517217e6bfb3812689280e7a8fa842
src/mem/cache/tags/fa_lru.cc 4aac82f109517217e6bfb3812689280e7a8fa842
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using --Debug-flags=Cache
Thanks,
Sophiane SENNI
;whenReady?
I we care about blk->whenReady in base_set_assoc.hh, I assume we have also to
care about it here.
- Sophiane
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This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3502/#review8552
> On juil. 25, 2016, 1:18 après-midi, Nikos Nikoleris wrote:
> > Ship It!
>
> Sophiane SENNI wrote:
> How can I commit the patch ? I am not sure I have the commit access ?
>
> Nikos Nikoleris wrote:
> You can't commit it youself, one of the maintainers w
> On juil. 25, 2016, 1:18 après-midi, Nikos Nikoleris wrote:
> > Ship It!
>
> Sophiane SENNI wrote:
> How can I commit the patch ? I am not sure I have the commit access ?
>
> Nikos Nikoleris wrote:
> You can't commit it youself, one of the maintainers w
> On juil. 25, 2016, 1:18 après-midi, Nikos Nikoleris wrote:
> > Ship It!
>
> Sophiane SENNI wrote:
> How can I commit the patch ? I am not sure I have the commit access ?
>
> Nikos Nikoleris wrote:
> You can't commit it youself, one of the maintainers w
sit:
http://reviews.gem5.org/r/3502/#review8525
---
On juil. 25, 2016, 1:16 après-midi, Sophiane SENNI wrote:
>
> ---
> This is an automatically generated e-mail. To reply, visit:
> ht
----
On juil. 25, 2016, 1:16 après-midi, Sophiane SENNI wrote:
>
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3502/
> --
a985b5fd56cb5b2708
src/mem/cache/tags/base_set_assoc.hh 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using --Debug-flags=Cache
Thanks,
Sophiane SENNI
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cbf7aa985b5fd56cb5b2708
src/mem/cache/tags/fa_lru.cc 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using --Debug-flags=Cache
Thanks,
Sophiane SENNI
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he
> > flag sequentialAccess and the condition lookupLatency >= dataLantency
> > shouldn't change during the simulation.
>
> Sophiane SENNI wrote:
> I think this code should be left here. Because the total access latency
> now depends on both tag_latency and
he
> > flag sequentialAccess and the condition lookupLatency >= dataLantency
> > shouldn't change during the simulation.
>
> Sophiane SENNI wrote:
> I think this code should be left here. Because the total access latency
> now depends on both tag_latency and
he
> > flag sequentialAccess and the condition lookupLatency >= dataLantency
> > shouldn't change during the simulation.
>
> Sophiane SENNI wrote:
> I think this code should be left here. Because the total access latency
> now depends on both tag_latency and
80e79ae636ca6b021cbf7aa985b5fd56cb5b2708
src/mem/cache/tags/Tags.py 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708
src/mem/cache/base.cc 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using --Deb
80e79ae636ca6b021cbf7aa985b5fd56cb5b2708
src/mem/cache/tags/base.hh 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708
src/mem/cache/tags/base.cc 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using --Debug-flags=Cache
Thanks,
Sophiane SENNI
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3502/#review8441
---
On juin 20, 2016, 3:07 après-midi, Sophiane SENNI wrote:
>
> ---
> This is an automatically generated e-mail. To reply, v
and "ram_latency" is also not very clear.
> > Maybe something like "tag_latency" and "line_latency" could be better ? I
> > think the two parts of a cache are well identified in this example.
>
> Sophiane SENNI wrote:
> Hi Pierre-Yves,
>
80e79ae636ca6b021cbf7aa985b5fd56cb5b2708
src/mem/cache/tags/fa_lru.cc 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using --Debug-flags=Cache
Thanks,
Sophiane SENNI
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y" could be a solution.
Any feedback from other gem5 users would be useful.
Sophiane
- Sophiane
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http://reviews.gem5.org/r/3502/#review8419
------
t_assoc.hh 80e79ae636ca
src/mem/cache/tags/base.hh 80e79ae636ca
configs/common/Caches.py 80e79ae636ca
src/mem/cache/Cache.py 80e79ae636ca
src/mem/cache/base.hh 80e79ae636ca
src/mem/cache/base.cc 80e79ae636ca
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using
o use the "-o" option on the extension.
> >
> > Cheers!
>
> Sophiane SENNI wrote:
> Hi Jason,
>
> If I use the hg postreview extension (with the following command hg
> postreview -o -u -e 3502), all the patch does not apply cleanly.
>
> J
o use the "-o" option on the extension.
> >
> > Cheers!
>
> Sophiane SENNI wrote:
> Hi Jason,
>
> If I use the hg postreview extension (with the following command hg
> postreview -o -u -e 3502), all the patch does not apply cleanly.
>
> J
em/cache/tags/Tags.py UNKNOWN
src/mem/cache/base.hh UNKNOWN
src/mem/cache/base.cc UNKNOWN
src/mem/cache/BaseCache.py UNKNOWN
configs/common/Caches.py UNKNOWN
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using --Deb
-
This is an automatically generated e-mail. To reply, visit:
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---
On juin 16, 2016, 3:15 après-midi, Sophiane SENNI wrote:
>
> ---
&g
src/mem/cache/tags/base_set_assoc.hh 629fe6e6c781ec542bcd1cfda0217dfc51c4826b
src/mem/cache/tags/fa_lru.hh 629fe6e6c781ec542bcd1cfda0217dfc51c4826b
src/mem/cache/tags/fa_lru.cc 629fe6e6c781ec542bcd1cfda0217dfc51c4826b
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using --Deb
src/mem/cache/tags/base.hh 629fe6e6c781
src/mem/cache/tags/base.cc 629fe6e6c781
src/mem/cache/tags/base_set_assoc.hh 629fe6e6c781
src/mem/cache/tags/fa_lru.hh 629fe6e6c781
src/mem/cache/tags/fa_lru.cc 629fe6e6c781
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using
hh UNKNOWN
src/mem/cache/tags/base.cc UNKNOWN
src/mem/cache/tags/base_set_assoc.hh UNKNOWN
src/mem/cache/tags/fa_lru.hh UNKNOWN
src/mem/cache/tags/fa_lru.cc UNKNOWN
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using --Deb
py 629fe6e6c781
src/mem/cache/base.hh 629fe6e6c781
src/mem/cache/base.cc 629fe6e6c781
src/mem/cache/tags/Tags.py 629fe6e6c781
src/mem/cache/tags/base.hh 629fe6e6c781
src/mem/cache/tags/base.cc 629fe6e6c781
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using
629fe6e6c781
src/mem/cache/tags/Tags.py 629fe6e6c781
src/mem/cache/tags/base.hh 629fe6e6c781
src/mem/cache/tags/base.cc 629fe6e6c781
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using --Debug-flags=Cache
Thanks,
Sophiane SENNI
oc.hh 629fe6e6c781
src/mem/cache/tags/fa_lru.cc 629fe6e6c781
src/mem/cache/tags/fa_lru.hh 629fe6e6c781
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
---
Tested using --Debug-flags=Cache
Thanks,
Sophiane SENNI
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ge
p://reviews.gem5.org/r/2109/#review5106
---
On Dec. 6, 2013, 11:09 a.m., Sophiane SENNI wrote:
>
> ---
> This is an automatically generated e-mail. To reply, vis
check read hit latency and write hit latency
for Dcache and Icache. I checked the time between a request sent by the cpu and
the response sent by the cache memory.
Thanks,
Sophiane SENNI
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(updated)
-
src/mem/SimpleDRAM.py 5e8970397ab7
src/mem/simple_dram.hh 5e8970397ab7
src/mem/simple_dram.cc 5e8970397ab7
Diff: http://reviews.gem5.org/r/2109/diff/
Testing
---
Thanks,
Sophiane SENNI
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om the memory side) in the cache takes place. Note that the fill
> > takes multiple bus cycles, thus, the write latency should take this into
> > account.
> >
> > As a last thing, maybe a new parameter should be added, i.e.,
> > writeResponseLatency.
> >
nk you very much for your post. I will try to complete this patch and post
an update.
- Sophiane
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Testing
---
I used --debug-flags command to check read hit latency and write hit latency
for Dcache and Icache. I checked the time between a request sent by the cpu and
the response sent by the cache memory.
Thanks,
Sophiane SENNI
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