[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fix memory leak problem in page table walker
Luming Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56609 )
Change subject: arch-riscv: fix memory leak problem in page table walker
..
arch-riscv: fix memory leak problem in page table walker
Valgrind detects memory leak problems in RISC-V's page table
walker(`Walker::WalkerState::stepWalk()`). In some situation,
the response packet is not freed. This patch partially fix
these memory leak problems.
Change-Id: I86d4c69c3c502bd92856a3d8863bfa1722a94512
---
M src/arch/riscv/pagetable_walker.cc
1 file changed, 20 insertions(+), 0 deletions(-)
diff --git a/src/arch/riscv/pagetable_walker.cc
b/src/arch/riscv/pagetable_walker.cc
index 81d1eb2..43adf78 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -426,6 +426,10 @@
//If we didn't return, we're setting up another read.
RequestPtr request = std::make_shared(
nextRead, oldRead->getSize(), flags, walker->requestorId);
+
+delete oldRead;
+oldRead = NULL;
+
read = new Packet(request, MemCmd::ReadReq);
read->allocate();
@@ -501,6 +505,8 @@
}
sendPackets();
} else {
+delete pkt;
+
sendPackets();
}
if (inflight == 0 && read == NULL && writes.size() == 0) {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I86d4c69c3c502bd92856a3d8863bfa1722a94512
Gerrit-Change-Number: 56609
Gerrit-PatchSet: 1
Gerrit-Owner: Luming Wang
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim,tests: Add unit test for Globals
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/43593 )
Change subject: sim,tests: Add unit test for Globals
..
sim,tests: Add unit test for Globals
Add a unit test for sim/globals.
Change-Id: Ia47e750df4cbdb91a0ab0498819f4e3451d74830
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43593
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M src/sim/SConscript
A src/sim/globals.test.cc
2 files changed, 184 insertions(+), 0 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/SConscript b/src/sim/SConscript
index 8bf5f5d..371eccd 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -92,6 +92,8 @@
env.TagImplies('gem5 serialize', 'gem5 trace')
GTest('byteswap.test', 'byteswap.test.cc', '../base/types.cc')
+GTest('globals.test', 'globals.test.cc', 'globals.cc',
+with_tag('gem5 serialize'))
GTest('guest_abi.test', 'guest_abi.test.cc')
GTest('port.test', 'port.test.cc', 'port.cc')
GTest('proxy_ptr.test', 'proxy_ptr.test.cc')
diff --git a/src/sim/globals.test.cc b/src/sim/globals.test.cc
new file mode 100644
index 000..8900c19
--- /dev/null
+++ b/src/sim/globals.test.cc
@@ -0,0 +1,166 @@
+/*
+ * Copyright 2022 Daniel R. Carvalho
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include
+
+#include
+
+#include "base/gtest/cur_tick_fake.hh"
+#include "base/gtest/logging.hh"
+#include "base/gtest/serialization_fixture.hh"
+#include "sim/globals.hh"
+
+// The version tags are declared as extern
+namespace gem5
+{
+std::set version_tags;
+} // namespace gem5
+
+using namespace gem5;
+
+// Use the tick handled to manipulate the current tick
+GTestTickHandler tickHandler;
+
+using GlobalsSerializationFixture = SerializationFixture;
+using GlobalsSerializationFixtureDeathTest = GlobalsSerializationFixture;
+
+/** Test serialization. */
+TEST_F(GlobalsSerializationFixture, Serialization)
+{
+Globals globals;
+tickHandler.setCurTick(1234);
+version_tags = { "first-tag", "second-tag", "third-tag", "fourth-tag"
};
+
+// Serialization
+std::ofstream cp(getCptPath());
+Serializable::ScopedCheckpointSection scs(cp, "Section1");
+globals.serialize(cp);
+
+// The checkpoint must be flushed, otherwise the file may not be up-
+// to-date and the assertions below will fail
+cp.close();
+
+// Verify the output
+std::ifstream is(getCptPath());
+assert(is.good());
+std::string str = std::string(std::istreambuf_iterator(is),
+std::istreambuf_iterator());
+ASSERT_THAT(str, ::testing::StrEq("\n[Section1]\ncurTick=1234\n"
+"version_tags=first-tag fourth-tag second-tag third-tag\n"));
+}
+
+/** Test unserialization. */
+TEST_F(GlobalsSerializationFixture, Unserialization)
+{
+version_tags = { "first-tag-un", "second-tag-un", "third-tag-un",
+"fourth-tag-un" };
+simulateSerialization("\n[Section1]\ncurTick=\nversion_tags="
+"first-tag-un second-tag-un third-tag-un fourth-tag-un\n");
+
+Globals globals;
+CheckpointIn cp(getDirName());
+Serializable::ScopedCheckpointSection scs(cp, "Section1");
+
+gtestLogOutput.str("");
+globals.unserialize(cp);
+ASSERT_THAT(gtestLogOutput.str(), ::testing::StrEq(""));
+
[gem5-dev] Change in gem5/gem5[develop]: sim,tests: Add a tag for gem5 events
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44107 )
Change subject: sim,tests: Add a tag for gem5 events
..
sim,tests: Add a tag for gem5 events
This tag can be used to determine which files are needed
when sim/eventq.hh is included in a header file. For
example, when declaring a unit test, this tag makes
the SConscript declaration much simpler.
Change-Id: If68ddf94975dbe9f7121fefb6051a8bbaca19c4b
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44107
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M src/base/SConscript
M src/sim/SConscript
2 files changed, 22 insertions(+), 2 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/SConscript b/src/base/SConscript
index c49e2ae..21ebde9 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -40,7 +40,7 @@
Source('cprintf.cc', add_tags='gtest lib')
GTest('cprintf.test', 'cprintf.test.cc')
Executable('cprintftime', 'cprintftime.cc', 'cprintf.cc')
-Source('debug.cc', add_tags='gem5 trace')
+Source('debug.cc', add_tags=['gem5 trace', 'gem5 events'])
GTest('debug.test', 'debug.test.cc', 'debug.cc')
if env['HAVE_FENV']:
Source('fenv.cc')
diff --git a/src/sim/SConscript b/src/sim/SConscript
index 371eccd..c0951f3 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -53,7 +53,7 @@
Source('cxx_config_ini.cc')
Source('debug.cc')
Source('py_interact.cc', add_tags='python')
-Source('eventq.cc')
+Source('eventq.cc', add_tags='gem5 events')
Source('futex_map.cc')
Source('global_event.cc')
Source('globals.cc')
@@ -89,6 +89,7 @@
Source('workload.cc')
Source('mem_pool.cc')
+env.TagImplies('gem5 events', ['gem5 serialize', 'gem5 trace'])
env.TagImplies('gem5 serialize', 'gem5 trace')
GTest('byteswap.test', 'byteswap.test.cc', '../base/types.cc')
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If68ddf94975dbe9f7121fefb6051a8bbaca19c4b
Gerrit-Change-Number: 44107
Gerrit-PatchSet: 13
Gerrit-Owner: Daniel Carvalho
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add TLB invalidation flags to the Request object
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56596 )
Change subject: mem: Add TLB invalidation flags to the Request object
..
mem: Add TLB invalidation flags to the Request object
Some ISAs implement TLB invalidation across multiple cores (TLB
shootdown) by broadcasting invalidation messages to every PE in a
target shareability domain.
These messages originate by specific instructions and can be
cathegorized in two macro groups
1) TLB Invalidation instructions: generating the invalidation
request
Example:
* Arm: TLBI instruction [1]
* AMD64: INVLPGB instruction [2]
2) TLB Invalidation sync instructions: serialization point, ensuring
completion of outstanding invalidation requests
Example:
* Arm: DSB instruction [1]
* AMD64: TLBSYNC instruction [2]
This patch is introducing TLBI and SYNC operations in the memory
subsystem by adding the following Request flags:
* TLBI (1)
* TLBI_SYNC (2)
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
[1]: https://developer.arm.com/documentation/ddi0487/gb/
[2]: https://www.amd.com/system/files/TechDocs/24594.pdf
Change-Id: Ib5b025d0f6bc0edaf4f11a66593947a72ba32b8f
---
M src/mem/request.hh
1 file changed, 54 insertions(+), 1 deletion(-)
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 3b884a9..867cbb0 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013,2017-2020 ARM Limited
+ * Copyright (c) 2012-2013,2017-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -237,6 +237,12 @@
// This separation is necessary to ensure the disjoint components
// of the system work correctly together.
+/** The Request is a TLB shootdown */
+TLBI= 0x1000,
+
+/** The Request is a TLB shootdown sync */
+TLBI_SYNC = 0x2000,
+
/**
* These flags are *not* cleared when a Request object is
* reused (assigned a new address).
@@ -249,6 +255,8 @@
static const FlagsType HTM_CMD = HTM_START | HTM_COMMIT |
HTM_CANCEL | HTM_ABORT;
+static const FlagsType TLBI_CMD = TLBI | TLBI_SYNC;
+
/** Requestor Ids that are statically allocated
* @{*/
enum : RequestorID
@@ -975,6 +983,10 @@
isHTMCancel() || isHTMAbort());
}
+bool isTlbi() const { return _flags.isSet(TLBI); }
+bool isTlbiSync() const { return _flags.isSet(TLBI_SYNC); }
+bool isTlbiCmd() const { return isTlbi() || isTlbiSync(); }
+
bool
isAtomic() const
{
--
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Gerrit-Change-Id: Ib5b025d0f6bc0edaf4f11a66593947a72ba32b8f
Gerrit-Change-Number: 56596
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Handle Request::NO_ACCESS flag in MinorCPU and O3CPU
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56591 )
Change subject: cpu: Handle Request::NO_ACCESS flag in MinorCPU and O3CPU
..
cpu: Handle Request::NO_ACCESS flag in MinorCPU and O3CPU
The Request::NO_ACCESS flag instructs the cpu model to not issue
the request to the memory port.
While Atomic and Timing CPU models properly implement it [1], [2],
* MinorCPU is not looking at the flag
* O3CPU is looking at the flag only in case of a nested transaction
start/commit
This patch is extending NO_ACCESS support to all memory instructions.
This is achieved by using the localAccess callback in the Request object.
Handling of nested hardware transactions in the O3 LSQUnit is moved within
the local accessor callback
[1]: https://github.com/gem5/gem5/blob/v21.1.0.2/\
src/cpu/simple/timing.cc#L318
[2]: https://github.com/gem5/gem5/blob/v21.1.0.2/\
src/cpu/simple/atomic.cc#L396
Change-Id: Ifd5b388c53ead4fe358aa35d2197c12f1c5bb4f2
Signed-off-by: Giacomo Travaglini
---
M src/cpu/minor/lsq.cc
M src/cpu/o3/lsq.cc
M src/cpu/o3/lsq_unit.cc
3 files changed, 56 insertions(+), 33 deletions(-)
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index e4c000b..17ae290 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014,2017-2018,2020 ARM Limited
+ * Copyright (c) 2013-2014,2017-2018,2020-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1651,6 +1651,14 @@
inst->pc->instAddr(), std::move(amo_op));
request->request->setByteEnable(byte_enable);
+/* If the request is marked as NO_ACCESS, setup a local access
+ * doing nothing */
+if (flags.isSet(Request::NO_ACCESS)) {
+assert(!request->request->isLocalAccess());
+request->request->setLocalAccessor(
+[] (ThreadContext *tc, PacketPtr pkt) { return Cycles(1); });
+}
+
requests.push(request);
inst->inLSQ = true;
request->startAddrTranslation();
diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
index 72ecc52..c932a93 100644
--- a/src/cpu/o3/lsq.cc
+++ b/src/cpu/o3/lsq.cc
@@ -1089,6 +1089,23 @@
_inst->pcState().instAddr(), _inst->contextId(),
std::move(_amo_op));
req->setByteEnable(byte_enable);
+
+/* If the request is marked as NO_ACCESS, setup a local access */
+if (_flags.isSet(Request::NO_ACCESS)) {
+req->setLocalAccessor(
+[this, req](gem5::ThreadContext *tc, PacketPtr pkt) ->
Cycles
+{
+if ((req->isHTMStart() || req->isHTMCommit())) {
+auto& inst = this->instruction();
+assert(inst->inHtmTransactionalState());
+pkt->setHtmTransactional(
+inst->getHtmTransactionUid());
+}
+return Cycles(1);
+}
+);
+}
+
_reqs.push_back(req);
}
}
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index 1541d2c..856cef3 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -1336,7 +1336,6 @@
if (request->mainReq()->isLocalAccess()) {
assert(!load_inst->memData);
-assert(!load_inst->inHtmTransactionalState());
load_inst->memData = new uint8_t[MaxDataBytes];
gem5::ThreadContext *thread = cpu->tcBase(lsqID);
@@ -1351,37 +1350,6 @@
return NoFault;
}
-// hardware transactional memory
-if (request->mainReq()->isHTMStart() ||
request->mainReq()->isHTMCommit())
-{
-// don't want to send nested transactionStarts and
-// transactionStops outside of core, e.g. to Ruby
-if (request->mainReq()->getFlags().isSet(Request::NO_ACCESS)) {
-Cycles delay(0);
-PacketPtr data_pkt =
-new Packet(request->mainReq(), MemCmd::ReadReq);
-
-// Allocate memory if this is the first time a load is issued.
-if (!load_inst->memData) {
-load_inst->memData =
-new uint8_t[request->mainReq()->getSize()];
-// sanity checks espect zero in request's data
-memset(load_inst->memData, 0,
request->mainReq()->getSize());
-}
-
-data_pkt->dataStatic(load_inst->memData);
-if (load_inst->inHtmTransactionalState()) {
-data_pkt->setHtmTransactional(
-load_inst->getHtmTransactionUid());
-}
-data_pkt->makeResponse();
-
-WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt,
this);
-cpu->schedule(wb, cpu->clockEdge(delay));
-return NoFault;
-}
-}
-
// Check the SQ for any
[gem5-dev] Change in gem5/gem5[develop]: cpu: Allow TLB shootdown requests in the timing cpu
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56599 )
Change subject: cpu: Allow TLB shootdown requests in the timing cpu
..
cpu: Allow TLB shootdown requests in the timing cpu
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: Ied38e9ed1f02d8e48bc5d62cc34baaec740bf6b8
Signed-off-by: Giacomo Travaglini
---
M src/cpu/simple/timing.cc
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index d791e3f..9e29cde 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1236,7 +1236,7 @@
req->taskId(taskId());
req->setInstCount(t_info.numInst);
-assert(req->isHTMCmd());
+assert(req->isHTMCmd() || req->isTlbiCmd());
// Use the payload as a sanity check,
// the memory subsystem will clear allocated data
@@ -1246,14 +1246,19 @@
memcpy (data, , size);
// debugging output
-if (req->isHTMStart())
-DPRINTF(HtmCpu, "HTMstart htmUid=%u\n",
t_info.getHtmTransactionUid());
-else if (req->isHTMCommit())
-DPRINTF(HtmCpu, "HTMcommit htmUid=%u\n",
t_info.getHtmTransactionUid());
-else if (req->isHTMCancel())
-DPRINTF(HtmCpu, "HTMcancel htmUid=%u\n",
t_info.getHtmTransactionUid());
-else
-panic("initiateHtmCmd: unknown CMD");
+if (req->isHTMCmd()) {
+if (req->isHTMStart())
+DPRINTF(HtmCpu, "HTMstart htmUid=%u\n",
+t_info.getHtmTransactionUid());
+else if (req->isHTMCommit())
+DPRINTF(HtmCpu, "HTMcommit htmUid=%u\n",
+t_info.getHtmTransactionUid());
+else if (req->isHTMCancel())
+DPRINTF(HtmCpu, "HTMcancel htmUid=%u\n",
+t_info.getHtmTransactionUid());
+else
+panic("initiateSpecialMemCmd: unknown HTM CMD");
+}
sendData(req, data, nullptr, true);
--
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Gerrit-Change-Id: Ied38e9ed1f02d8e48bc5d62cc34baaec740bf6b8
Gerrit-Change-Number: 56599
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Rename initiateHtmCmd to be more generic
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56598 )
Change subject: cpu: Rename initiateHtmCmd to be more generic
..
cpu: Rename initiateHtmCmd to be more generic
To prepare for future CHI work, rename ExecContext::initiateHtmCmd to
ExecContext::initiateSpecialMemCmd
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I7c7aed8ec06a66d9023c14dba37eae42907df222
---
M src/arch/arm/insts/tme64ruby.cc
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/dyn_inst.cc
M src/cpu/o3/dyn_inst.hh
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
11 files changed, 55 insertions(+), 31 deletions(-)
diff --git a/src/arch/arm/insts/tme64ruby.cc
b/src/arch/arm/insts/tme64ruby.cc
index 12cc878..95a7da2 100644
--- a/src/arch/arm/insts/tme64ruby.cc
+++ b/src/arch/arm/insts/tme64ruby.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -77,7 +77,7 @@
memAccessFlags = memAccessFlags | Request::NO_ACCESS;
}
-fault = xc->initiateHtmCmd(memAccessFlags);
+fault = xc->initiateSpecialMemCmd(memAccessFlags);
}
return fault;
@@ -175,7 +175,7 @@
Request::Flags memAccessFlags =
Request::STRICT_ORDER|Request::PHYSICAL|Request::HTM_CANCEL;
-fault = xc->initiateHtmCmd(memAccessFlags);
+fault = xc->initiateSpecialMemCmd(memAccessFlags);
return fault;
}
@@ -231,7 +231,7 @@
memAccessFlags = memAccessFlags | Request::NO_ACCESS;
}
-fault = xc->initiateHtmCmd(memAccessFlags);
+fault = xc->initiateSpecialMemCmd(memAccessFlags);
return fault;
}
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index b76c034..15a93f9 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -335,7 +335,7 @@
};
Fault
-initiateHtmCmd(Request::Flags flags) override
+initiateSpecialMemCmd(Request::Flags flags) override
{
panic("not yet supported!");
return NoFault;
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index b88c895..781b500 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, 2016-2018, 2020 ARM Limited
+ * Copyright (c) 2014, 2016-2018, 2020-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -218,10 +218,14 @@
}
/**
- * Initiate an HTM command,
- * e.g. tell Ruby we're starting/stopping a transaction
+ * Initiate a Special memory command,
+ * which bypasses squashing and has no address.
+ * Examples include HTM commands and TLBI commands.
+ * e.g. tell Ruby we're starting/stopping a HTM transaction,
+ * or tell Ruby to issue a TLBI operation
*/
-virtual Fault initiateHtmCmd(Request::Flags flags) = 0;
+virtual Fault initiateSpecialMemCmd(Request::Flags flags) = 0;
+
/**
* For atomic-mode contexts, perform an atomic memory write operation.
* For timing-mode contexts, initiate a timing memory write operation.
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 2773f9e..bf9b4b4 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2014, 2016-2018, 2020 ARM Limited
+ * Copyright (c) 2011-2014, 2016-2018, 2020-2021 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -117,9 +117,10 @@
}
Fault
-initiateHtmCmd(Request::Flags flags) override
+initiateSpecialMemCmd(Request::Flags flags) override
{
-panic("ExecContext::initiateHtmCmd() not implemented on
MinorCPU\n");
+panic("ExecContext::initiateSpecialMemCmd() not implemented "
+ " on MinorCPU\n");
return NoFault;
}
diff --git a/src/cpu/o3/dyn_inst.cc b/src/cpu/o3/dyn_inst.cc
index 4769896..8eb270a 100644
--- a/src/cpu/o3/dyn_inst.cc
+++ b/src/cpu/o3/dyn_inst.cc
@@ -410,7 +410,7 @@
}
Fault
-DynInst::initiateHtmCmd(Request::Flags flags)
+DynInst::initiateSpecialMemCmd(Request::Flags flags)
{
const unsigned int size = 8;
return cpu->pushRequest(
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index f97a525..0d4a56f 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2016 ARM Limited
+ * Copyright (c) 2010, 2016, 2021 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -397,7 +397,7 @@
Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add DVM enabled flag in the ExtMachInst/Decoder class
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56603 )
Change subject: arch-arm: Add DVM enabled flag in the ExtMachInst/Decoder
class
..
arch-arm: Add DVM enabled flag in the ExtMachInst/Decoder class
This is needed as the decoder needs to choose whether to
instantiate a DVM (treated as IsLoad) instruction when
decoding a TLBI/DSB Shareable, or to issue a simple system
instruction in case DVM messages are not modelled in the
simulated system.
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I9f46304dee63851caec809a5c6b8e796d684cc05
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/ArmDecoder.py
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
M src/arch/arm/types.hh
4 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/ArmDecoder.py b/src/arch/arm/ArmDecoder.py
index 9f01af6..a5c16f5 100644
--- a/src/arch/arm/ArmDecoder.py
+++ b/src/arch/arm/ArmDecoder.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2021 Arm Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
@@ -23,9 +35,13 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+from m5.params import *
from m5.objects.InstDecoder import InstDecoder
class ArmDecoder(InstDecoder):
type = 'ArmDecoder'
cxx_class = 'gem5::ArmISA::Decoder'
cxx_header = "arch/arm/decoder.hh"
+
+dvm_enabled = Param.Bool(False,
+"Does the decoder implement DVM operations")
diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index 9d90537..48a8641 100644
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2014,2018 ARM Limited
+ * Copyright (c) 2012-2014,2018, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -56,6 +56,7 @@
Decoder::Decoder(const ArmDecoderParams )
: InstDecoder(params, ), data(0), fpscrLen(0), fpscrStride(0),
+ dvmEnabled(params.dvm_enabled),
decoderFlavor(dynamic_cast(params.isa)->decoderFlavor())
{
reset();
@@ -188,6 +189,7 @@
this_emi.itstate = pc.itstate();
this_emi.illegalExecution = pc.illegalExec() ? 1 : 0;
this_emi.debugStep = pc.debugStep() ? 1 : 0;
+this_emi.dvmEnabled = dvmEnabled;
pc.size(inst_size);
emi = 0;
diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index 62d6f54..e1d2bed 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -80,6 +80,9 @@
*/
int sveLen;
+/** True if the decoder should emit DVM Ops (treated as Loads( */
+const bool dvmEnabled;
+
enums::DecoderFlavor decoderFlavor;
/// A cache of decoded instruction objects.
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 734fe6f..9693fc3 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -71,6 +71,8 @@
Bitfield<55, 52> itstateCond;
Bitfield<51, 48> itstateMask;
+Bitfield<42> dvmEnabled;
+
// FPSCR fields
Bitfield<41, 40> fpscrStride;
Bitfield<39, 37> fpscrLen;
--
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Gerrit-Change-Id: I9f46304dee63851caec809a5c6b8e796d684cc05
Gerrit-Change-Number: 56603
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement DSB Shareable as a DVM op
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56607 )
Change subject: arch-arm: Implement DSB Shareable as a DVM op
..
arch-arm: Implement DSB Shareable as a DVM op
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I52c965817dd9d70feca31d1ec2981ad3a090e6a3
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/isa/insts/misc64.isa
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/isa/insts/misc64.isa
b/src/arch/arm/isa/insts/misc64.isa
index 9151b88..3c1ff3b 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -179,12 +179,29 @@
decoder_output += BasicConstructor64.subst(dsbLocalIop)
exec_output += BasicExecute.subst(dsbLocalIop)
-dsbShareableIop =
ArmInstObjParams("dsb", "Dsb64Shareable", "ArmStaticInst", "",
+dvmCode = '''
+if (machInst.dvmEnabled) {
+Request::Flags memAccessFlags =
+Request::STRICT_ORDER|Request::TLBI_SYNC;
+
+if (!PendingDvm) {
+memAccessFlags = memAccessFlags | Request::NO_ACCESS;
+}
+
+fault = xc->initiateSpecialMemCmd(memAccessFlags);
+
+PendingDvm = false;
+}
+'''
+dsbShareableIop =
ArmInstObjParams("dsb", "Dsb64Shareable", "ArmStaticInst",
+ { "code" : "", "dvm_code" : dvmCode
},
['IsReadBarrier', 'IsWriteBarrier',
- 'IsSerializeAfter'])
-header_output += BasicDeclare.subst(dsbShareableIop)
-decoder_output += BasicConstructor64.subst(dsbShareableIop)
+'IsSerializeAfter'])
+header_output += DvmDeclare.subst(dsbShareableIop)
+decoder_output += DvmConstructor.subst(dsbShareableIop)
exec_output += BasicExecute.subst(dsbShareableIop)
+exec_output += DvmInitiateAcc.subst(dsbShareableIop)
+exec_output += DvmCompleteAcc.subst(dsbShareableIop)
dmbIop = ArmInstObjParams("dmb", "Dmb64", "ArmStaticInst", "",
['IsReadBarrier', 'IsWriteBarrier'])
--
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Gerrit-Change-Id: I52c965817dd9d70feca31d1ec2981ad3a090e6a3
Gerrit-Change-Number: 56607
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add helper MISCREG to track a pending DVM operation
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56601 ) Change subject: arch-arm: Add helper MISCREG to track a pending DVM operation .. arch-arm: Add helper MISCREG to track a pending DVM operation We are introducing the MISCREG_TLBINEEDSYNC misc register to track the presence of a pending DVM (TLBI) operation. It will be used by: * TLBI instructions: setting up the flag to indicate there is a pending DVM message * DSB instruction: clearing the flag indicating the DVM messgage has been syncronized Change-Id: I7a599ada5a6ac6f86ed2260caa872f085c889ab5 --- M src/arch/arm/regs/misc.cc M src/arch/arm/regs/misc.hh 2 files changed, 24 insertions(+), 0 deletions(-) diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 0e58d93..109d0fb 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2079,6 +2079,8 @@ .allPrivileges(); InitReg(MISCREG_SEV_MAILBOX) .allPrivileges(); +InitReg(MISCREG_TLBINEEDSYNC) + .allPrivileges().exceptUserMode(); // AArch32 CP14 registers InitReg(MISCREG_DBGDIDR) diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index ea58ad2..479d02e 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -90,6 +90,7 @@ MISCREG_PMXEVTYPER_PMCCFILTR, MISCREG_SCTLR_RST, MISCREG_SEV_MAILBOX, +MISCREG_TLBINEEDSYNC, // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control) MISCREG_DBGDIDR, @@ -1245,6 +1246,7 @@ "pmxevtyper_pmccfiltr", "sctlr_rst", "sev_mailbox", +"tlbi_needsync", // AArch32 CP14 registers "dbgdidr", -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/56601 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I7a599ada5a6ac6f86ed2260caa872f085c889ab5 Gerrit-Change-Number: 56601 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim,tests: Add a tag for drain-related files
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44108 )
Change subject: sim,tests: Add a tag for drain-related files
..
sim,tests: Add a tag for drain-related files
This tag can be used to determine which files are needed
when sim/drain.hh is included in a header file. For
example, when declaring a unit test, this tag makes
the SConscript declaration much simpler.
Change-Id: Ie8a44291a0408090ffbb5b078582d3c5c8d1fd55
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44108
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M src/sim/SConscript
1 file changed, 23 insertions(+), 3 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/SConscript b/src/sim/SConscript
index c0951f3..bf46ccb 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -52,10 +52,11 @@
Source('cxx_manager.cc')
Source('cxx_config_ini.cc')
Source('debug.cc')
+Source('drain.cc', add_tags='gem5 drain')
Source('py_interact.cc', add_tags='python')
Source('eventq.cc', add_tags='gem5 events')
Source('futex_map.cc')
-Source('global_event.cc')
+Source('global_event.cc', add_tags='gem5 drain')
Source('globals.cc')
Source('init.cc', add_tags='python')
Source('init_signals.cc')
@@ -66,9 +67,8 @@
Source('redirect_path.cc')
Source('root.cc')
Source('serialize.cc', add_tags='gem5 serialize')
-Source('drain.cc')
Source('se_workload.cc')
-Source('sim_events.cc')
+Source('sim_events.cc', add_tags='gem5 drain')
Source('sim_object.cc')
Source('sub_system.cc')
Source('ticked_object.cc')
@@ -89,6 +89,7 @@
Source('workload.cc')
Source('mem_pool.cc')
+env.TagImplies('gem5 drain', ['gem5 events', 'gem5 trace'])
env.TagImplies('gem5 events', ['gem5 serialize', 'gem5 trace'])
env.TagImplies('gem5 serialize', 'gem5 trace')
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie8a44291a0408090ffbb5b078582d3c5c8d1fd55
Gerrit-Change-Number: 44108
Gerrit-PatchSet: 13
Gerrit-Owner: Daniel Carvalho
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Replace mcrMrc15TrapToHyp with mcrMrc15Trap
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56592 )
Change subject: arch-arm: Replace mcrMrc15TrapToHyp with mcrMrc15Trap
..
arch-arm: Replace mcrMrc15TrapToHyp with mcrMrc15Trap
The mcrMrc15TrapToHyp helper is already called within mcrMrc15Trap
This achieves the following:
1) Simplifies ISA code
2) Aligns McrDc to Mcr instruction
Change-Id: I9b6bc621ad89230ad9dcf0563d8985d5757b4ae1
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/insts/misc.cc
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
4 files changed, 42 insertions(+), 45 deletions(-)
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 4bb02c9..8c46cb8 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2017-2018, 2021 Arm Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -362,14 +362,7 @@
Fault
McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData)
const
{
-bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
-
-if (hypTrap) {
-return std::make_shared(machInst, iss,
-EC_TRAPPED_CP15_MCR_MRC);
-} else {
-return NoFault;
-}
+return mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
}
std::string
@@ -388,11 +381,9 @@
Fault
McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData)
const
{
-bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
-
-if (hypTrap) {
-return std::make_shared(machInst, iss,
-EC_TRAPPED_CP15_MCR_MRC);
+Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
+if (fault != NoFault) {
+return fault;
} else {
return std::make_shared(machInst, false,
mnemonic);
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index 7253f85..f61c320 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010-2013,2017-2020 ARM Limited
+// Copyright (c) 2010-2013,2017-2021 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -1115,7 +1115,7 @@
MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
RegId(MiscRegClass, preFlatDest)).index();
-bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
+Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
@@ -1123,14 +1123,13 @@
// if we're in non secure PL1 mode then we can trap regardless
// of whether the register is accessible, in other modes we
// trap if only if the register IS accessible.
-if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) &
+if (undefined || (!can_write && !(fault != NoFault
&& !inUserMode(Cpsr) &&
!isSecure(xc->tcBase() {
return std::make_shared(machInst, false,
mnemonic);
}
-if (hypTrap) {
-return std::make_shared(machInst, imm,
-
EC_TRAPPED_CP15_MCR_MRC);
+if (fault != NoFault) {
+return fault;
}
'''
@@ -1209,10 +1208,8 @@
isbCode = '''
// If the barrier is due to a CP15 access check for hyp traps
-if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB,
-xc->tcBase(), imm)) {
-return std::make_shared(machInst, imm,
-EC_TRAPPED_CP15_MCR_MRC);
+if (imm != 0) {
+return mcrMrc15Trap(MISCREG_CP15ISB, machInst, xc->tcBase(),
imm);
}
'''
isbIop = ArmInstObjParams("isb", "Isb", "ImmOp",
@@ -1225,10 +1222,8 @@
dsbCode = '''
// If the barrier is due to a CP15 access check for hyp traps
-if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB,
-xc->tcBase(), imm)) {
-return std::make_shared(machInst, imm,
-EC_TRAPPED_CP15_MCR_MRC);
+if (imm != 0) {
+return mcrMrc15Trap(MISCREG_CP15DSB, machInst, xc->tcBase(),
imm);
}
'''
dsbIop = ArmInstObjParams("dsb", "Dsb", "ImmOp",
@@ -1242,10 +1237,8 @@
dmbCode = '''
// If the barrier is due to a CP15 access check for hyp traps
-if ((imm != 0) &&
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Create a magic PendingDvm operand
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56602 )
Change subject: arch-arm: Create a magic PendingDvm operand
..
arch-arm: Create a magic PendingDvm operand
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I38be0becc167d4d9764091aa46245508a0cc1ca4
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/isa/operands.isa
1 file changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 96c1ec1..01f94e4 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -419,6 +419,7 @@
'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'),
+'PendingDvm': cntrlRegNC('MISCREG_TLBINEEDSYNC'),
#Register fields for microops
'URa' : intReg('ura'),
--
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Gerrit-Change-Id: I38be0becc167d4d9764091aa46245508a0cc1ca4
Gerrit-Change-Number: 56602
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement TLBI Shareable as a DVM op
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56606 )
Change subject: arch-arm: Implement TLBI Shareable as a DVM op
..
arch-arm: Implement TLBI Shareable as a DVM op
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: Ie0a374abce41997af600773cc270a47cdf2c1338
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/isa/insts/data64.isa
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm/isa/insts/data64.isa
b/src/arch/arm/isa/insts/data64.isa
index 038963d..6cc177e 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -378,12 +378,24 @@
decoder_output += MiscRegRegOp64Constructor.subst(msrTlbiIop)
exec_output += BasicExecute.subst(msrTlbiIop)
+dvmCode = '''
+if (machInst.dvmEnabled) {
+Request::Flags memAccessFlags =
+Request::STRICT_ORDER | Request::TLBI;
+
+fault = xc->initiateSpecialMemCmd(memAccessFlags);
+
+PendingDvm = true;
+}
+'''
msrTlbiSIop = ArmInstObjParams("msr", "Tlbi64ShareableHub", "TlbiOp64",
- tlbiCode,
+ { "code" : tlbiCode, "dvm_code" :
dvmCode },
["IsSerializeAfter", "IsNonSpeculative"])
-header_output += MiscRegRegOp64Declare.subst(msrTlbiSIop)
-decoder_output += MiscRegRegOp64Constructor.subst(msrTlbiSIop)
+header_output += MiscRegRegMemOp64Declare.subst(msrTlbiSIop)
+decoder_output += DvmTlbiConstructor.subst(msrTlbiSIop)
exec_output += BasicExecute.subst(msrTlbiSIop)
+exec_output += DvmInitiateAcc.subst(msrTlbiSIop)
+exec_output += DvmCompleteAcc.subst(msrTlbiSIop)
buildDataXRegInst("msrNZCV", 1, '''
CPSR cpsr = XOp1;
--
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Fix SimpleExecContext coding style
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56597 )
Change subject: cpu: Fix SimpleExecContext coding style
..
cpu: Fix SimpleExecContext coding style
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I3b9107943732503055008f843a21925574dad930
Signed-off-by: Giacomo Travaglini
---
M src/cpu/simple/exec_context.hh
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index b0fe779..d23bf51 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -510,20 +510,23 @@
byte_enable);
}
-Fault amoMem(Addr addr, uint8_t *data, unsigned int size,
- Request::Flags flags, AtomicOpFunctorPtr amo_op) override
+Fault
+amoMem(Addr addr, uint8_t *data, unsigned int size,
+ Request::Flags flags, AtomicOpFunctorPtr amo_op) override
{
return cpu->amoMem(addr, data, size, flags, std::move(amo_op));
}
-Fault initiateMemAMO(Addr addr, unsigned int size,
- Request::Flags flags,
- AtomicOpFunctorPtr amo_op) override
+Fault
+initiateMemAMO(Addr addr, unsigned int size,
+ Request::Flags flags,
+ AtomicOpFunctorPtr amo_op) override
{
return cpu->initiateMemAMO(addr, size, flags, std::move(amo_op));
}
-Fault initiateHtmCmd(Request::Flags flags) override
+Fault
+initiateHtmCmd(Request::Flags flags) override
{
return cpu->initiateHtmCmd(flags);
}
--
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Allow TLB shootdown requests in the o3 cpu
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56600 )
Change subject: cpu: Allow TLB shootdown requests in the o3 cpu
..
cpu: Allow TLB shootdown requests in the o3 cpu
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: Ie698efd583f592e5564af01c2150fbec969f56a2
---
M src/cpu/o3/lsq.cc
M src/cpu/o3/lsq.hh
2 files changed, 34 insertions(+), 14 deletions(-)
diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
index c932a93..375093a 100644
--- a/src/cpu/o3/lsq.cc
+++ b/src/cpu/o3/lsq.cc
@@ -784,15 +784,16 @@
assert(!isAtomic || (isAtomic && !needs_burst));
const bool htm_cmd = isLoad && (flags & Request::HTM_CMD);
+const bool tlbi_cmd = isLoad && (flags & Request::TLBI_CMD);
if (inst->translationStarted()) {
request = inst->savedRequest;
assert(request);
} else {
-if (htm_cmd) {
+if (htm_cmd || tlbi_cmd) {
assert(addr == 0x0lu);
assert(size == 8);
-request = new HtmCmdRequest([tid], inst, flags);
+request = new UnsquashableDirectRequest([tid], inst,
flags);
} else if (needs_burst) {
request = new SplitDataRequest([tid], inst, isLoad,
addr,
size, flags, data, res);
@@ -1377,15 +1378,17 @@
lsq->recvReqRetry();
}
-LSQ::HtmCmdRequest::HtmCmdRequest(LSQUnit* port, const DynInstPtr& inst,
-const Request::Flags& flags_) :
+LSQ::UnsquashableDirectRequest::UnsquashableDirectRequest(
+LSQUnit* port,
+const DynInstPtr& inst,
+const Request::Flags& flags_) :
SingleDataRequest(port, inst, true, 0x0lu, 8, flags_,
nullptr, nullptr, nullptr)
{
}
void
-LSQ::HtmCmdRequest::initiateTranslation()
+LSQ::UnsquashableDirectRequest::initiateTranslation()
{
// Special commands are implemented as loads to avoid significant
// changes to the cpu and memory interfaces
@@ -1421,8 +1424,9 @@
}
void
-LSQ::HtmCmdRequest::finish(const Fault , const RequestPtr ,
-gem5::ThreadContext* tc, BaseMMU::Mode mode)
+LSQ::UnsquashableDirectRequest::finish(const Fault ,
+const RequestPtr , gem5::ThreadContext* tc,
+BaseMMU::Mode mode)
{
panic("unexpected behaviour - finish()");
}
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 2e99455..1d4ecfd 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -583,19 +583,24 @@
virtual std::string name() const { return "SingleDataRequest"; }
};
-// hardware transactional memory
-// This class extends SingleDataRequest for the sole purpose
-// of encapsulating hardware transactional memory command requests
-class HtmCmdRequest : public SingleDataRequest
+// This class extends SingleDataRequest for the purpose
+// of allowing special requests (eg Hardware transactional memory, TLB
+// shootdowns) to bypass irrelevant system elements like translation &
+// squashing.
+class UnsquashableDirectRequest : public SingleDataRequest
{
public:
-HtmCmdRequest(LSQUnit* port, const DynInstPtr& inst,
+UnsquashableDirectRequest(LSQUnit* port, const DynInstPtr& inst,
const Request::Flags& flags_);
-virtual ~HtmCmdRequest() {}
+inline virtual ~UnsquashableDirectRequest() {}
virtual void initiateTranslation();
virtual void finish(const Fault , const RequestPtr ,
gem5::ThreadContext* tc, BaseMMU::Mode mode);
-virtual std::string name() const { return "HtmCmdRequest"; }
+virtual std::string
+name() const
+{
+return "UnsquashableDirectRequest";
+}
};
class SplitDataRequest : public LSQRequest
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement DSB Shareable with a separate class
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56594 )
Change subject: arch-arm: Implement DSB Shareable with a separate class
..
arch-arm: Implement DSB Shareable with a separate class
This is an initial step towards making DSB shareable issue a memory
operation (generating DVM messages)
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: Ia7225acc13008ba1ebdf0b091941f6b494e9d4d6
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/misc64.isa
2 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index 0c67645..3c30be6 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2011-2020 ARM Limited
+// Copyright (c) 2011-2021 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -401,7 +401,16 @@
case 0x2:
return new Clrex64(machInst);
case 0x4:
-return new Dsb64(machInst);
+switch (bits(crm, 3, 2)) {
+ case 0x1: // Non-Shareable
+return new Dsb64Local(machInst);
+ case 0x0: // OuterShareable
+ case 0x2: // InnerShareable
+ case 0x3: // FullSystem
+return new Dsb64Shareable(machInst);
+ default:
+GEM5_UNREACHABLE;
+}
case 0x5:
return new Dmb64(machInst);
case 0x6:
diff --git a/src/arch/arm/isa/insts/misc64.isa
b/src/arch/arm/isa/insts/misc64.isa
index d516c53..9151b88 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2011-2013, 2016-2018, 2020 ARM Limited
+// Copyright (c) 2011-2013, 2016-2018, 2020-2021 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -172,12 +172,19 @@
decoder_output += BasicConstructor64.subst(isbIop)
exec_output += BasicExecute.subst(isbIop)
-dsbIop = ArmInstObjParams("dsb", "Dsb64", "ArmStaticInst", "",
- ['IsReadBarrier', 'IsWriteBarrier',
- 'IsSerializeAfter'])
-header_output += BasicDeclare.subst(dsbIop)
-decoder_output += BasicConstructor64.subst(dsbIop)
-exec_output += BasicExecute.subst(dsbIop)
+dsbLocalIop =
ArmInstObjParams("dsb", "Dsb64Local", "ArmStaticInst", "",
+ ['IsReadBarrier', 'IsWriteBarrier',
+ 'IsSerializeAfter'])
+header_output += BasicDeclare.subst(dsbLocalIop)
+decoder_output += BasicConstructor64.subst(dsbLocalIop)
+exec_output += BasicExecute.subst(dsbLocalIop)
+
+dsbShareableIop =
ArmInstObjParams("dsb", "Dsb64Shareable", "ArmStaticInst", "",
+ ['IsReadBarrier', 'IsWriteBarrier',
+ 'IsSerializeAfter'])
+header_output += BasicDeclare.subst(dsbShareableIop)
+decoder_output += BasicConstructor64.subst(dsbShareableIop)
+exec_output += BasicExecute.subst(dsbShareableIop)
dmbIop = ArmInstObjParams("dmb", "Dmb64", "ArmStaticInst", "",
['IsReadBarrier', 'IsWriteBarrier'])
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Reuse MCR15 trapping code in DC instructions
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56593 )
Change subject: arch-arm: Reuse MCR15 trapping code in DC instructions
..
arch-arm: Reuse MCR15 trapping code in DC instructions
Change-Id: I08fec815400ad572da543660f0136e3d88d4dc65
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/isa/insts/misc.isa
1 file changed, 17 insertions(+), 28 deletions(-)
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index f61c320..da2da0c 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -967,7 +967,7 @@
exec_output += PredOpExecute.subst(mrc15Iop)
-mcr15code = '''
+mcr15CheckCode = '''
int preFlatDest = snsBankedIndex(dest, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
@@ -989,6 +989,8 @@
if (fault != NoFault) {
return fault;
}
+'''
+mcr15code = mcr15CheckCode + '''
MiscNsBankedDest = Op1;
'''
mcr15Iop = ArmInstObjParams("mcr", "Mcr15", "MiscRegRegImmOp",
@@ -1110,29 +1112,6 @@
decoder_output += BasicConstructor.subst(clrexIop)
exec_output += PredOpExecute.subst(clrexIop)
-McrDcCheckCode = '''
-int preFlatDest = snsBankedIndex(dest, xc->tcBase());
-MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
-RegId(MiscRegClass, preFlatDest)).index();
-
-Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
-
-auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
-xc->tcBase());
-
-// if we're in non secure PL1 mode then we can trap regardless
-// of whether the register is accessible, in other modes we
-// trap if only if the register IS accessible.
-if (undefined || (!can_write && !(fault != NoFault
&& !inUserMode(Cpsr) &&
- !isSecure(xc->tcBase() {
-return std::make_shared(machInst, false,
- mnemonic);
-}
-if (fault != NoFault) {
-return fault;
-}
-'''
-
McrDcimvacCode = '''
const Request::Flags memAccessFlags(Request::INVALIDATE |
Request::DST_POC);
@@ -1140,7 +1119,7 @@
'''
McrDcimvacIop = ArmInstObjParams("mcr", "McrDcimvac",
"MiscRegRegImmOp",
- {"memacc_code": McrDcCheckCode,
+ {"memacc_code": mcr15CheckCode,
"postacc_code": "",
"ea_code": McrDcimvacCode,
"predicate_test": predicateTest},
@@ -1158,7 +1137,7 @@
'''
McrDccmvacIop = ArmInstObjParams("mcr", "McrDccmvac",
"MiscRegRegImmOp",
- {"memacc_code": McrDcCheckCode,
+ {"memacc_code": mcr15CheckCode,
"postacc_code": "",
"ea_code": McrDccmvacCode,
"predicate_test": predicateTest},
@@ -1176,7 +1155,7 @@
'''
McrDccmvauIop = ArmInstObjParams("mcr", "McrDccmvau",
"MiscRegRegImmOp",
- {"memacc_code": McrDcCheckCode,
+ {"memacc_code": mcr15CheckCode,
"postacc_code": "",
"ea_code": McrDccmvauCode,
"predicate_test": predicateTest},
@@ -1195,7 +1174,7 @@
'''
McrDccimvacIop = ArmInstObjParams("mcr", "McrDccimvac",
"MiscRegRegImmOp",
- {"memacc_code": McrDcCheckCode,
+ {"memacc_code": mcr15CheckCode,
"postacc_code": "",
"ea_code": McrDccimvacCode,
"predicate_test": predicateTest},
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add warning when DVM is enabled in the decoder
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56605 )
Change subject: arch-arm: Add warning when DVM is enabled in the decoder
..
arch-arm: Add warning when DVM is enabled in the decoder
DVM Ops instructions are micro-architecturally modelled as loads. This
will tamper the effective number of loads stat, so a user should
be careful when interpreting stat results
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I526cd542ef804111cf6919359c1ce02df6d4710d
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/decoder.cc
1 file changed, 23 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index 48a8641..f5dd1b1 100644
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -64,6 +64,13 @@
// Initialize SVE vector length
sveLen = (dynamic_cast(params.isa)
->getCurSveVecLenInBitsAtReset() >> 7) - 1;
+
+if (dvmEnabled) {
+warn_once(
+"DVM Ops instructions are micro-architecturally "
+"modelled as loads. This will tamper the effective "
+"number of loads stat\n");
+}
}
void
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add DVM ISA templates
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56604 )
Change subject: arch-arm: Add DVM ISA templates
..
arch-arm: Add DVM ISA templates
These will be used by DVM instructions:
* TLBI Shareable
* DSB Shareable
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I32f83e08360ceb7ba324d07c72fe6addeb4bbbca
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/isa/templates/misc64.isa
1 file changed, 112 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/isa/templates/misc64.isa
b/src/arch/arm/isa/templates/misc64.isa
index faad349..7a10463 100644
--- a/src/arch/arm/isa/templates/misc64.isa
+++ b/src/arch/arm/isa/templates/misc64.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2011,2017-2020 ARM Limited
+// Copyright (c) 2011,2017-2021 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -161,6 +161,24 @@
}
}};
+def template MiscRegRegMemOp64Declare {{
+class %(class_name)s : public %(base_class)s
+{
+ private:
+%(reg_idx_arr_decl)s;
+
+ public:
+// Constructor
+%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
+IntRegIndex _op1, uint64_t _imm);
+
+Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+Fault completeAcc(PacketPtr, ExecContext *,
+ Trace::InstRecord *) const override;
+Fault execute(ExecContext *, Trace::InstRecord *) const override;
+};
+}};
+
def template RegMiscRegOp64Declare {{
class %(class_name)s : public %(base_class)s
{
@@ -233,3 +251,79 @@
%(constructor)s;
}
}};
+
+def template DvmDeclare {{
+/**
+ * Static instruction class for "%(mnemonic)s".
+ */
+class %(class_name)s : public %(base_class)s
+{
+ private:
+%(reg_idx_arr_decl)s;
+
+ public:
+/// Constructor.
+%(class_name)s(ExtMachInst machInst);
+Fault initiateAcc(ExecContext *, Trace::InstRecord *) const
override;
+Fault completeAcc(PacketPtr, ExecContext *,
+ Trace::InstRecord *) const override;
+Fault execute(ExecContext *, Trace::InstRecord *) const override;
+};
+}};
+
+def template DvmTlbiConstructor {{
+%(class_name)s::%(class_name)s(ExtMachInst machInst, MiscRegIndex
_dest,
+ IntRegIndex _op1, uint64_t _imm) :
+%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ _dest, _op1, _imm)
+{
+%(set_reg_idx_arr)s;
+%(constructor)s;
+
+if (machInst.dvmEnabled) {
+flags[IsLoad] = true;
+}
+}
+}};
+
+def template DvmConstructor {{
+%(class_name)s::%(class_name)s(ExtMachInst machInst) :
+%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+{
+%(set_reg_idx_arr)s;
+%(constructor)s;
+
+if (machInst.dvmEnabled) {
+flags[IsLoad] = true;
+}
+}
+}};
+
+def template DvmInitiateAcc {{
+Fault
+%(class_name)s::initiateAcc(ExecContext *xc,
+Trace::InstRecord *traceData) const
+{
+Fault fault = NoFault;
+
+%(op_decl)s;
+%(op_rd)s;
+%(code)s;
+
+%(dvm_code)s;
+
+if (fault == NoFault) {
+%(op_wb)s;
+}
+return fault;
+}
+}};
+
+def template DvmCompleteAcc {{
+Fault
+%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
+Trace::InstRecord *traceData) const
+{
+return NoFault;
+}
+}};
--
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Gerrit-Change-Id: I32f83e08360ceb7ba324d07c72fe6addeb4bbbca
Gerrit-Change-Number: 56604
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Gerrit-Owner: Giacomo Travaglini
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[gem5-dev] Change in gem5/gem5[develop]: python: Update gem5 url output by the simulator
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56649 )
Change subject: python: Update gem5 url output by the simulator
..
python: Update gem5 url output by the simulator
This patch:
- Replaces 'http' with 'https'.
- Adds 'www'.
Change-Id: I6500a39171eb79c98754f517ff1fdd0cf60d83d0
---
M src/python/m5/main.py
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index 701d9f6..b216840 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -310,7 +310,7 @@
verbose = options.verbose - options.quiet
if verbose >= 0:
-print("gem5 Simulator System. http://gem5.org;)
+print("gem5 Simulator System. https://www.gem5.org;)
print(brief_copyright)
print()
--
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Gerrit-Change-Id: I6500a39171eb79c98754f517ff1fdd0cf60d83d0
Gerrit-Change-Number: 56649
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Gerrit-Owner: Bobby Bruce
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache,tests: Add unit test for ReplaceableEntry
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44110 )
(
12 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-cache,tests: Add unit test for ReplaceableEntry
..
mem-cache,tests: Add unit test for ReplaceableEntry
Add a unit test for ReplacementPolicy::ReplaceableEntry.
Change-Id: Iaa0c0cfdf1745b7b4d9efbe8ccab8f002a1bcee8
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44110
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M src/mem/cache/replacement_policies/SConscript
A src/mem/cache/replacement_policies/replaceable_entry.test.cc
2 files changed, 59 insertions(+), 0 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/replacement_policies/SConscript
b/src/mem/cache/replacement_policies/SConscript
index 19f987b..027093f 100644
--- a/src/mem/cache/replacement_policies/SConscript
+++ b/src/mem/cache/replacement_policies/SConscript
@@ -45,3 +45,5 @@
Source('ship_rp.cc')
Source('tree_plru_rp.cc')
Source('weighted_lru_rp.cc')
+
+GTest('replaceable_entry.test', 'replaceable_entry.test.cc')
diff --git a/src/mem/cache/replacement_policies/replaceable_entry.test.cc
b/src/mem/cache/replacement_policies/replaceable_entry.test.cc
new file mode 100644
index 000..fde5775
--- /dev/null
+++ b/src/mem/cache/replacement_policies/replaceable_entry.test.cc
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2021 Daniel R. Carvalho
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+
+#include "mem/cache/replacement_policies/replaceable_entry.hh"
+
+using namespace gem5;
+
+TEST(ReplaceableEntryTest, SetPosition)
+{
+ReplaceableEntry entry;
+uint32_t set = 10, way = 20;
+entry.setPosition(set, way);
+ASSERT_EQ(entry.getSet(), set);
+ASSERT_EQ(entry.getWay(), way);
+}
--
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Gerrit-Change-Id: Iaa0c0cfdf1745b7b4d9efbe8ccab8f002a1bcee8
Gerrit-Change-Number: 44110
Gerrit-PatchSet: 14
Gerrit-Owner: Daniel Carvalho
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Add x86 mutlicore boot tests for timing CPUs
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55744 )
Change subject: tests: Add x86 mutlicore boot tests for timing CPUs
..
tests: Add x86 mutlicore boot tests for timing CPUs
Due to a spin lock error affecting multicore timing cores,
https://gem5.atlassian.net/browse/GEM5-1105, gem5 only supported
single-core timing setups. As this has now been fixed, we support it.
This patch expands the boot tests to include tests for multicore timing
CPU systems.
Change-Id: I89b7f1bed077373dae5e9b8eb6818129da915fee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55744
Reviewed-by: Austin Harris
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M tests/gem5/x86-boot-tests/test_linux_boot.py
1 file changed, 45 insertions(+), 6 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Austin Harris: Looks good to me, but someone else must approve
Bobby Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py
b/tests/gem5/x86-boot-tests/test_linux_boot.py
index 77d1c0d..4b66541 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -126,6 +126,15 @@
)
test_boot(
+cpu="timing",
+num_cpus=8,
+mem_system="classic",
+memory_class="SingleChannelDDR3_2133",
+to_tick=100,
+length=constants.quick_tag,
+)
+
+test_boot(
cpu="atomic",
num_cpus=4,
mem_system="classic",
@@ -173,6 +182,15 @@
)
test_boot(
+cpu="timing",
+num_cpus=4,
+mem_system="classic",
+memory_class="DualChannelDDR3_2133",
+boot_type="init",
+length=constants.long_tag,
+)
+
+test_boot(
cpu="atomic",
num_cpus=4,
mem_system="classic",
@@ -224,15 +242,15 @@
},
"timing": {
1: True,
-2: False, # Timeout
-4: False, # Timeout
-8: False, # Timeout
+2: True,
+4: True,
+8: True,
},
"o3": {
1: False, # Timeout
-2: False, # Not Supported
-4: False, # Not Supported
-8: False, # Not Supported
+2: False, # Timeout
+4: False, # Timeout
+8: False, # Timeout
},
},
"mi_example": {
--
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Gerrit-Change-Id: I89b7f1bed077373dae5e9b8eb6818129da915fee
Gerrit-Change-Number: 55744
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby Bruce
Gerrit-Reviewer: Austin Harris
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Memory range configuration for NUMA system
Daecheol You has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56610 ) Change subject: mem-ruby: Memory range configuration for NUMA system .. mem-ruby: Memory range configuration for NUMA system When system is configured for NUMA, it has multiple memory ranges, and each memory range is mapped to a corresponding NUMA node. However, existing memory configuration maps each LLC/memory controller to all memory ranges. The change enables the CHI protocol based system to be configured as NUMA. Two main changes below: 1. numa_nodes attribute in CHI_Node's NoC_Params - It describes NUMA node ID where each CHI node belongs - Simple NoC configuration example was added 2. Memory range mapping only to a corresponding NUMA node - LLC/memory controllers get only a memory range of the NUMA node where they belong Jira Issue:https://gem5.atlassian.net/browse/GEM5-1187 Change-Id: If4a8f3ba9aac9f74125970f63410883d2ad32f01 --- A configs/example/noc_config/2x4_numa.py M configs/ruby/CHI.py M configs/ruby/CHI_config.py M configs/ruby/Ruby.py M src/sim/System.py 5 files changed, 217 insertions(+), 22 deletions(-) diff --git a/configs/example/noc_config/2x4_numa.py b/configs/example/noc_config/2x4_numa.py new file mode 100644 index 000..5560c26 --- /dev/null +++ b/configs/example/noc_config/2x4_numa.py @@ -0,0 +1,86 @@ +# Copyright (c) 2022 Samsung Electronics Co., Ltd. +# Copyright (c) 2021 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from ruby import CHI_config + +# CustomMesh parameters for a 2x4 mesh. Routers will have the following layout: +# +# 0 --- 1 --- 2 --- 3 +# | | | | +# 4 --- 5 --- 6 --- 7 +# +# 2x4 mesh is split into four numa nodes. +# Numa node0 consists of router 0, 1 (HNF0, SNF0) +# Numa node1 consists of router 2, 3 (HNF1, SNF1) +# Numa node2 consists of router 4, 5 (HNF2, SNF2) +# Numa node3 consists of router 6, 7 (HNF3, SNF3) +# +# Default parameter are configs/ruby/CHI_config.py +# +class NoC_Params(CHI_config.NoC_Params): +num_rows = 2 +num_cols = 4 + +# Specialization of nodes to define bindings for each CHI node type +# needed by CustomMesh. +# The default types are defined in CHI_Node and their derivatives in +# configs/ruby/CHI_config.py + +class CHI_RNF(CHI_config.CHI_RNF): +class NoC_Params(CHI_config.CHI_RNF.NoC_Params): +router_list = [1, 2, 5, 6] + +class CHI_HNF(CHI_config.CHI_HNF): +class NoC_Params(CHI_config.CHI_HNF.NoC_Params): +router_list = [1, 2, 5, 6] +numa_nodes = [0, 1, 2, 3] + +class CHI_SNF_MainMem(CHI_config.CHI_SNF_MainMem): +class NoC_Params(CHI_config.CHI_SNF_MainMem.NoC_Params): +router_list = [0, 3, 4, 7] +numa_nodes = [0, 1, 2, 3] + +class CHI_SNF_BootMem(CHI_config.CHI_SNF_BootMem): +class NoC_Params(CHI_config.CHI_SNF_BootMem.NoC_Params): +
