Re: [gem5-users] Cache Management

[Abhishek Singh]

Hi Timon,
I had one question eviction of write back.
What happens when a dirty block is evicted from L1 cache. Does it check L2
cache updates the content of that block in L2 and then goes to memory and
update contents in memory ?

On Thu, Aug 2, 2018 at 4:04 AM Timon Evenblij 
wrote:

> Hi Abishek,
>
> No, for this case, MSHRs (miss status handling registers) exists. These
> are registers that keep track of missed cache accesses (in your case packet
> 1 that misses in L1), so the cache can be freed to reply to other accesses
> (packet 2) while waiting for the answer of the miss (packet 1 gets answered
> from L2 or even further away).
>
> Best regards,
>
> Timon
>
> On Thu, Aug 2, 2018 at 2:30 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> My question is simple if there are two packets wants to access L1 cache
>> in a system of 2 level cache and cpu is o3. Will packet 2 has to wait for
>> packet 1 to get its response(packet 1) from L2 in case of L1 cache miss and
>> L2 cache hit?
>> What happen if its L2 miss?
>>
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[gem5-users] Cache Management

[Abhishek Singh]

My question is simple if there are two packets wants to access L1 cache in
a system of 2 level cache and cpu is o3. Will packet 2 has to wait for
packet 1 to get its response(packet 1) from L2 in case of L1 cache miss and
L2 cache hit?
What happen if its L2 miss?
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Re: [gem5-users] Cache Management

[Abhishek Singh]

Thanks

On Mon, Aug 6, 2018 at 3:25 AM Nikos Nikoleris 
wrote:

> Hi Abishek,
>
>
>
> Timon is right. In gem5 the caches implement a write-back policy. When
> there is an eviction of a dirty block from L1 then it will be written back
> to L2. In rare exceptions where allocation is not possible in the L2 (e.g.,
> there is a pending request for the victim block), the writeback will be
> sent to the memory below.
>
>
>
> As for your first question and as Timon pointed out, if you have a request
> for block X which misses in the L1 it will send a request to the memory
> below and it will allocate an MSHR while it is waiting for the response. If
> the cache receives another request for the same block X before the response
> comes back and if the two requests can be serviced together (e.g., both
> read from X) the cache will coalesce the second request with the first and
> will service both of them at once when the response arrives to L1.
>
>
>
> Nikos
>
>
>
> *From: *gem5-users  on behalf of Timon
> Evenblij 
> *Reply-To: *gem5 users mailing list 
> *Date: *Monday, 6 August 2018 at 06:56
> *To: *gem5 users mailing list 
> *Subject: *Re: [gem5-users] Cache Management
>
>
>
> Hi Abishek,
>
>
>
> Everything is possible, it all depends on the cache policy. I think the
> default behavior in gem5 is a write-back cache, and I am not sure if any
> other policies are implemented (Can someone else confirm?). A write-back
> cache only writes the data back upon eviction, unlike a write-trough cache
> were all levels are updated at write time. So, for your example: if both L1
> and L2 are write-back caches, then the block in L2 gets updated after
> eviction from L1. Only later, when the block gets evicted from L2, then the
> content is written in main-memory.
>
>
>
> Best regards
>
>
>
> On Sun, Aug 5, 2018 at 3:59 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
> Hi Timon,
>
> I had one question eviction of write back.
>
> What happens when a dirty block is evicted from L1 cache. Does it check L2
> cache updates the content of that block in L2 and then goes to memory and
> update contents in memory ?
>
>
>
> On Thu, Aug 2, 2018 at 4:04 AM Timon Evenblij 
> wrote:
>
> Hi Abishek,
>
>
>
> No, for this case, MSHRs (miss status handling registers) exists. These
> are registers that keep track of missed cache accesses (in your case packet
> 1 that misses in L1), so the cache can be freed to reply to other accesses
> (packet 2) while waiting for the answer of the miss (packet 1 gets answered
> from L2 or even further away).
>
>
>
> Best regards,
>
>
>
> Timon
>
>
>
> On Thu, Aug 2, 2018 at 2:30 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
> My question is simple if there are two packets wants to access L1 cache in
> a system of 2 level cache and cpu is o3. Will packet 2 has to wait for
> packet 1 to get its response(packet 1) from L2 in case of L1 cache miss and
> L2 cache hit?
>
> What happen if its L2 miss?
>
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>
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Re: [gem5-users] Cache Management

[Abhishek Singh]

Is there any limitation on issue width from LSQ queue to L1 cache?
Where I can find that issue width? I am talking about number of parallel
access issued to L1 cache.

On Mon, Aug 6, 2018 at 3:25 AM Nikos Nikoleris 
wrote:

> Hi Abishek,
>
>
>
> Timon is right. In gem5 the caches implement a write-back policy. When
> there is an eviction of a dirty block from L1 then it will be written back
> to L2. In rare exceptions where allocation is not possible in the L2 (e.g.,
> there is a pending request for the victim block), the writeback will be
> sent to the memory below.
>
>
>
> As for your first question and as Timon pointed out, if you have a request
> for block X which misses in the L1 it will send a request to the memory
> below and it will allocate an MSHR while it is waiting for the response. If
> the cache receives another request for the same block X before the response
> comes back and if the two requests can be serviced together (e.g., both
> read from X) the cache will coalesce the second request with the first and
> will service both of them at once when the response arrives to L1.
>
>
>
> Nikos
>
>
>
> *From: *gem5-users  on behalf of Timon
> Evenblij 
> *Reply-To: *gem5 users mailing list 
> *Date: *Monday, 6 August 2018 at 06:56
> *To: *gem5 users mailing list 
> *Subject: *Re: [gem5-users] Cache Management
>
>
>
> Hi Abishek,
>
>
>
> Everything is possible, it all depends on the cache policy. I think the
> default behavior in gem5 is a write-back cache, and I am not sure if any
> other policies are implemented (Can someone else confirm?). A write-back
> cache only writes the data back upon eviction, unlike a write-trough cache
> were all levels are updated at write time. So, for your example: if both L1
> and L2 are write-back caches, then the block in L2 gets updated after
> eviction from L1. Only later, when the block gets evicted from L2, then the
> content is written in main-memory.
>
>
>
> Best regards
>
>
>
> On Sun, Aug 5, 2018 at 3:59 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
> Hi Timon,
>
> I had one question eviction of write back.
>
> What happens when a dirty block is evicted from L1 cache. Does it check L2
> cache updates the content of that block in L2 and then goes to memory and
> update contents in memory ?
>
>
>
> On Thu, Aug 2, 2018 at 4:04 AM Timon Evenblij 
> wrote:
>
> Hi Abishek,
>
>
>
> No, for this case, MSHRs (miss status handling registers) exists. These
> are registers that keep track of missed cache accesses (in your case packet
> 1 that misses in L1), so the cache can be freed to reply to other accesses
> (packet 2) while waiting for the answer of the miss (packet 1 gets answered
> from L2 or even further away).
>
>
>
> Best regards,
>
>
>
> Timon
>
>
>
> On Thu, Aug 2, 2018 at 2:30 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
> My question is simple if there are two packets wants to access L1 cache in
> a system of 2 level cache and cpu is o3. Will packet 2 has to wait for
> packet 1 to get its response(packet 1) from L2 in case of L1 cache miss and
> L2 cache hit?
>
> What happen if its L2 miss?
>
> ___
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> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
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> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
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Re: [gem5-users] Checkpoint Creation in SE mode

[Abhishek Singh]

You can also use simpoints else just fast forward the start up instruction
and run for some instruction using -I

On Wed, Aug 22, 2018 at 8:54 AM Sakshi Tiwari 
wrote:

> Can someone please reply to the query above? It will be really helpful.
>
> Regards,
> Sakshi
>
>
> On Fri, Aug 10, 2018 at 12:53 AM Sakshi Tiwari 
> wrote:
>
>> Hi,
>>
>> I am running gem5 in se mode and I am using SPEC2006 test suite for my
>> experiments. To run the representative section of each of the SPEC
>> benchmark I created simpoints. I have a few questions now:
>>
>> 1) Is it necessary to create checkpoints? Or is there any other way to
>> simply fast forward the simulation on a multi-core system?
>>
>> 2) If it is necessary to create checkpoints then can someone please
>> confirm if the following commands are correct. I am able to follow step (a)
>> and (b) but most of the SPEC benchmarks are failing when I run step (c).
>>  (a) Create checkpoint for each of the simpoint:
>> build/X86/gem5.opt configs/example/se.py
>> --take-simpoint-checkpoint=m5out/simpoints/libq/libq.simpoint,m5out/simpoints/libq/libq.weight,300,1000
>> --cmd="benchmarks/ben/libquantum_base.amd64-m64-gcc43-nn" --options="1397
>> 8" --cpu-type=DerivO3CPU --l1d_size=32kB --l1i_size=32kB --l2_size=256kB
>> --caches --l2cache --l3cache --l3_size=8MB --num-cpus=1 --mem-size=8192MB
>> (b) Run checkpoint_aggregator script to aggregate the checkpoints which
>> would run on 4 different cores (I am running the same checkpoint on all the
>> 4 cores):
>> python util/checkpoint_aggregator.py -o
>> /home/sakshi/workspace2/gem5-63325e5b0a9d-modified/m5out/libq_cpt/cpt.None.4
>> -c --cpts
>> /home/sakshi/workspace2/gem5-63325e5b0a9d-modified/m5out/libq_cpt/cpt.simpoint_03_inst_11_weight_0.069900_interval_300_warmup_1000/
>> /home/sakshi/workspace2/gem5-63325e5b0a9d-modified/m5out/libq_cpt/cpt.simpoint_03_inst_11_weight_0.069900_interval_300_warmup_1000/
>> /home/sakshi/workspace2/gem5-63325e5b0a9d-modified/m5out/libq_cpt/cpt.simpoint_03_inst_11_weight_0.069900_interval_300_warmup_1000/
>> /home/sakshi/workspace2/gem5-63325e5b0a9d-modified/m5out/libq_cpt/cpt.simpoint_03_inst_11_weight_0.069900_interval_300_warmup_1000/
>> --memory-size 8589934592
>> (c) Run the simulation in atomic mode and restore it to the normal mode
>> (i.e. Timing+O3) from the aggregated checkpoint:
>> build/X86/gem5.opt configs/example/se.py --at-instruction
>> --checkpoint-restore=4 --restore-with-cpu=detailed --checkpoint-dir
>> /home/sakshi/workspace2/gem5-63325e5b0a9d-modified/m5out/libq_cpt/
>> --cmd="benchmarks/ben/libquantum_base.amd64-m64-gcc43-nn;benchmarks/ben/libquantum_base.amd64-m64-gcc43-nn;benchmarks/ben/libquantum_base.amd64-m64-gcc43-nn;benchmarks/ben/libquantum_base.amd64-m64-gcc43-nn"
>> --options="1397 8;1397 8;1397 8;1397 8" --cpu-type=DerivO3CPU
>> --l1d_size=32kB --l1i_size=32kB --l2_size=256kB --caches --l2cache
>> --l3cache --l3_size=8MB --num-cpus=4 --mem-size=8192MB -I 1
>>
>> Regards,
>> Sakshi
>>
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[gem5-users] Generate binary for new added instruction

[Abhishek Singh]

Hello Everyone,

I have added new instruction in x86 isa of gem5. I wanted to test it using
(modified) binary. As new instruction are not identified by general gcc/g++
complier on host x86 machine. I am unable to get binary.
I am using SE mode of gem5. Is there a way to run new instruction using asm
inline function, and  generate new binary to run the application on gem5?

Thanks,
Abhishek
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[gem5-users] REX prefix implementation in x86

[Abhishek Singh]

Hello Everyone,

I wanted to introduce a new implementation for Mov Instruction using R11
register, my new opcodes are placed in two_byte.isa and I have duplicated
'mov' functionality present in files move.py and ldstop.isa.

My question is: I understand how to decode opcode for example if the new
opcode is '0x11'
take top 5 bits and then 3 bits to write a case function in two_byte.isa

I am not understanding, how should I make sure it uses REX format same as
MOV?


For example:
In the case of 8 bits:


*41* 8a 03 mov (%r11),%al

*41* 0f xx 03 new_mov (%r11),%al

In the case of 16*: *

*66 41* 8b 03 mov (%r11),%ax

*66 41* 0f xx 03 new_mov (%r11),%ax


In the case of 32*: *

*41* 8b 03 mov (%r11),%eax

*41* 0f xx 03 new_mov (%r11),%eax


In the case of 64*: *

*49* 8b 03 mov (%r11),%rax

*49* 0f xx 03 new_mov (%r11),%rax

***Numbers in bold are REX bits, xx are new opcodes.

Gabe or anyone who has any information on this?


Best regards,

Abhishek
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Re: [gem5-users] REX prefix implementation in x86

[Abhishek Singh]

Thanks for the clarification.
You helped me a lot thanks :-)

On Fri, Nov 2, 2018 at 8:41 PM Gabe Black  wrote:

> You don't need to worry about changing ldstop.isa unless you're adding a
> new microop also, but yes I think that's correct. If you use Eb and Gb, I
> think you're restricting your operand size to always be a byte, but that
> might be what you want.
>
> Gabe
>
> On Thu, Nov 1, 2018 at 9:13 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> There was typo in my last line
>> It is
>> I do *NOT* have to worry for "41" in "41 0f 6c 03" (41 is used for Extension
>> of r/m field, base field, or opcode reg field(reference:
>> http://ref.x86asm.net/coder64.html))
>>
>>
>> On Thu, Nov 1, 2018 at 9:37 PM Abhishek Singh <
>> abhishek.singh199...@gmail.com> wrote:
>>
>>> Hello Gabe,
>>>
>>> Thanks for your help, just to verify what I have understood from your
>>> explanation is, to add new instruction which behaves like MOV
>>> I just need to take care of using proper operands(Gb,Eb), and *REX(Prefix)
>>> will be taken care automatically*.
>>>
>>> From available opcodes in two_byte.isa, I have chosen 6c, 6d, 7c, and 7d.
>>> for example to implement
>>> 6c:New_mov(Eb,Gb)
>>>
>>> I just add following line it in two_byte.isa file
>>> ""
>>>
>>> 0x0D: decode LEGACY_DECODEVAL {
>>>
>>> // no prefix
>>>
>>> 0x0: decode OPCODE_OP_BOTTOM3 {
>>>
>>> {
>>>
>>>   0x4: NEWMOV(Eb,Gb);
>>>
>>>  }
>>>
>>> }
>>> ""
>>> And just duplicate function by changing name in "
>>> insts/general_purpose/data_transfer/move.py" and "microops/ldstop.isa"
>>>
>>> So if I create binary for "41 0f 6c 03" (for NEWMOV (%r11),%al)
>>>
>>> I do have to worry for "41" in "41 0f 6c 03" (41 is used for Extension
>>> of r/m field, base field, or opcode reg field(reference:
>>> http://ref.x86asm.net/coder64.html))
>>>
>>> Is this correct?
>>>
>>> Best regards,
>>>
>>> Abhishek
>>>
>>>
>>> On Thu, Nov 1, 2018 at 6:25 PM Gabe Black  wrote:
>>>
>>>> Hi Abhishek. In x86, and in gem5 in general but particularly in x86,
>>>> decoding happens in two steps. The predecoder reads in the bytes which are
>>>> in memory and applies context to them (operating mode, various global
>>>> settings like address sizes) and translates them into a canonical structure
>>>> called an ExtMachInst. In x86, that step gathers up all the prefixes,
>>>> opcode bytes, etc., and stores them in the ExtMachInst. When an instruction
>>>> is specified in the decoder, it has some parameters which specify what
>>>> format its operands come in. That's useful if the basic functionality of
>>>> the instruction is the same, but in different scenarios it uses register
>>>> indices from different parts of the encoding for instance. If that flavor
>>>> of operand is defined to include bits from the REX prefix, then that will
>>>> be factored in when that instruction is set up. The format of those
>>>> specifiers is modeled after an encoding you'll find in the AMD architecture
>>>> manuals where it serves a similar purpose, and you can look at that to get
>>>> an idea of what a particular specifier means.
>>>>
>>>> If you use the same operand suffixes as regular mov does (for instance
>>>> Ev,Gv), then your mov should get its arguments in the same way. For
>>>> reference, E means that operand may be a register or a memory location
>>>> based on the ModRM byte, and G means the "reg" field of modRM. The small v
>>>> means to use the effective operand size.
>>>>
>>>> Gabe
>>>>
>>>> On Thu, Nov 1, 2018 at 9:51 AM Abhishek Singh <
>>>> abhishek.singh199...@gmail.com> wrote:
>>>>
>>>>> Hello Everyone,
>>>>>
>>>>> I wanted to introduce a new implementation for Mov Instruction using
>>>>> R11 register, my new opcodes are placed in two_byte.isa and I have
>>>>> duplicated 'mov' functionality present in files move.py and ldstop.isa.
>>>>>
>>>>> My question is: I understan

Re: [gem5-users] REX prefix implementation in x86

[Abhishek Singh]

Hello Gabe,

Thanks for your help, just to verify what I have understood from your
explanation is, to add new instruction which behaves like MOV
I just need to take care of using proper operands(Gb,Eb), and *REX(Prefix)
will be taken care automatically*.

>From available opcodes in two_byte.isa, I have chosen 6c, 6d, 7c, and 7d.
for example to implement
6c:New_mov(Eb,Gb)

I just add following line it in two_byte.isa file
""

0x0D: decode LEGACY_DECODEVAL {

// no prefix

0x0: decode OPCODE_OP_BOTTOM3 {

{

  0x4: NEWMOV(Eb,Gb);

 }

}
""
And just duplicate function by changing name in "
insts/general_purpose/data_transfer/move.py" and "microops/ldstop.isa"

So if I create binary for "41 0f 6c 03" (for NEWMOV (%r11),%al)

I do have to worry for "41" in "41 0f 6c 03" (41 is used for Extension of
r/m field, base field, or opcode reg field(reference:
http://ref.x86asm.net/coder64.html))

Is this correct?

Best regards,

Abhishek


On Thu, Nov 1, 2018 at 6:25 PM Gabe Black  wrote:

> Hi Abhishek. In x86, and in gem5 in general but particularly in x86,
> decoding happens in two steps. The predecoder reads in the bytes which are
> in memory and applies context to them (operating mode, various global
> settings like address sizes) and translates them into a canonical structure
> called an ExtMachInst. In x86, that step gathers up all the prefixes,
> opcode bytes, etc., and stores them in the ExtMachInst. When an instruction
> is specified in the decoder, it has some parameters which specify what
> format its operands come in. That's useful if the basic functionality of
> the instruction is the same, but in different scenarios it uses register
> indices from different parts of the encoding for instance. If that flavor
> of operand is defined to include bits from the REX prefix, then that will
> be factored in when that instruction is set up. The format of those
> specifiers is modeled after an encoding you'll find in the AMD architecture
> manuals where it serves a similar purpose, and you can look at that to get
> an idea of what a particular specifier means.
>
> If you use the same operand suffixes as regular mov does (for instance
> Ev,Gv), then your mov should get its arguments in the same way. For
> reference, E means that operand may be a register or a memory location
> based on the ModRM byte, and G means the "reg" field of modRM. The small v
> means to use the effective operand size.
>
> Gabe
>
> On Thu, Nov 1, 2018 at 9:51 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Everyone,
>>
>> I wanted to introduce a new implementation for Mov Instruction using R11
>> register, my new opcodes are placed in two_byte.isa and I have duplicated
>> 'mov' functionality present in files move.py and ldstop.isa.
>>
>> My question is: I understand how to decode opcode for example if the new
>> opcode is '0x11'
>> take top 5 bits and then 3 bits to write a case function in two_byte.isa
>>
>> I am not understanding, how should I make sure it uses REX format same as
>> MOV?
>>
>>
>> For example:
>> In the case of 8 bits:
>>
>>
>> *41* 8a 03 mov (%r11),%al
>>
>> *41* 0f xx 03 new_mov (%r11),%al
>>
>> In the case of 16*: *
>>
>> *66 41* 8b 03 mov (%r11),%ax
>>
>> *66 41* 0f xx 03 new_mov (%r11),%ax
>>
>>
>> In the case of 32*: *
>>
>> *41* 8b 03 mov (%r11),%eax
>>
>> *41* 0f xx 03 new_mov (%r11),%eax
>>
>>
>> In the case of 64*: *
>>
>> *49* 8b 03 mov (%r11),%rax
>>
>> *49* 0f xx 03 new_mov (%r11),%rax
>>
>> ***Numbers in bold are REX bits, xx are new opcodes.
>>
>> Gabe or anyone who has any information on this?
>>
>>
>> Best regards,
>>
>> Abhishek
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Re: [gem5-users] REX prefix implementation in x86

[Abhishek Singh]

There was typo in my last line
It is
I do *NOT* have to worry for "41" in "41 0f 6c 03" (41 is used for Extension
of r/m field, base field, or opcode reg field(reference:
http://ref.x86asm.net/coder64.html))


On Thu, Nov 1, 2018 at 9:37 PM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hello Gabe,
>
> Thanks for your help, just to verify what I have understood from your
> explanation is, to add new instruction which behaves like MOV
> I just need to take care of using proper operands(Gb,Eb), and *REX(Prefix)
> will be taken care automatically*.
>
> From available opcodes in two_byte.isa, I have chosen 6c, 6d, 7c, and 7d.
> for example to implement
> 6c:New_mov(Eb,Gb)
>
> I just add following line it in two_byte.isa file
> ""
>
> 0x0D: decode LEGACY_DECODEVAL {
>
> // no prefix
>
> 0x0: decode OPCODE_OP_BOTTOM3 {
>
> {
>
>   0x4: NEWMOV(Eb,Gb);
>
>  }
>
> }
> ""
> And just duplicate function by changing name in "
> insts/general_purpose/data_transfer/move.py" and "microops/ldstop.isa"
>
> So if I create binary for "41 0f 6c 03" (for NEWMOV (%r11),%al)
>
> I do have to worry for "41" in "41 0f 6c 03" (41 is used for Extension of
> r/m field, base field, or opcode reg field(reference:
> http://ref.x86asm.net/coder64.html))
>
> Is this correct?
>
> Best regards,
>
> Abhishek
>
>
> On Thu, Nov 1, 2018 at 6:25 PM Gabe Black  wrote:
>
>> Hi Abhishek. In x86, and in gem5 in general but particularly in x86,
>> decoding happens in two steps. The predecoder reads in the bytes which are
>> in memory and applies context to them (operating mode, various global
>> settings like address sizes) and translates them into a canonical structure
>> called an ExtMachInst. In x86, that step gathers up all the prefixes,
>> opcode bytes, etc., and stores them in the ExtMachInst. When an instruction
>> is specified in the decoder, it has some parameters which specify what
>> format its operands come in. That's useful if the basic functionality of
>> the instruction is the same, but in different scenarios it uses register
>> indices from different parts of the encoding for instance. If that flavor
>> of operand is defined to include bits from the REX prefix, then that will
>> be factored in when that instruction is set up. The format of those
>> specifiers is modeled after an encoding you'll find in the AMD architecture
>> manuals where it serves a similar purpose, and you can look at that to get
>> an idea of what a particular specifier means.
>>
>> If you use the same operand suffixes as regular mov does (for instance
>> Ev,Gv), then your mov should get its arguments in the same way. For
>> reference, E means that operand may be a register or a memory location
>> based on the ModRM byte, and G means the "reg" field of modRM. The small v
>> means to use the effective operand size.
>>
>> Gabe
>>
>> On Thu, Nov 1, 2018 at 9:51 AM Abhishek Singh <
>> abhishek.singh199...@gmail.com> wrote:
>>
>>> Hello Everyone,
>>>
>>> I wanted to introduce a new implementation for Mov Instruction using R11
>>> register, my new opcodes are placed in two_byte.isa and I have duplicated
>>> 'mov' functionality present in files move.py and ldstop.isa.
>>>
>>> My question is: I understand how to decode opcode for example if the new
>>> opcode is '0x11'
>>> take top 5 bits and then 3 bits to write a case function in two_byte.isa
>>>
>>> I am not understanding, how should I make sure it uses REX format same
>>> as MOV?
>>>
>>>
>>> For example:
>>> In the case of 8 bits:
>>>
>>>
>>> *41* 8a 03 mov (%r11),%al
>>>
>>> *41* 0f xx 03 new_mov (%r11),%al
>>>
>>> In the case of 16*: *
>>>
>>> *66 41* 8b 03 mov (%r11),%ax
>>>
>>> *66 41* 0f xx 03 new_mov (%r11),%ax
>>>
>>>
>>> In the case of 32*: *
>>>
>>> *41* 8b 03 mov (%r11),%eax
>>>
>>> *41* 0f xx 03 new_mov (%r11),%eax
>>>
>>>
>>> In the case of 64*: *
>>>
>>> *49* 8b 03 mov (%r11),%rax
>>>
>>> *49* 0f xx 03 new_mov (%r11),%rax
>>>
>>> ***Numbers in bold are REX bits, xx are new opcodes.
>>>
>>> Gabe or anyone who has any information on this?
>>>
>>>
>>> Best regards,
>>>
>>> Abhishek
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>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
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>
>
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[gem5-users] Fwd: Adding new flags at decoder

[Abhishek Singh]

Hello everyone and Gabe,

Do you have any information on this question?

-- Forwarded message -
From: Abhishek Singh 
Date: Wed, Nov 14, 2018 at 8:07 PM
Subject: Adding new flags at decoder
To: gem5 users mailing list 


Hello Everyone,

I have added new instructions in SE x86 ISA, this instructions are same as
MOV instructions in x86 and use the similar mnemonic defined in
/arch/x86/isa/microops/ldstop.isa i.e. Ld and St

For example:

defineMicroLoadOp('*Ldnew*', 'Data = merge(Data, Mem, dataSize);', 'Data =
Mem & mask(dataSize * 8);')


defineMicroStoreOp('*Stnew*', 'Mem = pick(Data, 2, dataSize);')


I have added a new flag "SPECIAL" in src/mem/request.hh, and also added

 bool *isSpecial*() const { return _flags.isSet(SPECIAL); } in same file to
identify this instructions in different cache levels.


I want to set this flag when I see this new mov instruction so I modify
ldstop.isa lines as


defineMicroLoadOp('Ldnew', 'Data = merge(Data, Mem, dataSize);', 'Data =
Mem & mask(dataSize * 8);*'mem_flags="Request::Special”*)


defineMicroStoreOp('Stnew', 'Mem = pick(Data, 2, dataSize);'
*mem_flags="Request::Special”*)




*My question is:*


   1. Are this steps enough to set a flag and use it in caches?
   2. Will this flag be deleted on own on response path(recvTimingResp in
   src/mem/cache/base.cc) i.e. on a cold miss to load when pkt is
   traversing from LLC to Dcache, will I be able to see this flag again in
   when pkt is the response?








Best regards,

Abhishek
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[gem5-users] Adding new flags at decoder

[Abhishek Singh]

Hello Everyone,

I have added new instructions in SE x86 ISA, this instructions are same as
MOV instructions in x86 and use the similar mnemonic defined in
/arch/x86/isa/microops/ldstop.isa i.e. Ld and St

For example:

defineMicroLoadOp('*Ldnew*', 'Data = merge(Data, Mem, dataSize);', 'Data =
Mem & mask(dataSize * 8);')


defineMicroStoreOp('*Stnew*', 'Mem = pick(Data, 2, dataSize);')


I have added a new flag "SPECIAL" in src/mem/request.hh, and also added

 bool *isSpecial*() const { return _flags.isSet(SPECIAL); } in same file to
identify this instructions in different cache levels.


I want to set this flag when I see this new mov instruction so I modify
ldstop.isa lines as


defineMicroLoadOp('Ldnew', 'Data = merge(Data, Mem, dataSize);', 'Data =
Mem & mask(dataSize * 8);*'mem_flags="Request::Special”*)


defineMicroStoreOp('Stnew', 'Mem = pick(Data, 2, dataSize);'
*mem_flags="Request::Special”*)




*My question is:*


   1. Are this steps enough to set a flag and use it in caches?
   2. Will this flag be deleted on own on response path(recvTimingResp in
   src/mem/cache/base.cc) i.e. on a cold miss to load when pkt is
   traversing from LLC to Dcache, will I be able to see this flag again in
   when pkt is the response?








Best regards,

Abhishek
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[gem5-users] Persistent Benchmark Fails on gem5-SE

[Abhishek Singh]

Hello Everyone,

I am trying to run "Mnemosyne" benchmark on gem5 in SE mode,
Mnemosyne can be found from "https://github.com/snalli/mnemosyne-gcc; site.
I am able to run the benchmark on host machine but when I try to run on
gem5 in SE mode, simulation exits with the following error:

warn: Attempting to open special file: /proc/self/status. Ignoring.
Simulation may take un-expected code path or be non-deterministic until
proper handling is implemented.

warn: instruction 'movntdq_Mo_Vo' unimplemented

warn: instruction 'movntdq_Mo_Vo' unimplemented

warn: instruction 'movntdq_Mo_Vo' unimplemented

warn: instruction 'movntdq_Mo_Vo' unimplemented

warn: Attempting to open special file: /sys/devices/system/node. Ignoring.
Simulation may take un-expected code path or be non-deterministic until
proper handling is implemented.

warn: ignoring syscall getdents(...)

warn: ignoring syscall sched_getaffinity(...)

warn: Attempting to open special file: /sys/devices/system/cpu. Ignoring.
Simulation may take un-expected code path or be non-deterministic until
proper handling is implemented.

warn: ignoring syscall getdents(...)

sysconf(NPROCESSORS_CONF) failed.

: Success

request to allocate mask for invalid number; abort

: Success

Exiting @ tick 7065141500 because exiting with last active thread context

Simulated exit code not 0! Exit code is 1

If anyone has been successful in running any persistent workload on gem5-SE
mode, please let me know so I can change my benchmark.

Also, if anyone knows how can I solve this problem without migrating to FS
mode please let me know.


Best regards,

Abhishek
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[gem5-users] Set number of ports to dcache and l2 cache in gem5

[Abhishek Singh]

Hello Everyone,

I want to simulate multi-port cache configuration for O3CPU, for example,

Private L1: Split I/D, 64KB, 4-way, 64B blocks, *3ports,* 1ns, 32MSHRs, LRU
Private L2: 256kB, 8-way, *2 ports,* 3ns, 32MSHRs, LRU

How should I set highlighted ports in gem5 i.e. *3 ports* for L1 and *2
ports* for L2?

I know there is a parameter in O3CPU.py which is *cacheStorePorts, *which
is for stores which will limit store port to L1-dcache, and where is Load
FU, I searched in *FuncUnitConfig.py *but there was no LoadFU, is* class
ReadPort* mean LoadFu?

And then how to set the number of ports for L2?

I have seen this multi-port configuration in most gem5 papers, so if anyone
knows how to do it please let me know!

I have seen this post:
https://www.mail-archive.com/gem5-users@gem5.org/msg12912.html
But still, it does not say how to set this parameter for L1 and L2 and
where is LoadFU.


Best regards,

Abhishek
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Re: [gem5-users] Set number of ports to dcache and l2 cache in gem5

[Abhishek Singh]

Thank you  so much Jason, your reply was very much required.

On Thu, Dec 13, 2018 at 1:17 PM Jason Lowe-Power 
wrote:

> Hi Abhishek,
>
> I wouldn't trust the parameters you mentioned to correctly model cache
> ports as you want. The bandwidth between the core and the caches is not
> flexibly modeled with the classic caches or with Ruby right now. I believe
> there are some patches on the code review site that try to make this better
> (they relate to the ARM vector extension patch series). For the bandwidth
> between caches, I think it's even worse. You can configure the interconnect
> (e.g., crossbar) to have a particular bandwidth which is modeled in detail
> for the classic cache, but the cache itself doesn't model bandwidth well.
> For Ruby, you can use the BankedCache models if your coherence protocol
> correctly requests those resources, but most of the protocols don't
> implement that. Also, the BankedCache model is a quick and dirty model for
> cache bandwidth, not a detailed port model.
>
> As far as "I have seen this multi-port configuration in most gem5 papers",
> I would guess that one person wrote it once and then everyone else copied
> it. I doubt that there was significant care given to the cache bandwidth
> model in all but a few papers (if that).
>
> Hope this helps,
> Jason
>
> On Tue, Dec 11, 2018 at 10:51 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Everyone,
>>
>> I want to simulate multi-port cache configuration for O3CPU, for example,
>>
>> Private L1: Split I/D, 64KB, 4-way, 64B blocks, *3ports,* 1ns, 32MSHRs,
>> LRU
>> Private L2: 256kB, 8-way, *2 ports,* 3ns, 32MSHRs, LRU
>>
>> How should I set highlighted ports in gem5 i.e. *3 ports* for L1 and *2
>> ports* for L2?
>>
>> I know there is a parameter in O3CPU.py which is *cacheStorePorts, *which
>> is for stores which will limit store port to L1-dcache, and where is Load
>> FU, I searched in *FuncUnitConfig.py *but there was no LoadFU, is* class
>> ReadPort* mean LoadFu?
>>
>> And then how to set the number of ports for L2?
>>
>> I have seen this multi-port configuration in most gem5 papers, so if
>> anyone knows how to do it please let me know!
>>
>> I have seen this post:
>> https://www.mail-archive.com/gem5-users@gem5.org/msg12912.html
>> But still, it does not say how to set this parameter for L1 and L2 and
>> where is LoadFU.
>>
>>
>> Best regards,
>>
>> Abhishek
>>
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[gem5-users] Running Mnemosyne Benchmark on gem5

[Abhishek Singh]

Hello Everyone,

I am trying to run Mnemosyne benchmark (
https://github.com/snalli/mnemosyne-gcc) on SE mode of gem5(latest Master
Commit as of today), I am running into this runtime error as follows:

"""

warn: ignoring syscall set_robust_list(...)

warn: ignoring syscall rt_sigaction(...)

  (further warnings will be suppressed)

warn: ignoring syscall rt_sigprocmask(...)

  (further warnings will be suppressed)

warn: Attempting to open special file: /proc/self/status. Ignoring.
Simulation may take un-expected code path or be non-deterministic until
proper handling is implemented.

warn: instruction 'movntdq_Mo_Vo' unimplemented

warn: instruction 'movntdq_Mo_Vo' unimplemented

warn: instruction 'movntdq_Mo_Vo' unimplemented

warn: instruction 'movntdq_Mo_Vo' unimplemented

warn: Attempting to open special file: /sys/devices/system/node. Ignoring.
Simulation may take un-expected code path or be non-deterministic until
proper handling is implemented.

warn: Attempting to open special file:
/sys/devices/system/node/node0/meminfo. Ignoring. Simulation may take
un-expected code path or be non-deterministic until proper handling is
implemented.

warn: ignoring syscall sched_getaffinity(...)

warn: Attempting to open special file: /sys/devices/system/cpu. Ignoring.
Simulation may take un-expected code path or be non-deterministic until
proper handling is implemented.

*request to allocate mask for invalid number; abort*

: Success

Exiting @ tick 3402857920 because exiting with last active thread context

*Simulated exit code not 0! Exit code is 1*


"""


I am not able to understand this, can anyone help me with this?



Best regards,

Abhishek
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[gem5-users] Running pthread Application Binary on gem5

[Abhishek Singh]

Hello Users,

I am trying to run BWA(https://github.com/lh3/bwa) its an application to
align DNA sequence, one can think of as string matching type of program.

The command line I use is:

*/home/abs218/baseline/gem5/build/X86/gem5.opt
/home/abs218/baseline/gem5/configs/example/se.py -c /home/abs218/bwa/bwa -o
"mem ../genome/test/ref.fa ../genome/test/test_PE1.fa" --caches --l2cache
--l1d_size=32kB --l1i_size=32kB --l2_size=256kB --l1d_assoc=8 --l1i_assoc=8
--l2_assoc=8 --cacheline_size=64 --cpu-type=DerivO3CPU
--mem-type=DDR4_2400_8x8 --mem-size=8GB --sys-clock=2.6GHz
--cpu-clock=2.6GHz -n 8*


I use more than 1 core because the "BWA" application uses pthreads.


The error I encounter is "panic: Tried to read unmapped address
0x80255298."


Is there a way I can overcome the error?

Best regards,

Abhishek
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[gem5-users] Bypassing Dcache on MSHR 1

[Abhishek Singh]

Hello Everyone,

I want to bypass Dcache i.e., do not allocate anything in Dcache, in order
to do that, I use tempBlock in *handleFill* function in
src/mem/cache/base.cc.


*Before: *

 blk = allocate ? allocateBlock(pkt, writebacks) : nullptr;

*After:*


if(name() == "system.cpu.dcache”) blk = nullptr;

else

 blk = allocate ? allocateBlock(pkt, writebacks) : nullptr;

The problem I run into, I get stuck in continuous request and response
cycle, that is I keep getting request for particular address and I satisfy
the response for it.

This only happens when I set mshr for dcache as 1.
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Re: [gem5-users] Creating Blocking caches (i.e., 1 target per MSHR)

[Abhishek Singh]

(There was a typo in previous mail)

Hello Nikos and Everyone,

In src/mem/cache/cache.cc for function handleTimingReqMiss(), we only check
if there is an existing mshr entry corresponding to Miss Request. And then
we call  *BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time,
request_time);*

In BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time,
request_time) function if its the first time the cache line is having a
miss we create MSHR entry by calling allocateMissbuffer which is defined in
base.hh, this allocateMissBuffer function creates new MSHR entry and first
target of that entry, so I have modified allcateMissBuffer in base.hh to :

   MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send =
true)

{

MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,

pkt, time, order++,

allocOnFill(pkt->cmd));


if (mshrQueue.isFull()) {

setBlocked((BlockedCause)MSHRQueue_MSHRs);

}


*if (mshr->getNumTargets() == numTarget) {*



*//cout << "Blocked: " << name() << endl;*

*noTargetMSHR = mshr;*

*setBlocked(Blocked_NoTargets);*

*}*


if (sched_send) {

// schedule the send

schedMemSideSendEvent(time);

}


return mshr;

}

What highlighted part does it blocks the cache from receiving any request
from LSQ until we get clear the MSHR entry through recvTimingResp function.
Note that *mshr->getNumTargets() *will always be one as this is the very
first time an MSHR entry is created. But somehow I do not think this is
correctas the simulation is not terminating but it does when hello binary
is tested.

Now if in baseline gem5 the current commit if we* set tgts_per_mshr from
configs/common/Caches.py *for dcache to 1 and compare the stats with *
tgts_per_mshr
set to 2 *we can clearly see that * tgts_per_mshr set to 2 * has more
cycles from stat *system.cpu.dcache.blocked:**:no_targets* when compared to
1 target per mshr. This is because we never blocked the requests coming to
Dcache when we had only one target per MSHR.

On Mon, Mar 25, 2019 at 5:43 PM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hello Nikos and Everyone,
>
> In src/mem/cache/cache.cc for function handleTimingReqMiss(), we only
> check if there is an existing mshr entry corresponding to Miss Request. And
> then we call  *BaseCache::handleTimingReqMiss(pkt, mshr, blk,
> forward_time, request_time);*
>
> In BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time,
> request_time) function if its the first time the cache line is having a
> miss we create MSHR entry by calling allocateMissbuffer which is defined in
> base.hh, this allocateMissBuffer function creates new MSHR entry and first
> target or that entry, so I have modified allcateMissBuffer in base.hh to :
>
>MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send =
> true)
>
> {
>
> MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize),
> blkSize,
>
> pkt, time, order++,
>
> allocOnFill(pkt->cmd));
>
>
> if (mshrQueue.isFull()) {
>
> setBlocked((BlockedCause)MSHRQueue_MSHRs);
>
> }
>
>
> *if (mshr->getNumTargets() == numTarget) {*
>
>
>
> *//cout << "Blocked: " << name() << endl;*
>
> *noTargetMSHR = mshr;*
>
> *setBlocked(Blocked_NoTargets);*
>
> *}*
>
>
> if (sched_send) {
>
> // schedule the send
>
> schedMemSideSendEvent(time);
>
> }
>
>
> return mshr;
>
> }
>
> What highlighted part does it blocks the cache from receiving any request
> from LSQ until we get clear the MSHR entry through recvTimingResp function.
> Note that *mshr->getNumTargets() *will always be one as this is the very
> first time an MSHR entry is created. But somehow I do not think this is
> correctas the simulation is not terminating but it does when hello binary
> is tested.
>
> Now if in baseline gem5 the current commit if we* set tgts_per_mshr from
> configs/common/Caches.py *for dcache to 1 and compare the stats with * 
> tgts_per_mshr
> set to 2 *we can clearly see that * tgts_per_mshr set to 2 * has more
> cycles from stat *system.cpu.dcache.blocked:**:no_targets* when compared
> to 1 target per mshr. This is because we never blocked the requests coming
> to Dcache when we had only one target per MSHR.
>
>
> Best regards,
>
> Abhishek
>
>
> On Mon, Mar 

Re: [gem5-users] Creating Blocking caches (i.e., 1 target per MSHR)

[Abhishek Singh]

Hello Nikos and Everyone,

In src/mem/cache/cache.cc for function handleTimingReqMiss(), we only check
if there is an existing mshr entry corresponding to Miss Request. And then
we call  *BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time,
request_time);*

In BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time,
request_time) function if its the first time the cache line is having a
miss we create MSHR entry by calling allocateMissbuffer which is defined in
base.hh, this allocateMissBuffer function creates new MSHR entry and first
target or that entry, so I have modified allcateMissBuffer in base.hh to :

   MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send =
true)

{

MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,

pkt, time, order++,

allocOnFill(pkt->cmd));


if (mshrQueue.isFull()) {

setBlocked((BlockedCause)MSHRQueue_MSHRs);

}


*if (mshr->getNumTargets() == numTarget) {*



*//cout << "Blocked: " << name() << endl;*

*noTargetMSHR = mshr;*

*setBlocked(Blocked_NoTargets);*

*}*


if (sched_send) {

// schedule the send

schedMemSideSendEvent(time);

}


return mshr;

}

What highlighted part does it blocks the cache from receiving any request
from LSQ until we get clear the MSHR entry through recvTimingResp function.
Note that *mshr->getNumTargets() *will always be one as this is the very
first time an MSHR entry is created. But somehow I do not think this is
correctas the simulation is not terminating but it does when hello binary
is tested.

Now if in baseline gem5 the current commit if we* set tgts_per_mshr from
configs/common/Caches.py *for dcache to 1 and compare the stats with *
tgts_per_mshr
set to 2 *we can clearly see that * tgts_per_mshr set to 2 * has more
cycles from stat *system.cpu.dcache.blocked:**:no_targets* when compared to
1 target per mshr. This is because we never blocked the requests coming to
Dcache when we had only one target per MSHR.


Best regards,

Abhishek


On Mon, Mar 25, 2019 at 5:09 PM Nikos Nikoleris 
wrote:

> Abhishek,
>
> In that case the code you should be looking at is in
> src/mem/cache/cache.cc in the function handleTimingReqMiss()
>
> mshr->allocateTarget(pkt, forward_time, order++,
>   allocOnFill(pkt->cmd));
> if (mshr->getNumTargets() == numTarget) {
>  noTargetMSHR = mshr;
>  setBlocked(Blocked_NoTargets);
> }
>
> I'm not sure why you don't see any stalls due to no_targets. You might
> want to check how we measure the relevant stats and also make sure that
> the simulation you run will trigger this.
>
> Nikos
>
>
> On 25/03/2019 20:19, Abhishek Singh wrote:
> > I want to have just 1 target per cache line in MHSR queue ie., one
> > target per MSHR entry, but if I set parameter tgt_per_mshr to be 1, I
> > get the number of blocked cycles to zero i.e, there is no blocking due
> > to full targets.
> >
> > If we see the allocateMissBuffer calls code in base.cc and base.hh, the
> > first time we allocate entry to a miss we create a mshr entry and target
> > for that and do not check the tgts_per_mshr parameter. The second time
> > when a miss occurs to the same cache line, we create target for that and
> > then check tgts_per_mshr to block the future requests.
> >
> > The quicker way to find if tgt_per_mshr is working or not when set to 1
> > is to check number for system.cpu.dcache.blocked::no_targets in
> > m5out/stats.txt.
> >
> >
> > Best regards,
> >
> > Abhishek
> >
> >
> >
> > On Mon, Mar 25, 2019 at 4:05 PM Nikos Nikoleris  > <mailto:nikos.nikole...@arm.com>> wrote:
> >
> > Hi Abishek,
> >
> > A single MSHR can keep track of more than one requests for a given
> cache
> > line. If you set tgts_per_mshr to 1, then the MSHR will only be able
> to
> > keep track of a single request for any given cache line. But it can
> >     still service requests to other cache lines by allocating more MSHRs.
> >
> > If you want the cache to block on a single request you will need to
> > limit both the number of MSHRs and tgts_per_mshr to 1.
> >
> > I hope this helps.
> >
> > Nikos
> >
> > On 25/03/2019 19:03, Abhishek Singh wrote:
> >  > Hello Everyone,
> >  >
> >  > I am trying to simulate D-cache with one target per mshr, I tried
> >  > changing the parameter "tgts_per_mshr" defined in
> >  > "co

[gem5-users] FunctionalAccess and Use of tempBlock

[Abhishek Singh]

I would like to clarify a few things:

I want to bypass Dcache i.e., do not allocate anything in Dcache, in order
to do that, I use tempBlock in *handleFill* function in
src/mem/cache/base.cc.

Is this correct, and will not cause any problem?

*Before: *

 blk = allocate ? allocateBlock(pkt, writebacks) : nullptr;

*After:*


if(name() == "system.cpu.dcache”) blk = nullptr;

else

 blk = allocate ? allocateBlock(pkt, writebacks) : nullptr;


Also, what is the use of Functional Access when we use DerivO3CPU, I notice
blk data is being updated or read using the *satisfyRequest* function then
what is to use of using FunctionalAccess in DerivO3CPU.


Best regards,

Abhishek
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[gem5-users] Creating Blocking caches (i.e., 1 target per MSHR)

[Abhishek Singh]

Hello Everyone,

I am trying to simulate D-cache with one target per mshr, I tried changing
the parameter "tgts_per_mshr" defined in "configs/common/Caches.py"  to 1,
it does not work.

This is because when we allocate target for existing MSHR, we always check
the  "tgts_per_mshr" parameter after allocating the second target and
blocks the requests coming from LSQ.

I tried copying the blocking target code to an allocateMissBuffer function
defined and declared in "src/mem/cache/base.hh" as:


*BEFORE*:

MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send =
true)

{

MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,

pkt, time, order++,

allocOnFill(pkt->cmd));


if (mshrQueue.isFull()) {

setBlocked((BlockedCause)MSHRQueue_MSHRs);

}


if (sched_send) {

// schedule the send

schedMemSideSendEvent(time);

}


return mshr;

}



*AFTER:*


MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send =
true)

{

MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,

pkt, time, order++,

allocOnFill(pkt->cmd));


if (mshrQueue.isFull()) {

setBlocked((BlockedCause)MSHRQueue_MSHRs);

}


*if (mshr->getNumTargets() == numTarget) {*



*//cout << "Blocked: " << name() << endl;*

*noTargetMSHR = mshr;*

*setBlocked(Blocked_NoTargets);*

*}*


if (sched_send) {

// schedule the send

schedMemSideSendEvent(time);

}


return mshr;

}

I also change the "tgts_per_mshr" defined in "configs/common/Caches.py" to
1.

But simulation goes into an infinite loop and does not end.

Does anyone have the technique to create Blocking caches with 1 target per
MSHR entry?



Best regards,

Abhishek
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Re: [gem5-users] Creating Blocking caches (i.e., 1 target per MSHR)

[Abhishek Singh]

I want to have just 1 target per cache line in MHSR queue ie., one target
per MSHR entry, but if I set parameter tgt_per_mshr to be 1, I get the
number of blocked cycles to zero i.e, there is no blocking due to full
targets.

If we see the allocateMissBuffer calls code in base.cc and base.hh, the
first time we allocate entry to a miss we create a mshr entry and target
for that and do not check the tgts_per_mshr parameter. The second time when
a miss occurs to the same cache line, we create target for that and then
check tgts_per_mshr to block the future requests.

The quicker way to find if tgt_per_mshr is working or not when set to 1 is
to check number for system.cpu.dcache.blocked::no_targets in
m5out/stats.txt.


Best regards,

Abhishek


On Mon, Mar 25, 2019 at 4:05 PM Nikos Nikoleris 
wrote:

> Hi Abishek,
>
> A single MSHR can keep track of more than one requests for a given cache
> line. If you set tgts_per_mshr to 1, then the MSHR will only be able to
> keep track of a single request for any given cache line. But it can
> still service requests to other cache lines by allocating more MSHRs.
>
> If you want the cache to block on a single request you will need to
> limit both the number of MSHRs and tgts_per_mshr to 1.
>
> I hope this helps.
>
> Nikos
>
> On 25/03/2019 19:03, Abhishek Singh wrote:
> > Hello Everyone,
> >
> > I am trying to simulate D-cache with one target per mshr, I tried
> > changing the parameter "tgts_per_mshr" defined in
> > "configs/common/Caches.py"  to 1, it does not work.
> >
> > This is because when we allocate target for existing MSHR, we always
> > check the  "tgts_per_mshr" parameter after allocating the second target
> > and blocks the requests coming from LSQ.
> >
> > I tried copying the blocking target code to an allocateMissBuffer
> > function defined and declared in "src/mem/cache/base.hh" as:
> >
> >
> > *_BEFORE_*:
> >
> > MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send =
> true)
> >
> > {
> >
> > MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
> >
> > pkt, time, order++,
> >
> > allocOnFill(pkt->cmd));
> >
> >
> > if (mshrQueue.isFull()) {
> >
> > setBlocked((BlockedCause)MSHRQueue_MSHRs);
> >
> > }
> >
> >
> > if (sched_send) {
> >
> > // schedule the send
> >
> > schedMemSideSendEvent(time);
> >
> > }
> >
> >
> > return mshr;
> >
> > }
> >
> >
> >
> > *_AFTER:_*
> >
> >
> >
> > MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send =
> true)
> >
> > {
> >
> > MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
> >
> > pkt, time, order++,
> >
> > allocOnFill(pkt->cmd));
> >
> >
> > if (mshrQueue.isFull()) {
> >
> > setBlocked((BlockedCause)MSHRQueue_MSHRs);
> >
> > }
> >
> >
> > *if (mshr->getNumTargets() == numTarget) {*
> >
> > **
> >
> > *//cout << "Blocked: " << name() << endl;*
> >
> > *noTargetMSHR = mshr;*
> >
> > *setBlocked(Blocked_NoTargets);*
> >
> > *}*
> >
> > *
> > *
> >
> > if (sched_send) {
> >
> > // schedule the send
> >
> > schedMemSideSendEvent(time);
> >
> > }
> >
> >
> > return mshr;
> >
> > }
> >
> >
> > I also change the "tgts_per_mshr" defined in "configs/common/Caches.py"
> > to 1.
> >
> > But simulation goes into an infinite loop and does not end.
> >
> > Does anyone have the technique to create Blocking caches with 1
> > target per MSHR entry?
> >
> >
> >
> > Best regards,
> >
> > Abhishek
> >
> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
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[gem5-users] gem5 X86 Full System fails with DerivO3CPU

[Abhishek Singh]

Hello Everyone,

I am trying to run the gem5 full system with X86 ISA and DerivO3CPU

I have built image and kernel following Jason's Website (ref:
http://www.lowepower.com/jason/setting-up-gem5-full-system.html)
My image is* Ubuntu 16.04.5 LTS*
My kernel is  *Linux-4.8.13*
Gem5 version: Latest as of 6th March 2019

The image and kernel work fine with Atomic and Timing CPU for x86.
But for O3CPU, it gives an error as shown below:
"

command line: *./build/X86/gem5.opt configs/example/fs.py
--script=./script.rcS
--disk-image=/home/abs218/image_kernel/ubuntu-test.img
--kernel=/home/abs218/new_fs/gem5/linux-4.8.13/vmlinux --caches --l2cache
--cpu-type=DerivO3CPU*


Global frequency set at 1 ticks per second

warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (512 Mbytes)

info: kernel located at: /home/abs218/new_fs/gem5/linux-4.8.13/vmlinux

system.pc.com_1.device: Listening for connections on port 3456

  0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012

0: system.remote_gdb: listening for remote gdb on port 7000

warn: Reading current count from inactive timer.

 REAL SIMULATION 

info: Entering event queue @ 0.  Starting simulation...

*gem5.opt: build/X86/mem/packet.hh:1047: T* Packet::getPtr() [with T =
unsigned char]: Assertion `flags.isSet(STATIC_DATA|DYNAMIC_DATA)' failed*.

Program aborted at tick 11637500

--- BEGIN LIBC BACKTRACE ---

./build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x561f4b44d8bc]

./build/X86/gem5.opt(_Z12abortHandleri+0x4a)[0x561f4b45fc8a]

/lib/x86_64-linux-gnu/libpthread.so.0(+0x12890)[0x7f25466db890]

/lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7f2544e02e97]

/lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f2544e04801]

/lib/x86_64-linux-gnu/libc.so.6(+0x3039a)[0x7f2544df439a]

/lib/x86_64-linux-gnu/libc.so.6(+0x30412)[0x7f2544df4412]

./build/X86/gem5.opt(_ZN6X86ISA13handleIprReadEP13ThreadContextP6Packet+0x17c)[0x561f4ace817c]

./build/X86/gem5.opt(_ZN7LSQUnitI9O3CPUImplE4readEPN3LSQIS0_E10LSQRequestEi+0x431)[0x561f4aca8781]

./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE4readEPNS1_10LSQRequestEi+0xad)[0x561f4acee75d]

./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE11pushRequestERK14RefCountingPtrI13BaseO3DynInstIS0_EEbPhjm5FlagsImEPmP15AtomicOpFunctor+0x523)[0x561f4aceecf3]

./build/X86/gem5.opt(_ZN11BaseDynInstI9O3CPUImplE15initiateMemReadEmj5FlagsImE+0x7b)[0x561f4ac8cb3b]

./build/X86/gem5.opt(_ZNK10X86ISAInst5LdBig11initiateAccEP11ExecContextPN5Trace10InstRecordE+0xd1)[0x561f4b99e521]

./build/X86/gem5.opt(_ZN13BaseO3DynInstI9O3CPUImplE11initiateAccEv+0x45)[0x561f4acbfc15]

./build/X86/gem5.opt(_ZN7LSQUnitI9O3CPUImplE11executeLoadERK14RefCountingPtrI13BaseO3DynInstIS0_EE+0x57)[0x561f4acf87e7]

./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE11executeLoadERK14RefCountingPtrI13BaseO3DynInstIS0_EE+0x3b)[0x561f4ace8a0b]

./build/X86/gem5.opt(_ZN10DefaultIEWI9O3CPUImplE12executeInstsEv+0xf06)[0x561f4acd6e96]

./build/X86/gem5.opt(_ZN10DefaultIEWI9O3CPUImplE4tickEv+0x8c0)[0x561f4acda9a0]

./build/X86/gem5.opt(_ZN9FullO3CPUI9O3CPUImplE4tickEv+0x144)[0x561f4acac574]

./build/X86/gem5.opt(_ZN10EventQueue10serviceOneEv+0xd9)[0x561f4b455699]

./build/X86/gem5.opt(_Z9doSimLoopP10EventQueue+0x87)[0x561f4b470e77]

./build/X86/gem5.opt(_Z8simulatem+0xcaa)[0x561f4b471eba]

./build/X86/gem5.opt(+0x5b4d4e)[0x561f4aaedd4e]

./build/X86/gem5.opt(+0x591bf4)[0x561f4aacabf4]

/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x64d7)[0x7f2546995697]

/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7d8)[0x7f2546ac7278]

/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x5bf6)[0x7f2546994db6]

/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7d8)[0x7f2546ac7278]

/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x5bf6)[0x7f2546994db6]

/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7d8)[0x7f2546ac7278]

/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x5bf6)[0x7f2546994db6]

/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7d8)[0x7f2546ac7278]

--- END LIBC BACKTRACE ---

Aborted (core dumped)


When I tried to use AtomicCPU for boot up by fast forwarding it, as soon as
its fast forwarded, simulations get killed with the message shown below:


"""

Switched CPUS @ tick 7034903342000

switching cpus

warn: ClockedObject: Already in the requested power state, request ignored

 REAL SIMULATION 

info: Entering event queue @ 7034903342000.  Starting simulation...

*Killed*

""


I see this message using m5term "*Connection closed by foreign host*."


I can run parsec v2.1 using their image "
http://www.cs.utexas.edu/~cart/parsec_m5/; and gem5's old kernel using x86
03CPU and Fast forwarding.


I want to run some benchmarks which require FS mode of x86, so I developed
new image and kernel and it works correctly for AtomicSimpleCPU and
TimingSimpleCPU.


I also used gdb tool with O3CPU to see 

Re: [gem5-users] Debug for c++

[Abhishek Singh]

Hello Yunxia,

If you want to run pthread application in SE mode, you need to use m5
threads library (ref:https://github.com/gem5/m5threads) or shift to FS mode
of gem5.



Best regards,

Abhishek


On Wed, Mar 6, 2019 at 2:30 PM Yunxia Zhu  wrote:

> Hello everyone,
>
> My OS is Linux Mint 18 Cinnamon 64-bit and Gem5 is in SE mode of x86.
>
> main.cpp
>
> #include 
>
> #include 
>
> #include 
>
>
>
> using namespace std;
>
>
>
> void task1(string msg)
>
> {
>
> cout << "task1 says: " << msg<
> }
>
>
>
> int main()
>
> {
>
> thread t1(task1, "Hello");
>
> t1.join();
>
> }
>
>
> I use this command to compile main.cpp
>
> g++ -std=c++11 -pthread -o main main.cpp
>
> And command for debug information
>
> objdump --dwarf=info main
>
> but there is no result showing. Anyone has same problem? Thank you
>
>
>
> With best regards
>
> Yunxia Zhu
>
>
>
>
>
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Re: [gem5-users] Assertion failure when using DerivO3CPU with full system config

[Abhishek Singh]

Hello Sethu,

Did you try baseline i.e, without making any changes to cache and can you
the also mention the command line statement?

Best regards,

Abhishek


On Tue, Mar 5, 2019 at 1:20 PM Sethu Jose  wrote:

> Hi,
>
> I'm using the full system config explained in this page:
> http://learning.gem5.org/book/part5/fs_config.html#running-a-full-system-simulation
>
> I have modified the cache hierarchy to have a unified L2 cache. This
> config works as long as I use AtomicSimpleCPU or TimingSimpleCPU.
>
> When I switch to DerivO3CPU, it gives run time assertion error in the
> Packet::getPtr() method of mem/packet.hh file. I have added the error to
> the end of this mail.
>
> I have tried with gem5.debug and also with varing sizes for cache.
> However, the assertion is always failing.
>
> Any help would be appreciated.
>
> *Error*:
> Global frequency set at 1 ticks per second
> warn: DRAM device capacity (8192 Mbytes) does not match the address range
> assigned (512 Mbytes)
> info: kernel located at:
> /home/sethu/workspace/_x86/configs/full_system/binaries/x86_64-vmlinux-2.6.22.9
> system.pc.com_1.device: Listening for connections on port 3456
>   0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
> 0: system.remote_gdb: listening for remote gdb on port 7000
> warn: Reading current count from inactive timer.
> Running the simulation
> info: Entering event queue @ 0.  Starting simulation...
> gem5.opt: build/X86/mem/packet.hh:1047: T* Packet::getPtr() [with T =
> unsigned char]: Assertion `flags.isSet(STATIC_DATA|DYNAMIC_DATA)' failed.
> Program aborted at tick 11005983
> --- BEGIN LIBC BACKTRACE ---
> build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x561d1302bccc]
> build/X86/gem5.opt(_Z12abortHandleri+0x4a)[0x561d1303e09a]
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x12890)[0x7faf396a7890]
> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7faf37c83e97]
> /lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7faf37c85801]
> /lib/x86_64-linux-gnu/libc.so.6(+0x3039a)[0x7faf37c7539a]
> /lib/x86_64-linux-gnu/libc.so.6(+0x30412)[0x7faf37c75412]
>
> build/X86/gem5.opt(_ZN6X86ISA13handleIprReadEP13ThreadContextP6Packet+0x17c)[0x561d12365ddc]
>
> build/X86/gem5.opt(_ZN7LSQUnitI9O3CPUImplE4readEPN3LSQIS0_E10LSQRequestEi+0x431)[0x561d12322f71]
>
> build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE4readEPNS1_10LSQRequestEi+0xad)[0x561d1236c77d]
>
> build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE11pushRequestERK14RefCountingPtrI13BaseO3DynInstIS0_EEbPhjm5FlagsImEPmP15AtomicOpFunctor+0x523)[0x561d1236cd13]
>
> build/X86/gem5.opt(_ZN11BaseDynInstI9O3CPUImplE15initiateMemReadEmj5FlagsImE+0x7b)[0x561d1230444b]
>
> build/X86/gem5.opt(_ZNK10X86ISAInst5LdBig11initiateAccEP11ExecContextPN5Trace10InstRecordE+0xd1)[0x561d12867e31]
>
> build/X86/gem5.opt(_ZN13BaseO3DynInstI9O3CPUImplE11initiateAccEv+0x45)[0x561d1233b135]
>
> build/X86/gem5.opt(_ZN7LSQUnitI9O3CPUImplE11executeLoadERK14RefCountingPtrI13BaseO3DynInstIS0_EE+0x57)[0x561d12376e87]
>
> build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE11executeLoadERK14RefCountingPtrI13BaseO3DynInstIS0_EE+0x3b)[0x561d123b]
>
> build/X86/gem5.opt(_ZN10DefaultIEWI9O3CPUImplE12executeInstsEv+0xf06)[0x561d12354696]
>
> build/X86/gem5.opt(_ZN10DefaultIEWI9O3CPUImplE4tickEv+0x8c0)[0x561d123581a0]
> build/X86/gem5.opt(_ZN9FullO3CPUI9O3CPUImplE4tickEv+0x144)[0x561d12326d64]
> build/X86/gem5.opt(_ZN10EventQueue10serviceOneEv+0xd9)[0x561d13033aa9]
> build/X86/gem5.opt(_Z9doSimLoopP10EventQueue+0x87)[0x561d1304f287]
> build/X86/gem5.opt(_Z8simulatem+0xcaa)[0x561d130502ca]
> build/X86/gem5.opt(+0x13741ce)[0x561d131351ce]
> build/X86/gem5.opt(+0x4fd95e)[0x561d122be95e]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x64d7)[0x7faf39961697]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7d8)[0x7faf39a93278]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x5bf6)[0x7faf39960db6]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7d8)[0x7faf39a93278]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCode+0x19)[0x7faf3995b029]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6ac0)[0x7faf39961c80]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7d8)[0x7faf39a93278]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x5bf6)[0x7faf39960db6]
> --- END LIBC BACKTRACE ---
> Aborted (core dumped)
>
> --
> Thanks and Regards,
> Sethu
>
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Re: [gem5-users] Assertion failure when using DerivO3CPU with full system config

[Abhishek Singh]

Can you try this command line:

./build/X86/gem5.opt configs/example/fs.py --cpu-type=DerivO3CPU --caches
--disk-image=(point to ur disk) --kernel=(point to ur kernel)

And try a new image and kernel. For e.g., you can try to use Parsec image
x86 image to test if that works or not. (x86 image:
http://www.cs.utexas.edu/~cart/parsec_m5/)









Best regards,

Abhishek


On Tue, Mar 5, 2019 at 2:46 PM Sethu Jose  wrote:

> Hi Abhishek,
>
> I tried the baseline system without the L2 cache. I get the same error
> when I use the DerivO3CPU.
>
> The command I'm using is 'build/X86/gem5.opt configs/full_system/run.py'.
> I have also tried with gem5.debug.
>
> run.py is same as the file available in this link:
> http://learning.gem5.org/book/part5/fs_config.html#running-a-full-system-simulation
> system.py is same as in the link except that I have modified it to use
> DerivO3CPU. Following are my modification:
>
> self.cpu = DerivO3CPU()
> self.mem_mode = 'timing'
>
> Thanks in advance for any suggestions.
>
> Regards,
> Sethu
>
> On Tue, Mar 5, 2019 at 1:55 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Sethu,
>>
>> Did you try baseline i.e, without making any changes to cache and can you
>> the also mention the command line statement?
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Tue, Mar 5, 2019 at 1:20 PM Sethu Jose  wrote:
>>
>>> Hi,
>>>
>>> I'm using the full system config explained in this page:
>>> http://learning.gem5.org/book/part5/fs_config.html#running-a-full-system-simulation
>>>
>>> I have modified the cache hierarchy to have a unified L2 cache. This
>>> config works as long as I use AtomicSimpleCPU or TimingSimpleCPU.
>>>
>>> When I switch to DerivO3CPU, it gives run time assertion error in the
>>> Packet::getPtr() method of mem/packet.hh file. I have added the error to
>>> the end of this mail.
>>>
>>> I have tried with gem5.debug and also with varing sizes for cache.
>>> However, the assertion is always failing.
>>>
>>> Any help would be appreciated.
>>>
>>> *Error*:
>>> Global frequency set at 1 ticks per second
>>> warn: DRAM device capacity (8192 Mbytes) does not match the address
>>> range assigned (512 Mbytes)
>>> info: kernel located at:
>>> /home/sethu/workspace/_x86/configs/full_system/binaries/x86_64-vmlinux-2.6.22.9
>>> system.pc.com_1.device: Listening for connections on port 3456
>>>   0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
>>> 0: system.remote_gdb: listening for remote gdb on port 7000
>>> warn: Reading current count from inactive timer.
>>> Running the simulation
>>> info: Entering event queue @ 0.  Starting simulation...
>>> gem5.opt: build/X86/mem/packet.hh:1047: T* Packet::getPtr() [with T =
>>> unsigned char]: Assertion `flags.isSet(STATIC_DATA|DYNAMIC_DATA)' failed.
>>> Program aborted at tick 11005983
>>> --- BEGIN LIBC BACKTRACE ---
>>> build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x561d1302bccc]
>>> build/X86/gem5.opt(_Z12abortHandleri+0x4a)[0x561d1303e09a]
>>> /lib/x86_64-linux-gnu/libpthread.so.0(+0x12890)[0x7faf396a7890]
>>> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7faf37c83e97]
>>> /lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7faf37c85801]
>>> /lib/x86_64-linux-gnu/libc.so.6(+0x3039a)[0x7faf37c7539a]
>>> /lib/x86_64-linux-gnu/libc.so.6(+0x30412)[0x7faf37c75412]
>>>
>>> build/X86/gem5.opt(_ZN6X86ISA13handleIprReadEP13ThreadContextP6Packet+0x17c)[0x561d12365ddc]
>>>
>>> build/X86/gem5.opt(_ZN7LSQUnitI9O3CPUImplE4readEPN3LSQIS0_E10LSQRequestEi+0x431)[0x561d12322f71]
>>>
>>> build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE4readEPNS1_10LSQRequestEi+0xad)[0x561d1236c77d]
>>>
>>> build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE11pushRequestERK14RefCountingPtrI13BaseO3DynInstIS0_EEbPhjm5FlagsImEPmP15AtomicOpFunctor+0x523)[0x561d1236cd13]
>>>
>>> build/X86/gem5.opt(_ZN11BaseDynInstI9O3CPUImplE15initiateMemReadEmj5FlagsImE+0x7b)[0x561d1230444b]
>>>
>>> build/X86/gem5.opt(_ZNK10X86ISAInst5LdBig11initiateAccEP11ExecContextPN5Trace10InstRecordE+0xd1)[0x561d12867e31]
>>>
>>> build/X86/gem5.opt(_ZN13BaseO3DynInstI9O3CPUImplE11initiateAccEv+0x45)[0x561d1233b135]
>>>
>>> build/X86/gem5.opt(_ZN7LSQUnitI9O3CPUImplE11executeLoadERK14RefCountingPtrI13BaseO3DynInstIS0_EE+0x57)[0x561d12376e87]
>>>
>>> build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE11executeLoadERK14RefCountingPtrI13BaseO3DynI

Re: [gem5-users] Assertion failure when using DerivO3CPU with full system config

[Abhishek Singh]

So if you use parsec scripts and do not specify cpu type. It has switch cpu
command in its rcS script. And when the simulation is finished, on checking
config.json, you can find O3 cpu running.

On Tue, Mar 5, 2019 at 10:19 PM Sethu Jose  wrote:

> Abhishek,
>
> Thanks you for the confirmation. Could you suggest any earlier version
> where this should work without error?
>
> Regards,
> Sethu
>
> On Tue, 5 Mar 2019, 9:09 PM Abhishek Singh  wrote:
>
>> You are correct Sethu, latest gem5 O3CPU does give an error. Is there
>> anyone in a community who has got O3CPU working with x86 full system mode?
>> If yes, can you share how did you get it working?
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Tue, Mar 5, 2019 at 4:35 PM Sethu Jose  wrote:
>>
>>> Hi Abhishek,
>>>
>>> I tried the parsec images. I get the same error when I'm using out of
>>> order CPU.
>>>
>>> Regards,
>>> Sethu
>>>
>>> On Tue, Mar 5, 2019 at 3:16 PM Abhishek Singh <
>>> abhishek.singh199...@gmail.com> wrote:
>>>
>>>> Can you try this command line:
>>>>
>>>> ./build/X86/gem5.opt configs/example/fs.py --cpu-type=DerivO3CPU
>>>> --caches --disk-image=(point to ur disk) --kernel=(point to ur kernel)
>>>>
>>>> And try a new image and kernel. For e.g., you can try to use Parsec
>>>> image x86 image to test if that works or not. (x86 image:
>>>> http://www.cs.utexas.edu/~cart/parsec_m5/)
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> Best regards,
>>>>
>>>> Abhishek
>>>>
>>>>
>>>> On Tue, Mar 5, 2019 at 2:46 PM Sethu Jose  wrote:
>>>>
>>>>> Hi Abhishek,
>>>>>
>>>>> I tried the baseline system without the L2 cache. I get the same error
>>>>> when I use the DerivO3CPU.
>>>>>
>>>>> The command I'm using is 'build/X86/gem5.opt
>>>>> configs/full_system/run.py'. I have also tried with gem5.debug.
>>>>>
>>>>> run.py is same as the file available in this link:
>>>>> http://learning.gem5.org/book/part5/fs_config.html#running-a-full-system-simulation
>>>>> system.py is same as in the link except that I have modified it to use
>>>>> DerivO3CPU. Following are my modification:
>>>>>
>>>>> self.cpu = DerivO3CPU()
>>>>> self.mem_mode = 'timing'
>>>>>
>>>>> Thanks in advance for any suggestions.
>>>>>
>>>>> Regards,
>>>>> Sethu
>>>>>
>>>>> On Tue, Mar 5, 2019 at 1:55 PM Abhishek Singh <
>>>>> abhishek.singh199...@gmail.com> wrote:
>>>>>
>>>>>> Hello Sethu,
>>>>>>
>>>>>> Did you try baseline i.e, without making any changes to cache and can
>>>>>> you the also mention the command line statement?
>>>>>>
>>>>>> Best regards,
>>>>>>
>>>>>> Abhishek
>>>>>>
>>>>>>
>>>>>> On Tue, Mar 5, 2019 at 1:20 PM Sethu Jose 
>>>>>> wrote:
>>>>>>
>>>>>>> Hi,
>>>>>>>
>>>>>>> I'm using the full system config explained in this page:
>>>>>>> http://learning.gem5.org/book/part5/fs_config.html#running-a-full-system-simulation
>>>>>>>
>>>>>>> I have modified the cache hierarchy to have a unified L2 cache. This
>>>>>>> config works as long as I use AtomicSimpleCPU or TimingSimpleCPU.
>>>>>>>
>>>>>>> When I switch to DerivO3CPU, it gives run time assertion error in
>>>>>>> the Packet::getPtr() method of mem/packet.hh file. I have added the 
>>>>>>> error
>>>>>>> to the end of this mail.
>>>>>>>
>>>>>>> I have tried with gem5.debug and also with varing sizes for cache.
>>>>>>> However, the assertion is always failing.
>>>>>>>
>>>>>>> Any help would be appreciated.
>>>>>>>
>>>>>>> *Error*:
>>>>>>> Global frequency set at 1 ticks per second
>>>>>>> warn: DRAM device capacity

Re: [gem5-users] Assertion failure when using DerivO3CPU with full system config

[Abhishek Singh]

You are correct Sethu, latest gem5 O3CPU does give an error. Is there
anyone in a community who has got O3CPU working with x86 full system mode?
If yes, can you share how did you get it working?

Best regards,

Abhishek


On Tue, Mar 5, 2019 at 4:35 PM Sethu Jose  wrote:

> Hi Abhishek,
>
> I tried the parsec images. I get the same error when I'm using out of
> order CPU.
>
> Regards,
> Sethu
>
> On Tue, Mar 5, 2019 at 3:16 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Can you try this command line:
>>
>> ./build/X86/gem5.opt configs/example/fs.py --cpu-type=DerivO3CPU --caches
>> --disk-image=(point to ur disk) --kernel=(point to ur kernel)
>>
>> And try a new image and kernel. For e.g., you can try to use Parsec image
>> x86 image to test if that works or not. (x86 image:
>> http://www.cs.utexas.edu/~cart/parsec_m5/)
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Tue, Mar 5, 2019 at 2:46 PM Sethu Jose  wrote:
>>
>>> Hi Abhishek,
>>>
>>> I tried the baseline system without the L2 cache. I get the same error
>>> when I use the DerivO3CPU.
>>>
>>> The command I'm using is 'build/X86/gem5.opt
>>> configs/full_system/run.py'. I have also tried with gem5.debug.
>>>
>>> run.py is same as the file available in this link:
>>> http://learning.gem5.org/book/part5/fs_config.html#running-a-full-system-simulation
>>> system.py is same as in the link except that I have modified it to use
>>> DerivO3CPU. Following are my modification:
>>>
>>> self.cpu = DerivO3CPU()
>>> self.mem_mode = 'timing'
>>>
>>> Thanks in advance for any suggestions.
>>>
>>> Regards,
>>> Sethu
>>>
>>> On Tue, Mar 5, 2019 at 1:55 PM Abhishek Singh <
>>> abhishek.singh199...@gmail.com> wrote:
>>>
>>>> Hello Sethu,
>>>>
>>>> Did you try baseline i.e, without making any changes to cache and can
>>>> you the also mention the command line statement?
>>>>
>>>> Best regards,
>>>>
>>>> Abhishek
>>>>
>>>>
>>>> On Tue, Mar 5, 2019 at 1:20 PM Sethu Jose  wrote:
>>>>
>>>>> Hi,
>>>>>
>>>>> I'm using the full system config explained in this page:
>>>>> http://learning.gem5.org/book/part5/fs_config.html#running-a-full-system-simulation
>>>>>
>>>>> I have modified the cache hierarchy to have a unified L2 cache. This
>>>>> config works as long as I use AtomicSimpleCPU or TimingSimpleCPU.
>>>>>
>>>>> When I switch to DerivO3CPU, it gives run time assertion error in the
>>>>> Packet::getPtr() method of mem/packet.hh file. I have added the error to
>>>>> the end of this mail.
>>>>>
>>>>> I have tried with gem5.debug and also with varing sizes for cache.
>>>>> However, the assertion is always failing.
>>>>>
>>>>> Any help would be appreciated.
>>>>>
>>>>> *Error*:
>>>>> Global frequency set at 1 ticks per second
>>>>> warn: DRAM device capacity (8192 Mbytes) does not match the address
>>>>> range assigned (512 Mbytes)
>>>>> info: kernel located at:
>>>>> /home/sethu/workspace/_x86/configs/full_system/binaries/x86_64-vmlinux-2.6.22.9
>>>>> system.pc.com_1.device: Listening for connections on port 3456
>>>>>   0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
>>>>> 0: system.remote_gdb: listening for remote gdb on port 7000
>>>>> warn: Reading current count from inactive timer.
>>>>> Running the simulation
>>>>> info: Entering event queue @ 0.  Starting simulation...
>>>>> gem5.opt: build/X86/mem/packet.hh:1047: T* Packet::getPtr() [with T =
>>>>> unsigned char]: Assertion `flags.isSet(STATIC_DATA|DYNAMIC_DATA)' failed.
>>>>> Program aborted at tick 11005983
>>>>> --- BEGIN LIBC BACKTRACE ---
>>>>> build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x561d1302bccc]
>>>>> build/X86/gem5.opt(_Z12abortHandleri+0x4a)[0x561d1303e09a]
>>>>> /lib/x86_64-linux-gnu/libpthread.so.0(+0x12890)[0x7faf396a7890]
>>>>> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7faf37c83e97]
>>>>> /lib/x86_64-linux-gnu/libc.so.6(abort+0x

Re: [gem5-users] Assert error while running FS

[Abhishek Singh]

Hello,
Can you post the command line?

On Sat, Mar 16, 2019 at 7:37 AM Ashok Sathyan  wrote:

> Dear All,
>
> I downloaded a fresh copy of gem5
> (9e22a2ab603d743b187108986cfbeba07c0c0b8d) and it giving a assert error
> while trying to run it in FS. I haven't done any modifications to the code.
> Any help will be appreciated. Thanks
>
> info: Entering event queue @ 0.  Starting simulation...
> gem5.opt: build/X86/mem/packet.hh:1047: T* Packet::getPtr() [with T =
> unsigned char]: Assertion `flags.isSet(STATIC_DATA|DYNAMIC_DATA)' failed.
> Program aborted at tick 14603000
> --- BEGIN LIBC BACKTRACE ---
> ./build/X86/gem5.opt(_Z15print_backtracev+0x28)[0xfce178]
> ./build/X86/gem5.opt(_Z12abortHandleri+0x46)[0xfdea36]
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x11390)[0x7fdc2407c390]
> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0x38)[0x7fdc22a84428]
> /lib/x86_64-linux-gnu/libc.so.6(abort+0x16a)[0x7fdc22a8602a]
> /lib/x86_64-linux-gnu/libc.so.6(+0x2dbd7)[0x7fdc22a7cbd7]
> /lib/x86_64-linux-gnu/libc.so.6(+0x2dc82)[0x7fdc22a7cc82]
>
> ./build/X86/gem5.opt(_ZN6X86ISA13handleIprReadEP13ThreadContextP6Packet+0x13e)[0x1073ece]
>
> ./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE17SingleDataRequest13handleIprReadEP13ThreadContextP6Packet+0xf)[0x1639a5f]
>
> ./build/X86/gem5.opt(_ZN7LSQUnitI9O3CPUImplE4readEPN3LSQIS0_E10LSQRequestEi+0x639)[0x15fe4a9]
>
> ./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE4readEPNS1_10LSQRequestEi+0xac)[0x163f68c]
>
> ./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE11pushRequestERK14RefCountingPtrI13BaseO3DynInstIS0_EEbPhjm5FlagsImEPmP15AtomicOpFunctor+0x45c)[0x163fb4c]
>
> ./build/X86/gem5.opt(_ZN11BaseDynInstI9O3CPUImplE15initiateMemReadEmj5FlagsImE+0x81)[0x15e49a1]
>
> ./build/X86/gem5.opt(_ZNK10X86ISAInst5LdBig11initiateAccEP11ExecContextPN5Trace10InstRecordE+0x128)[0xbc5de8]
>
> ./build/X86/gem5.opt(_ZN13BaseO3DynInstI9O3CPUImplE11initiateAccEv+0x45)[0x1610b55]
>
> ./build/X86/gem5.opt(_ZN7LSQUnitI9O3CPUImplE11executeLoadERK14RefCountingPtrI13BaseO3DynInstIS0_EE+0x55)[0x16495e5]
>
> ./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE11executeLoadERK14RefCountingPtrI13BaseO3DynInstIS0_EE+0x3b)[0x163a1bb]
>
> ./build/X86/gem5.opt(_ZN10DefaultIEWI9O3CPUImplE12executeInstsEv+0xddd)[0x1627a4d]
> ./build/X86/gem5.opt(_ZN10DefaultIEWI9O3CPUImplE4tickEv+0x13a)[0x162bdea]
> ./build/X86/gem5.opt(_ZN9FullO3CPUI9O3CPUImplE4tickEv+0x133)[0x1600733]
> ./build/X86/gem5.opt(_ZN10EventQueue10serviceOneEv+0xc5)[0xfd4b15]
> ./build/X86/gem5.opt(_Z9doSimLoopP10EventQueue+0x50)[0xfedc80]
> ./build/X86/gem5.opt(_Z8simulatem+0xd1b)[0xfeed6b]
> ./build/X86/gem5.opt[0xd1745a]
> ./build/X86/gem5.opt[0xcb6f97]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x7852)[0x7fdc243397b2]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x85c)[0x7fdc2447011c]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6ffd)[0x7fdc24338f5d]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x85c)[0x7fdc2447011c]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6ffd)[0x7fdc24338f5d]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x85c)[0x7fdc2447011c]
>
> /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6ffd)[0x7fdc24338f5d]
> --- END LIBC BACKTRACE ---
>
>
>
> --
> Regards,
> Ashok Sathyan
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Re: [gem5-users] Assert error while running FS

[Abhishek Singh]

Hello Ashok,

Just change the CPU type to Timing or Atomic. Gem5 FS x86 mode gives the
assertion error when used with O3CPU directly.

The way you can use O3CPU, is to Fast Forward boot process or use
checkpointing technique i.e., create checkpoints with Atomic CPU and then
restore with DerivO3CPU.

On Sat, Mar 16, 2019 at 9:15 AM Ashok Sathyan  wrote:

> ./build/X86/gem5.opt -d results/gcc configs/example/fs.py --caches
> --cpu-type=DerivO3CPU
>
>
> --
> Regards,
> Ashok Sathyan
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Re: [gem5-users] Assert error while running FS

[Abhishek Singh]

I have not dugged into the problem yet.

I did post about the problem in past.


I am sure that it’s related to boot up process.



On Sat, Mar 16, 2019 at 9:44 AM Ashok Sathyan  wrote:

> Hi Abhishek,
>
> It is working as you suggested, Any idea why it's not working when I start
> with DerivO3CPU.
>
> On Sat, Mar 16, 2019 at 6:50 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Ashok,
>>
>> Just change the CPU type to Timing or Atomic. Gem5 FS x86 mode gives the
>> assertion error when used with O3CPU directly.
>>
>> The way you can use O3CPU, is to Fast Forward boot process or use
>> checkpointing technique i.e., create checkpoints with Atomic CPU and then
>> restore with DerivO3CPU.
>>
>> On Sat, Mar 16, 2019 at 9:15 AM Ashok Sathyan 
>> wrote:
>>
>>> ./build/X86/gem5.opt -d results/gcc configs/example/fs.py --caches
>>> --cpu-type=DerivO3CPU
>>>
>>>
>>> --
>>> Regards,
>>> Ashok Sathyan
>>> ___
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>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>> ___
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>
>
>
> --
> Regards,
> Ashok Sathyan
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Re: [gem5-users] Does SE account for system call cycles and instructions?

[Abhishek Singh]

Thanks Jason

On Thu, Mar 7, 2019 at 12:32 PM Jason Lowe-Power 
wrote:

> Hi Abhishek,
>
> No, it does not account for cycle or instructions. If you need this
> information you should use FS mode.
>
> I believe the syscalls are serializing instructions. It depends on the
> CPU's implementation of that semantic.
>
> Jason
>
> On Thu, Mar 7, 2019 at 9:27 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Everyone,
>>
>> I have some questions regarding already defined system call in gem5 SE
>> x86.
>>
>> I understand this system calls for a benchmark in SE mode are ran over
>> host machine but does gem5 SE (simulator) account for the number of
>> instructions and cycles for running this system calls.
>>
>> Is the O3 pipeline flushed when you run a system call in gem5 SE x86
>> using O3CPU?
>>
>>
>> Best regards,
>>
>> Abhishek
>>
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Re: [gem5-users] Commonitor

[Abhishek Singh]

Hi,

A smart way to know how many instruction to Fastforward is to use dump
stats just after boot up for the first run and then see instruction count.

Second way is to use checkpointing technique for the boot-up and then
restore from that and then run your application.

For monitoring accesses I would have defined new stats if it’s already not
there.

On Thu, Mar 7, 2019 at 4:03 AM Morteza Soltani <
morteza.soltani8...@gmail.com> wrote:

> Hi
> I want to monitor DRAM access after LLC request in full system simulation
> of gem5. I want to know that, how can i enable commonitor feature after
> going to run benchmark (into ROI)?
> "I am familiar with fast-forward mode but i don't have any information
> about the number of instruction before running each benchmark"
>
>
> --
>
>*Sincerely Yours,*
>
>*Morteza Soltani*
>
>
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[gem5-users] Bypass Dcache gives tcmalloc error

[Abhishek Singh]

Hello Everyone,

I am trying to bypass Dcache, the way I do it is in src/mem/cache/base.cc
file in allocateBlock function, I return "nullptr" for Dcache.

It works correctly for small size applications but gives this error
*"**src/tcmalloc.cc:283]
Attempt to free invalid pointer 0x563d2c5" *for bigger application size.

Have anyone encountered this error?





Best regards,

Abhishek
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Re: [gem5-users] (no subject)

[Abhishek Singh]

Your logic sounds correct to me for single core.

For multi core, the last level cache is shared, and you can get block from
other core’s L1 dcache.
So you need to think through about what behavior you are expecting from
your design and make changes or keep things same.

On Mon, May 13, 2019 at 12:02 AM Muhammad Avais 
wrote:

> Dear Abhishek,
>
>  Many thanks for your reply. I will set the flag in response packet
> for L2 hit. This flag will be default reset, therefore, I think I will not
> need main memory flag in this case.
>  Please, let me know if you feel a problem in this logic.
>  For multicore simulation, what should be the difference?
>
> Many thanks for your response,
> Best regards,
> Avais
>
> On Sat, May 11, 2019 at 8:15 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> What you do, is create flags in src/mem/packet.hh for various cache
>> levels.
>> Whenever you hit in L2, you can set the L2flag in response pkt.
>> And if it is misses in L2, set main memory flag in response pkt, as you
>> are sure you will get data from main memory.
>> Here we are assuming it’s a single core simulation.
>>
>> On Fri, May 10, 2019 at 5:42 AM Muhammad Avais 
>> wrote:
>>
>>> Dear All,
>>>
>>> 1- For blocks loaded in the L1 cache, how can I distinguish that it was
>>> loaded into the L1 cache from the L2 cache (L2 hit) or main memory (L1
>>> cache)?
>>>
>>> Many thanks,
>>> Best Regards,
>>> Avais
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Re: [gem5-users] Update an architectural register on eviction from dCache

[Abhishek Singh]

Thank you!
This information helps a lot !

On Fri, May 17, 2019 at 2:13 PM Gabe Black  wrote:

> Hi Abhishek. You would probably want accesses to the MISCREG_* to go find
> the cache and ask it what value to reply with instead of the other way
> around. The system doesn't necessarily have caches or a particular number
> or topology of caches, so you'll likely need to set up some custom plumbing
> so the register code and the cache code can find each other in your setup.
>
> Gabe
>
> On Thu, May 16, 2019, 10:47 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Has anyone used Model Specific register in caches?
>> That is, to set single bit value in any of the MSR from caches?
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Wed, May 15, 2019 at 2:54 PM Abhishek Singh <
>> abhishek.singh199...@gmail.com> wrote:
>>
>>> Hello Everyone and Gabe,
>>>
>>> I am having difficulty in finding a way to implment a new register in
>>> X86 ISA which is set one when an eviction occurs in dCache.
>>>
>>> Does anyone know which files, I should look into or any suggestions on
>>> how to achieve this implementation?
>>>
>>>
>>> Best regards,
>>>
>>> Abhishek
>>>
>>
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Re: [gem5-users] (no subject)

[Abhishek Singh]

What you do, is create flags in src/mem/packet.hh for various cache levels.
Whenever you hit in L2, you can set the L2flag in response pkt.
And if it is misses in L2, set main memory flag in response pkt, as you are
sure you will get data from main memory.
Here we are assuming it’s a single core simulation.

On Fri, May 10, 2019 at 5:42 AM Muhammad Avais 
wrote:

> Dear All,
>
> 1- For blocks loaded in the L1 cache, how can I distinguish that it was
> loaded into the L1 cache from the L2 cache (L2 hit) or main memory (L1
> cache)?
>
> Many thanks,
> Best Regards,
> Avais
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Re: [gem5-users] Bypassing blocks to LLC

[Abhishek Singh]

Hi Richard,

What you can do is, wherever your desired block reaches at L3 level in the
form of a packet that is in “recvTimingReq” function, instead of writing in
L3. Create a write-back queue entry at L3 for that pkt and then it should
automatically go to Main memory.

On Thu, May 2, 2019 at 7:08 PM Richard Brown 
wrote:

> Hello everyone,
>
> I am PhD student and new with gem5, I have a multicore system with 2
> private cache levels (DL1, IL1 and L2) and 1 shared L3/LLC. I am using
> classic memory system, I know this model is non-inclusive, non-exclusive.
>
> For my research I need to bypass some blocks from L3, I mean when some
> blocks are read I want to write them to L1 and L2 and not write them in L3,
> and when some blocks are evicted from L2, if they are dirty, I want to
> write them to Main Memory and not to L3.
>
> Is it possible to bypass some blocks from L3 reading the accesses
> messages? I think I just need to change cache.cc, is it right?
>
> I really apreciate your help, thanks in advance.
>
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Re: [gem5-users] (no subject)

[Abhishek Singh]

Hi Muhammad,

One way is to use the function "name()" in src/mem/cache/base.cc and
src/mem/cache/cache.cc file to implement cache specific function.
For e.g.,
for implementing things specifically  for dcache u can just write if
(name() == "system.cpu.dcache"){ }


Best regards,

Abhishek


On Fri, May 10, 2019 at 5:23 AM Muhammad Avais 
wrote:

>Dear All,
>
>   I have one question. For blocks loaded in the L1 cache, how can I
> distinguish that it was loaded into the L1 cache from L2 cache or main
> memory?
>
> Many thanks,
> Best regards,
> Avais
>
>
> On Wed, May 8, 2019 at 5:21 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hi Muhammad,
>>
>>
>> If you want on L2 hit, the block is invalidated from L2 cache and filled
>> in Dcache and the rest behavior same as you explained in the diagram, you
>> can use gem5's "most_excl" option in "gem5/src/mem/cache/Cache.py" file.
>> You may need to take care of "clean victim" from dcache which is not a
>> difficult modification.
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Tue, May 7, 2019 at 1:48 AM Muhammad Avais 
>> wrote:
>>
>>> Dear All,
>>>   Is 'mostly exclusive cache' supported in GEM5 classic model
>>> strictly non-exclusive cache? If it is not non-exclusive cache, how can I
>>> make it non-exclusive cache?
>>>
>>>   The non-exclusive cache is shown in Fig. below.
>>> [image: image.png]
>>>  Can anyone guide me?
>>>
>>> Many thanks,
>>> best regards,
>>> Avais
>>>
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Re: [gem5-users] Update an architectural register on eviction from dCache

[Abhishek Singh]

Has anyone used Model Specific register in caches?
That is, to set single bit value in any of the MSR from caches?

Best regards,

Abhishek


On Wed, May 15, 2019 at 2:54 PM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hello Everyone and Gabe,
>
> I am having difficulty in finding a way to implment a new register in X86
> ISA which is set one when an eviction occurs in dCache.
>
> Does anyone know which files, I should look into or any suggestions on how
> to achieve this implementation?
>
>
> Best regards,
>
> Abhishek
>
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[gem5-users] Update an architectural register on eviction from dCache

[Abhishek Singh]

Hello Everyone and Gabe,

I am having difficulty in finding a way to implment a new register in X86
ISA which is set one when an eviction occurs in dCache.

Does anyone know which files, I should look into or any suggestions on how
to achieve this implementation?


Best regards,

Abhishek
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Re: [gem5-users] (no subject)

[Abhishek Singh]

Hello Nazish,

If you are using classic memory, edit src/mem/cache/base.cc file’s
recvTimingReq function.
You can access the old data through blk->data and the new data by
pkt->getdata(this you need to search in src/mem/packet.hh, I may have made
mistake in writing correct name of the function).

On Sun, May 12, 2019 at 2:52 AM Nazish Shabbir 
wrote:

>  Hello! I am relatively new to gem5 and trying to implement an encoding
> scheme in it but not exactly sure what the best approach to implementing
> this would be.
>
> The way i would like this to work is when there is a write access to the
> last level cache, we need to read the old data in the last level cache.
> Then we compare the new cache line with the old cache line to calculate the
> HTs and STs.
>
> Where would you recommend i look to start implementing this? Which place
> i need to start modifying?
>
> Thanks!
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Re: [gem5-users] (no subject)

[Abhishek Singh]

Hi Muhammad,


If you want on L2 hit, the block is invalidated from L2 cache and filled in
Dcache and the rest behavior same as you explained in the diagram, you can
use gem5's "most_excl" option in "gem5/src/mem/cache/Cache.py" file.
You may need to take care of "clean victim" from dcache which is not a
difficult modification.

Best regards,

Abhishek


On Tue, May 7, 2019 at 1:48 AM Muhammad Avais 
wrote:

> Dear All,
>   Is 'mostly exclusive cache' supported in GEM5 classic model strictly
> non-exclusive cache? If it is not non-exclusive cache, how can I make it
> non-exclusive cache?
>
>   The non-exclusive cache is shown in Fig. below.
> [image: image.png]
>  Can anyone guide me?
>
> Many thanks,
> best regards,
> Avais
>
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Re: [gem5-users] Error during gem5 full system simulation with DerivO3CPU

[Abhishek Singh]

Use an older commit
It solves the problem

On Sat, Apr 20, 2019 at 1:48 PM ABHISHEK BHATTACHARYYA <
abhattach...@wisc.edu> wrote:

> Hi
>
> I am trying to run a full system simulation with DerivO3CPU and a mesh
> interconnect model from garnet2.0. However, the simulation fails giving the
> following error message. Any idea what can be wrong?
>
> build/X86_MESI_Two_Level/mem/packet.hh:1047: T* Packet::getPtr() [with T =
> unsigned char]: Assertion `flags.isSet(STATIC_DATA|DYNAMIC_DATA)' failed.
>
> Regards,
>
>
> Abhishek Bhattacharyya
>
> *Graduate Research Assistant*
>
> *Electrical and Computer Engineering Department*
>
> *University of Wisconsin-Madison*
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Re: [gem5-users] Error during gem5 full system simulation with DerivO3CPU

[Abhishek Singh]

Hi Abhishek,

This commit works perfectly 6379bebd41899ca74ac146e8073aee0bd1781b3f


Best regards,

Abhishek


On Mon, Apr 22, 2019 at 2:58 PM ABHISHEK BHATTACHARYYA <
abhattach...@wisc.edu> wrote:

> Thanks, Abhishek. Do you know which previous commit will work fine?
> --
> *From:* gem5-users  on behalf of Abhishek
> Singh 
> *Sent:* Saturday, April 20, 2019 12:54 PM
> *To:* gem5 users mailing list
> *Subject:* Re: [gem5-users] Error during gem5 full system simulation with
> DerivO3CPU
>
> Use an older commit
> It solves the problem
>
> On Sat, Apr 20, 2019 at 1:48 PM ABHISHEK BHATTACHARYYA <
> abhattach...@wisc.edu> wrote:
>
> Hi
>
> I am trying to run a full system simulation with DerivO3CPU and a mesh
> interconnect model from garnet2.0. However, the simulation fails giving the
> following error message. Any idea what can be wrong?
>
> build/X86_MESI_Two_Level/mem/packet.hh:1047: T* Packet::getPtr() [with T =
> unsigned char]: Assertion `flags.isSet(STATIC_DATA|DYNAMIC_DATA)' failed.
>
> Regards,
>
>
> Abhishek Bhattacharyya
>
> *Graduate Research Assistant*
>
> *Electrical and Computer Engineering Department*
>
> *University of Wisconsin-Madison*
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Re: [gem5-users] gem5 X86 Full System fails with DerivO3CPU

[Abhishek Singh]

Hello Everyone,

Yaz: I do not change anything, I am using commit
2a98a994df296f818b05da90ba073d879562da04
of gem5.

Is there anyone who was able to *boot* the full system for x86 ISA using
O3CPU?

My command line :

*build/X86/gem5.opt configs/example/fs.py  --kernel=x86_64-vmlinux-2.6.22.9
--disk-image=linux-x86.img --cpu-type=DerivO3CPU --caches*

Best regards,

Abhishek


On Fri, Mar 8, 2019 at 2:09 PM Ayaz Akram  wrote:

> Hi Abhishek,
>
> I wonder if you are using the default CPU configuration for full-system or
> do you have any changes?
>
> Regards
> -Ayaz
>
> On Wed, Mar 6, 2019 at 2:20 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Everyone,
>>
>> I am trying to run the gem5 full system with X86 ISA and DerivO3CPU
>>
>> I have built image and kernel following Jason's Website (ref:
>> http://www.lowepower.com/jason/setting-up-gem5-full-system.html)
>> My image is* Ubuntu 16.04.5 LTS*
>> My kernel is  *Linux-4.8.13*
>> Gem5 version: Latest as of 6th March 2019
>>
>> The image and kernel work fine with Atomic and Timing CPU for x86.
>> But for O3CPU, it gives an error as shown below:
>> """""""""
>>
>> command line: *./build/X86/gem5.opt configs/example/fs.py
>> --script=./script.rcS
>> --disk-image=/home/abs218/image_kernel/ubuntu-test.img
>> --kernel=/home/abs218/new_fs/gem5/linux-4.8.13/vmlinux --caches --l2cache
>> --cpu-type=DerivO3CPU*
>>
>>
>> Global frequency set at 1 ticks per second
>>
>> warn: DRAM device capacity (8192 Mbytes) does not match the address range
>> assigned (512 Mbytes)
>>
>> info: kernel located at: /home/abs218/new_fs/gem5/linux-4.8.13/vmlinux
>>
>> system.pc.com_1.device: Listening for connections on port 3456
>>
>>   0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
>>
>> 0: system.remote_gdb: listening for remote gdb on port 7000
>>
>> warn: Reading current count from inactive timer.
>>
>>  REAL SIMULATION 
>>
>> info: Entering event queue @ 0.  Starting simulation...
>>
>> *gem5.opt: build/X86/mem/packet.hh:1047: T* Packet::getPtr() [with T =
>> unsigned char]: Assertion `flags.isSet(STATIC_DATA|DYNAMIC_DATA)' failed*
>> .
>>
>> Program aborted at tick 11637500
>>
>> --- BEGIN LIBC BACKTRACE ---
>>
>> ./build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x561f4b44d8bc]
>>
>> ./build/X86/gem5.opt(_Z12abortHandleri+0x4a)[0x561f4b45fc8a]
>>
>> /lib/x86_64-linux-gnu/libpthread.so.0(+0x12890)[0x7f25466db890]
>>
>> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7f2544e02e97]
>>
>> /lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f2544e04801]
>>
>> /lib/x86_64-linux-gnu/libc.so.6(+0x3039a)[0x7f2544df439a]
>>
>> /lib/x86_64-linux-gnu/libc.so.6(+0x30412)[0x7f2544df4412]
>>
>>
>> ./build/X86/gem5.opt(_ZN6X86ISA13handleIprReadEP13ThreadContextP6Packet+0x17c)[0x561f4ace817c]
>>
>>
>> ./build/X86/gem5.opt(_ZN7LSQUnitI9O3CPUImplE4readEPN3LSQIS0_E10LSQRequestEi+0x431)[0x561f4aca8781]
>>
>>
>> ./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE4readEPNS1_10LSQRequestEi+0xad)[0x561f4acee75d]
>>
>>
>> ./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE11pushRequestERK14RefCountingPtrI13BaseO3DynInstIS0_EEbPhjm5FlagsImEPmP15AtomicOpFunctor+0x523)[0x561f4aceecf3]
>>
>>
>> ./build/X86/gem5.opt(_ZN11BaseDynInstI9O3CPUImplE15initiateMemReadEmj5FlagsImE+0x7b)[0x561f4ac8cb3b]
>>
>>
>> ./build/X86/gem5.opt(_ZNK10X86ISAInst5LdBig11initiateAccEP11ExecContextPN5Trace10InstRecordE+0xd1)[0x561f4b99e521]
>>
>>
>> ./build/X86/gem5.opt(_ZN13BaseO3DynInstI9O3CPUImplE11initiateAccEv+0x45)[0x561f4acbfc15]
>>
>>
>> ./build/X86/gem5.opt(_ZN7LSQUnitI9O3CPUImplE11executeLoadERK14RefCountingPtrI13BaseO3DynInstIS0_EE+0x57)[0x561f4acf87e7]
>>
>>
>> ./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE11executeLoadERK14RefCountingPtrI13BaseO3DynInstIS0_EE+0x3b)[0x561f4ace8a0b]
>>
>>
>> ./build/X86/gem5.opt(_ZN10DefaultIEWI9O3CPUImplE12executeInstsEv+0xf06)[0x561f4acd6e96]
>>
>>
>> ./build/X86/gem5.opt(_ZN10DefaultIEWI9O3CPUImplE4tickEv+0x8c0)[0x561f4acda9a0]
>>
>>
>> ./build/X86/gem5.opt(_ZN9FullO3CPUI9O3CPUImplE4tickEv+0x144)[0x561f4acac574]
>>
>> ./build/X86/gem5.opt(_ZN10EventQueue10serviceOneEv+0xd9)[0x561f4b455699]
>>
>> ./build/X86/gem5.opt(_Z9doSimLoopP10EventQueue+0x87)[0x561f4b470e77]
>>
>> ./build/X86/gem5.opt(_Z8simulatem+0xcaa)[0x561f4b471eba]
>>
>> ./build/X86/gem5.opt(+0x

[gem5-users] Full System X86 restoring from checkpoint questions

[Abhishek Singh]

Hello Everyone,

I have created the checkpoint for booting up Linux image.
My command line is
"""

build/X86/gem5.opt
--outdir=/home/abs218/gem5_dir_local/gem5_bl_fs/common_checkpoint_chkpt
--stats-file=common_checkpoint_chkpt.simout
--dump-config=common_checkpoint_chkpt.ini --redirect-stderr
--stderr-file=common_checkpoint_chkpt.e configs/example/fs.py
--checkpoint-dir=/home/abs218/gem5_dir_local/gem5_bl_fs/common_checkpoint_chkpt
--disk-image=/home/abs218/gem5_dir_local/gem5_bl_fs/intel.img
--kernel=/home/abs218/new_fs/gem5/linux-4.8.13/vmlinux
--script=./common_checkpoint.rcS --caches --l2cache


"""

my common_checkpoint.rcS is

"""

#!/bin/sh

/sbin/m5 checkpoint

echo "Done :D"

/sbin/m5 exit


"""

I wanted to use this checkpoint and try to run a hello_world benchmark.
So I modify my common_checkpoint.rcS script to
"""

#!/bin/sh

./hello_world

echo "Done :D"

/sbin/m5 exit

"""
And my gem5 command line is
"""
./build/X86/gem5.opt
--outdir=/home/abs218/gem5_dir_local/gem5_bl_fs/common_checkpoint_chkpt
--stats-file=common_checkpoint_chkpt_restore.simout
--dump-config=common_checkpoint_chkpt_restore.ini configs/example/fs.py
--checkpoint-restore=1
--checkpoint-dir=/home/abs218/gem5_dir_local/gem5_bl_fs/common_checkpoint_chkpt
--restore-with-cpu=AtomicSimpleCPU --cpu-type=DerivO3CPU --caches --l2cache
--disk-image=/home/abs218/gem5_dir_local/gem5_bl_fs/intel.img
--kernel=/home/abs218/new_fs/gem5/linux-4.8.13/vmlinux
--script=./common_checkpoint.rcS
"""
But my "system.pc.com_1.device" output after restoring  is
""

Done :D
""
That is, it did not run the hello_world program!

I have made no changes to gem5, the commit I am using is "
2a98a994df296f818b05da90ba073d879562da04"


My question is:
Is it not possible to create a common checkpoint and then run the benchmark
using that checkpoint?
Are my steps incorrect to create or restore from the checkpoint?




Best regards,

Abhishek
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Re: [gem5-users] Full System X86 restoring from checkpoint questions

[Abhishek Singh]

Thank you for the clarification.

On Fri, Aug 30, 2019 at 12:43 PM Jason Lowe-Power 
wrote:

> Hi Abhishek,
>
> You have to use something like the hack back script if you want to change
> your script parameter after checkpointing. When you checkpoint, it saves
> the state of the system. When you restore, it's restored with *exactly that
> state.* I.e., your original rcS file is still on the disk. If you want to
> change the rcS file, your original file must call m5 readfile twice. Hence,
> the hack back script calls it a second time (the first time is, by
> definition, outside of the rcS script).
>
> Jason
>
> On Fri, Aug 30, 2019 at 9:39 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hi Pouya and Jason,
>> Yes the binary is present.
>> My question is it necessary to run the binary after the checkpoint
>> command that is after “/sbin/m5 checkpoint”
>> And if yes why?
>>
>> On Fri, Aug 30, 2019 at 12:30 PM Pouya Fotouhi 
>> wrote:
>>
>>> Hi Abhishek,
>>>
>>> Do you have your binary (hello_world) on your disk image? To be more
>>> precise, was the binary on the disk image when you took the checkpoint?
>>>
>>> Best,
>>>
>>> On Fri, Aug 30, 2019 at 8:26 AM Abhishek Singh <
>>> abhishek.singh199...@gmail.com> wrote:
>>>
>>>> Hello Everyone,
>>>>
>>>> I have created the checkpoint for booting up Linux image.
>>>> My command line is
>>>> """
>>>>
>>>> build/X86/gem5.opt
>>>> --outdir=/home/abs218/gem5_dir_local/gem5_bl_fs/common_checkpoint_chkpt
>>>> --stats-file=common_checkpoint_chkpt.simout
>>>> --dump-config=common_checkpoint_chkpt.ini --redirect-stderr
>>>> --stderr-file=common_checkpoint_chkpt.e configs/example/fs.py
>>>> --checkpoint-dir=/home/abs218/gem5_dir_local/gem5_bl_fs/common_checkpoint_chkpt
>>>> --disk-image=/home/abs218/gem5_dir_local/gem5_bl_fs/intel.img
>>>> --kernel=/home/abs218/new_fs/gem5/linux-4.8.13/vmlinux
>>>> --script=./common_checkpoint.rcS --caches --l2cache
>>>>
>>>>
>>>> """
>>>>
>>>> my common_checkpoint.rcS is
>>>>
>>>> """
>>>>
>>>> #!/bin/sh
>>>>
>>>> /sbin/m5 checkpoint
>>>>
>>>> echo "Done :D"
>>>>
>>>> /sbin/m5 exit
>>>>
>>>>
>>>> """
>>>>
>>>> I wanted to use this checkpoint and try to run a hello_world benchmark.
>>>> So I modify my common_checkpoint.rcS script to
>>>> """
>>>>
>>>> #!/bin/sh
>>>>
>>>> ./hello_world
>>>>
>>>> echo "Done :D"
>>>>
>>>> /sbin/m5 exit
>>>>
>>>> """
>>>> And my gem5 command line is
>>>> """
>>>> ./build/X86/gem5.opt
>>>> --outdir=/home/abs218/gem5_dir_local/gem5_bl_fs/common_checkpoint_chkpt
>>>> --stats-file=common_checkpoint_chkpt_restore.simout
>>>> --dump-config=common_checkpoint_chkpt_restore.ini configs/example/fs.py
>>>> --checkpoint-restore=1
>>>> --checkpoint-dir=/home/abs218/gem5_dir_local/gem5_bl_fs/common_checkpoint_chkpt
>>>> --restore-with-cpu=AtomicSimpleCPU --cpu-type=DerivO3CPU --caches --l2cache
>>>> --disk-image=/home/abs218/gem5_dir_local/gem5_bl_fs/intel.img
>>>> --kernel=/home/abs218/new_fs/gem5/linux-4.8.13/vmlinux
>>>> --script=./common_checkpoint.rcS
>>>> """
>>>> But my "system.pc.com_1.device" output after restoring  is
>>>> ""
>>>>
>>>> Done :D
>>>> ""
>>>> That is, it did not run the hello_world program!
>>>>
>>>> I have made no changes to gem5, the commit I am using is "
>>>> 2a98a994df296f818b05da90ba073d879562da04"
>>>>
>>>>
>>>> My question is:
>>>> Is it not possible to create a common checkpoint and then run the
>>>> benchmark using that checkpoint?
>>>> Are my steps incorrect to create or restore from the checkpoint?
>>>>
>>>>
>>>>
>>>>
>>>> Best regards,
>>>>
>>>> Abhishek
>>>>
>>> ___
>>>> gem5-users mailing list
>>>> gem5-users@gem5.org
>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>>
>>>
>>> --
>>> Pouya Fotouhi
>>> PhD Candidate
>>> Department of Electrical and Computer Engineering
>>> University of California, Davis
>>> ___
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>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>>
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Re: [gem5-users] Full System X86 restoring from checkpoint questions

[Abhishek Singh]

Hi Pouya and Jason,
Yes the binary is present.
My question is it necessary to run the binary after the checkpoint command
that is after “/sbin/m5 checkpoint”
And if yes why?

On Fri, Aug 30, 2019 at 12:30 PM Pouya Fotouhi  wrote:

> Hi Abhishek,
>
> Do you have your binary (hello_world) on your disk image? To be more
> precise, was the binary on the disk image when you took the checkpoint?
>
> Best,
>
> On Fri, Aug 30, 2019 at 8:26 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Everyone,
>>
>> I have created the checkpoint for booting up Linux image.
>> My command line is
>> """
>>
>> build/X86/gem5.opt
>> --outdir=/home/abs218/gem5_dir_local/gem5_bl_fs/common_checkpoint_chkpt
>> --stats-file=common_checkpoint_chkpt.simout
>> --dump-config=common_checkpoint_chkpt.ini --redirect-stderr
>> --stderr-file=common_checkpoint_chkpt.e configs/example/fs.py
>> --checkpoint-dir=/home/abs218/gem5_dir_local/gem5_bl_fs/common_checkpoint_chkpt
>> --disk-image=/home/abs218/gem5_dir_local/gem5_bl_fs/intel.img
>> --kernel=/home/abs218/new_fs/gem5/linux-4.8.13/vmlinux
>> --script=./common_checkpoint.rcS --caches --l2cache
>>
>>
>> """
>>
>> my common_checkpoint.rcS is
>>
>> """
>>
>> #!/bin/sh
>>
>> /sbin/m5 checkpoint
>>
>> echo "Done :D"
>>
>> /sbin/m5 exit
>>
>>
>> """
>>
>> I wanted to use this checkpoint and try to run a hello_world benchmark.
>> So I modify my common_checkpoint.rcS script to
>> """
>>
>> #!/bin/sh
>>
>> ./hello_world
>>
>> echo "Done :D"
>>
>> /sbin/m5 exit
>>
>> """
>> And my gem5 command line is
>> """
>> ./build/X86/gem5.opt
>> --outdir=/home/abs218/gem5_dir_local/gem5_bl_fs/common_checkpoint_chkpt
>> --stats-file=common_checkpoint_chkpt_restore.simout
>> --dump-config=common_checkpoint_chkpt_restore.ini configs/example/fs.py
>> --checkpoint-restore=1
>> --checkpoint-dir=/home/abs218/gem5_dir_local/gem5_bl_fs/common_checkpoint_chkpt
>> --restore-with-cpu=AtomicSimpleCPU --cpu-type=DerivO3CPU --caches --l2cache
>> --disk-image=/home/abs218/gem5_dir_local/gem5_bl_fs/intel.img
>> --kernel=/home/abs218/new_fs/gem5/linux-4.8.13/vmlinux
>> --script=./common_checkpoint.rcS
>> """
>> But my "system.pc.com_1.device" output after restoring  is
>> ""
>>
>> Done :D
>> ""
>> That is, it did not run the hello_world program!
>>
>> I have made no changes to gem5, the commit I am using is "
>> 2a98a994df296f818b05da90ba073d879562da04"
>>
>>
>> My question is:
>> Is it not possible to create a common checkpoint and then run the
>> benchmark using that checkpoint?
>> Are my steps incorrect to create or restore from the checkpoint?
>>
>>
>>
>>
>> Best regards,
>>
>> Abhishek
>>
> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>
>
> --
> Pouya Fotouhi
> PhD Candidate
> Department of Electrical and Computer Engineering
> University of California, Davis
> ___
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Re: [gem5-users] How to run SE on multicores to speedup simulation ?

[Abhishek Singh]

Hi yuan,
Gem5 is a single thread application. So there’s no way to speed up gem5
with increasing number of core.


On Sat, Aug 31, 2019 at 12:30 PM Yuan Kevin  wrote:

> Dear gem5 community members,
>
> I am playing the DRAM simulation with configs/dram/sweep.py on my 12 core
> CPU workstation.
>
> However I found gem5 is running on only one of the 12 cores.
>
> It there a way to run the simulation on multiple cores to speedup the
> process and how ?
>
> Best regards.
>
>
> Thanks,
>
>
> Kevin Yuan
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[gem5-users] How to run gdb or debug segmentation fault in Full System O3CPU in x86 isa

[Abhishek Singh]

Hello Everyone,

I am running the persistent benchmarks (tatp, vacation), which is a single
thread benchmark.
I can correctly run the benchmark on AtomicSimpleCPU and generate
checkpoint.
When I am trying to restore it with O3CPU, I can see "Segmentation Fault
(core dumped)" in "system.pc.com_1.device" file.
I want to know the reason why the benchmark could not run in O3CPU.
I am using gem5 commit "def0a4c6fdefd9458bc15ccf7c36efdd79204821". I am
using X86 ISA.
I do not make changes in gem5 source codes.
My restoring command line is
"""

./build/X86/gem5.opt
--outdir=/home/abs218/gem5_latest/gem5_bl_fs/tatp_pi_cgl_lazy_chkpt
--stats-file=tatp_pi_cgl_lazy_chkpt.simout
--dump-config=tatp_pi_cgl_lazy_chkpt.ini --redirect-stderr
--stderr-file=tatp_pi_cgl_lazy_chkpt.e configs/example/fs.py
--checkpoint-dir=/home/abs218/gem5_latest/gem5_bl_fs/tatp_pi_cgl_lazy_chkpt
--disk-image=/home/abs218/gem5_latest/gem5_bl_fs/intel.img
--kernel=/home/abs218/new_fs/gem5/linux-4.8.13/vmlinux
--script=./tatp_pi_cgl_lazy.rcS --caches --l2cache

"""
Is there any way, I can run gdb with the application and see the problem
with the application?

Best regards,

Abhishek
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Re: [gem5-users] How to run gdb or debug segmentation fault in Full System O3CPU in x86 isa

[Abhishek Singh]

Hello Ayaz and Everyone,

I would like to run gdb tool within the image while restoring from the
checkpoint in x86 O3CPU.
I get a "segmentation fault error " when I restore from the checkpoint.
The segmentation fault I get is in "system.pc.com_1.device" and simulation
exits normally.
I do not get any such error when I run on AtomicSimpleCPU or restore with
AtomicSimpleCPU.
I cannot use this method " http://www.gem5.org/Debugging_Simulated_Code;



Best regards,

Abhishek


On Sun, Sep 1, 2019 at 9:16 PM Ayaz Akram  wrote:

> Hi Abhishek,
>
> You can use gdb's remote debugger interface to debug simulated code in
> gem5. See details here: http://www.gem5.org/Debugging_Simulated_Code.
>
> Regards,
> -Ayaz
>
> On Sun, Sep 1, 2019 at 5:56 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Everyone,
>>
>> I am running the persistent benchmarks (tatp, vacation), which is a
>> single thread benchmark.
>> I can correctly run the benchmark on AtomicSimpleCPU and generate
>> checkpoint.
>> When I am trying to restore it with O3CPU, I can see "Segmentation Fault
>> (core dumped)" in "system.pc.com_1.device" file.
>> I want to know the reason why the benchmark could not run in O3CPU.
>> I am using gem5 commit "def0a4c6fdefd9458bc15ccf7c36efdd79204821". I am
>> using X86 ISA.
>> I do not make changes in gem5 source codes.
>> My restoring command line is
>> """
>>
>> ./build/X86/gem5.opt
>> --outdir=/home/abs218/gem5_latest/gem5_bl_fs/tatp_pi_cgl_lazy_chkpt
>> --stats-file=tatp_pi_cgl_lazy_chkpt.simout
>> --dump-config=tatp_pi_cgl_lazy_chkpt.ini --redirect-stderr
>> --stderr-file=tatp_pi_cgl_lazy_chkpt.e configs/example/fs.py
>> --checkpoint-dir=/home/abs218/gem5_latest/gem5_bl_fs/tatp_pi_cgl_lazy_chkpt
>> --disk-image=/home/abs218/gem5_latest/gem5_bl_fs/intel.img
>> --kernel=/home/abs218/new_fs/gem5/linux-4.8.13/vmlinux
>> --script=./tatp_pi_cgl_lazy.rcS --caches --l2cache
>>
>> """
>> Is there any way, I can run gdb with the application and see the problem
>> with the application?
>>
>> Best regards,
>>
>> Abhishek
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
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Re: [gem5-users] MemTraceProbe cannot be imported successfully

[Abhishek Singh]

Can you try older version of libptotoc like libprotoc 2.6.1?

On Thu, Jul 25, 2019 at 11:18 AM Rosen Lu  wrote:

> Hi,
>
> I set the environment as follow:
>
> export PATH=$PATH:/usr/local/protobuf/bin
> export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/usr/local/protobuf/lib
> export LIBRARY_PATH=$LIBRARY_PATH:/usr/local/protobuf/lib
>
> Best,
> Rosen
>
> Serhat Gesoglu  于2019年7月25日周四 上午9:43写道：
>
>> Hello,
>> Could you try locating the protoc bin and setting the environment PROTOC
>> to it?
>>
>> Serhat
>>
>> --
>> *From:* gem5-users [gem5-users-boun...@gem5.org] on behalf of Rosen Lu [
>> wisdom@gmail.com]
>> *Sent:* 25 July 2019 15:06
>> *To:* gem5 users mailing list
>> *Subject:* Re: [gem5-users] MemTraceProbe cannot be imported successfully
>>
>> Hello Serhat,
>>
>> Thank you for your reply. After I rebuilt gem5, the following error
>> message prompted:
>> ***
>> scons: Reading SConscript files ...
>> Package protobuf was not found in the pkg-config search path.
>> Perhaps you should add the directory containing `protobuf.pc'
>> to the PKG_CONFIG_PATH environment variable
>> No package 'protobuf' found
>> Warning: pkg-config could not get protobuf flags.
>> Checking for C header file Python.h... (cached) yes
>> Checking for C library pthread... (cached) yes
>> Checking for C library dl... (cached) yes
>> Checking for C library util... (cached) yes
>> Checking for C library m... (cached) yes
>> Checking for C library python2.7... (cached) yes
>> Checking for accept(0,0,0) in C++ library None... (cached) yes
>> Checking for zlibVersion() in C++ library z... (cached) yes
>> Checking for GOOGLE_PROTOBUF_VERIFY_VERSION in C++ library protobuf...
>> (cached) no
>> Warning: did not find protocol buffer library and/or headers.
>>Please install libprotobuf-dev for tracing support.
>> Checking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached)
>> yes
>> Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library
>> None... (cached) no
>> Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library rt...
>> (cached) yes
>> Checking for C library tcmalloc... (cached) no
>> Checking for C library tcmalloc_minimal... (cached) no
>> You can get a 12% performance improvement by installing tcmalloc
>> (libgoogle-perftools-dev package on Ubuntu or RedHat).
>> Checking for backtrace_symbols_fd((void*)0, 0, 0) in C library None...
>> (cached) no
>> Checking for backtrace_symbols_fd((void*)0, 0, 0) in C library
>> execinfo... (cached) no
>> No suitable back trace implementation found.
>> Checking for C header file fenv.h... (cached) yes
>> Checking for C header file png.h... (cached) no
>> Warning: Header file  not found.
>>  This host has no libpng library.
>>  Disabling support for PNG framebuffers.
>> Checking for C header file linux/kvm.h... (cached) yes
>> Checking for C header file linux/if_tun.h... (cached) yes
>> Checking size of struct kvm_xsave ... (cached) yes
>> Checking for member exclude_host in struct perf_event_attr...(cached) yes
>> Checking whether __i386__ is declared... (cached) no
>> Checking whether __x86_64__ is declared... (cached) yes
>> Building in /home/cc/gem5-prefetch-camat/build/X86
>> Using saved variables file
>> /home/cc/gem5-prefetch-camat/build/variables/X86
>> ImportError: No module named MemTraceProbe:
>>   File "/home/cc/gem5-prefetch-camat/SConstruct", line 1249:
>> SConscript('src/SConscript', variant_dir = variant_path, exports =
>> 'env')
>>   File "/usr/lib/python2.7/site-packages/SCons/Script/SConscript.py",
>> line 614:
>> return method(*args, **kw)
>>   File "/usr/lib/python2.7/site-packages/SCons/Script/SConscript.py",
>> line 551:
>> return _SConscript(self.fs, *files, **subst_kw)
>>   File "/usr/lib/python2.7/site-packages/SCons/Script/SConscript.py",
>> line 260:
>> exec _file_ in call_stack[-1].globals
>>   File "/home/cc/gem5-prefetch-camat/build/X86/SConscript", line 532:
>> exec('from m5.objects import %s' % modname)
>>   File "", line 1:
>> None
>>   File "/home/cc/gem5-prefetch-camat/build/X86/SConscript", line 512:
>> exec file(source.abspath, 'r') in mod.__dict__
>>   File "/home/cc/gem5-prefetch-camat/src/cpu/simple/AtomicSimpleCPU.py",
>> line 42:
>> from BaseSimpleCPU import BaseSimpleCPU
>>   File "/home/cc/gem5-prefetch-camat/build/X86/SConscript", line 512:
>> exec file(source.abspath, 'r') in mod.__dict__
>>   File "/home/cc/gem5-prefetch-camat/src/cpu/simple/BaseSimpleCPU.py",
>> line 31:
>> from BaseCPU import BaseCPU
>>   File "/home/cc/gem5-prefetch-camat/build/X86/SConscript", line 512:
>> exec file(source.abspath, 'r') in mod.__dict__
>>   File "/home/cc/gem5-prefetch-camat/src/cpu/BaseCPU.py", line 60:
>> from m5.objects.MemTraceProbe import *
>> ***
>>
>> I think this error was because of the absence of protobuf.  However, I
>> have installed protobuf,
>> ***
>> protoc --version
>> libprotoc 3.9.0
>> ***
>> So is this a version 

Re: [gem5-users] derivo3cpu issue

[Abhishek Singh]

Hi,
Where did you get the config file from?
Also can you run gdb and send us the backtrace?

On Fri, Nov 22, 2019 at 9:21 PM ABD ALRHMAN ABO ALKHEEL <
abdkeel...@hotmail.com> wrote:

> Global frequency set at 1 ticks per second
> warn: DRAM device capacity (8192 Mbytes) does not match the address range
> assigned (16384 Mbytes)
> 0: system.remote_gdb: listening for remote gdb on port 7000
> info: Entering event queue @ 0.  Starting simulation...
>  REAL SIMULATION 
> info: Increasing stack size by one page.
> warn: ignoring syscall access(...)
> warn: MOVNTDQ: Ignoring non-temporal hint, modeling as cacheable!
> info: Increasing stack size by one page.
> info: Increasing stack size by one page.
> info: Increasing stack size by one page.
> info: Increasing stack size by one page.
> info: Increasing stack size by one page.
> gem5 has encountered a segmentation fault!
>
> --- BEGIN LIBC BACKTRACE ---
>
> /home/abdkhail/aa/gem5/build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x55cda9d47dac]
> /home/abdkhail/aa/gem5/build/X86/gem5.opt(+0x584e7f)[0x55cda9d59e7f]
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x12890)[0x7f77bb174890]
> /lib/x86_64-linux-gnu/libgcc_s.so.1(_Unwind_Resume+0xcf)[0x7f77b9b137df]
>
> /home/abdkhail/aa/gem5/build/X86/gem5.opt(_ZN6X86ISA7Decoder10decodeInstENS_11ExtMachInstE+0x4e609)[0x55cda9ee8659]
>
> /home/abdkhail/aa/gem5/build/X86/gem5.opt(_ZN6X86ISA7Decoder6decodeENS_11ExtMachInstEm+0x244)[0x55cda9e63db4]
> Command: /home/abdkhail/aa/gem5/build/X86/gem5.opt
> --outdir=/home/abdkhail/aa/gem5/o1
> /home/abdkhail/aa/gem5/configs/example/spec06_config.py -I 10
> --benchmark=povray --benchmark_stdout=/home/abdkhail/aa/gem5/o1/povray.out
> --benchmark_stderr=/home/abdkhail/aa/gem5/o1/povray.err
> --cpu-type=DerivO3CPU --caches
> --
> *From:* gem5-users  on behalf of Abhishek
> Singh 
> *Sent:* Friday, November 22, 2019 11:11:38 PM
> *To:* gem5 users mailing list 
> *Cc:* gem5-users 
> *Subject:* Re: [gem5-users] derivo3cpu issue
>
> Hey,
> What is the error and what is the command line?
> Can you run gdb and paste the back trace?
> Did you made any changes to baseline gem5?
>
> On Fri, Nov 22, 2019 at 5:54 PM ABD ALRHMAN ABO ALKHEEL <
> abdkeel...@hotmail.com> wrote:
>
> Hello everyone, I am running the benchmark on gem5 and I got error when I
> use derivo3cpu . I have to use it so how I can fix the issue?
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Re: [gem5-users] derivo3cpu issue

[Abhishek Singh]

Hey,
What is the error and what is the command line?
Can you run gdb and paste the back trace?
Did you made any changes to baseline gem5?

On Fri, Nov 22, 2019 at 5:54 PM ABD ALRHMAN ABO ALKHEEL <
abdkeel...@hotmail.com> wrote:

> Hello everyone, I am running the benchmark on gem5 and I got error when I
> use derivo3cpu . I have to use it so how I can fix the issue?
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Re: [gem5-users] Gem5 Cache

[Abhishek Singh]

Hi,
See the options for se.py or fs.py depending on what mode you are using.



On Wed, Dec 11, 2019 at 12:07 AM DURAIRAJ J <2016506...@annauniv.edu.in>
wrote:

> Thanks for the reply.
> Is there any way to specify it by using simulation command
>
> --
> *From: *"Abhishek Singh" 
> *To: *"gem5-users" 
> *Sent: *Wednesday, 11 December, 2019 10:03:25
> *Subject: *Re: [gem5-users] Gem5 Cache
>
> Check config/common/Caches.py
>
> On Tue, Dec 10, 2019 at 11:32 PM DURAIRAJ J <2016506...@annauniv.edu.in>
> wrote:
>
>> Hello everyone,
>> I am a newbie in gem5, so someone cloud helps me with how to specify the
>> values for the Icache and Dcache parameter?
>>
>> ___
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>
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Re: [gem5-users] What is the default coherence mechanism in gem5 for multicore systems?

[Abhishek Singh]

Hi,
The default is MI protocol in classic cache model, there are various
protocols which you can find in build_opts directory.
Also, you can find the build info by using —build-info flag.
For example ./build/X86/gem5.opt —build-info

On Wed, Dec 11, 2019 at 10:11 AM Francisco Carlos 
wrote:

> Hi all,
>
> I am currently running simulation in a multicore processor. I connect the
> memory system as follow:
>
> for i in range(np):
> system.cpu[i].icache = L1_ICache()
> system.cpu[i].dcache = L1_DCache()
> system.cpu[i].icache.connectCPU(system.cpu[i])
> system.cpu[i].dcache.connectCPU(system.cpu[i])
>
> system.l2cache = L2Cache()
> system.l2bus = L2XBar()
>
> #np means number of processor and it is a parameter
> for i in range(np):
> system.cpu[i].icache.connectBus(system.l2bus)
> system.cpu[i].dcache.connectBus(system.l2bus)
> system.l2cache.connectCPUSideBus(system.l2bus)
> system.l2cache.connectMemSideBus(system.membus)
> In summary, to each core I have private Icache and Dcache which are
> connected to an L2 shared cache.
>
> So, my question is: how is the coherence guaranteed in the system, since I
> do not provide this information in my configuration file? Is there a
> default coherency used in the gem5? If so, which is it?
>
> Thanks in advance.
>
>
> --
> Francisco Carlos Silva Junior
> Ph.D student at University of Brasilia
>
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Re: [gem5-users] What is the default coherence mechanism in gem5 for multicore systems?

[Abhishek Singh]

Thank you for the clarification.

On Wed, Dec 11, 2019 at 11:40 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:

> The PROTOCOL env var (available in build_opts) is used in Ruby only.
> For the classic memory system, MOESI is used.
>
> Giacomo
> --
> *From:* gem5-users  on behalf of Abhishek
> Singh 
> *Sent:* 11 December 2019 16:32
> *To:* gem5 users mailing list 
> *Subject:* Re: [gem5-users] What is the default coherence mechanism in
> gem5 for multicore systems?
>
> Hi,
> The default is MI protocol in classic cache model, there are various
> protocols which you can find in build_opts directory.
> Also, you can find the build info by using —build-info flag.
> For example ./build/X86/gem5.opt —build-info
>
> On Wed, Dec 11, 2019 at 10:11 AM Francisco Carlos <
> juninho.u...@hotmail.com> wrote:
>
> Hi all,
>
> I am currently running simulation in a multicore processor. I connect the
> memory system as follow:
>
> for i in range(np):
> system.cpu[i].icache = L1_ICache()
> system.cpu[i].dcache = L1_DCache()
> system.cpu[i].icache.connectCPU(system.cpu[i])
> system.cpu[i].dcache.connectCPU(system.cpu[i])
>
> system.l2cache = L2Cache()
> system.l2bus = L2XBar()
>
> #np means number of processor and it is a parameter
> for i in range(np):
> system.cpu[i].icache.connectBus(system.l2bus)
> system.cpu[i].dcache.connectBus(system.l2bus)
> system.l2cache.connectCPUSideBus(system.l2bus)
> system.l2cache.connectMemSideBus(system.membus)
> In summary, to each core I have private Icache and Dcache which are
> connected to an L2 shared cache.
>
> So, my question is: how is the coherence guaranteed in the system, since I
> do not provide this information in my configuration file? Is there a
> default coherency used in the gem5? If so, which is it?
>
> Thanks in advance.
>
>
> --
> Francisco Carlos Silva Junior
> Ph.D student at University of Brasilia
>
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Re: [gem5-users] Disable pre-fetching in l2 cache

[Abhishek Singh]

Hi,
Prefetching will impact the replacement in a way it can bring non demand
dead blocks which will not be referenced in the application and force evict
a demand block.
You can disable prefetchers by editing src/configs/common/Caches.py and
setting the parameter “prefetcher” to NULL just for L2 cache.



On Tue, Dec 3, 2019 at 5:15 PM Charitha Saumya 
wrote:

> Hi,
>
> 1. Can pre-fetching impact the performance of cache replacement policies
> (e.g. LIP vs LRU)?
> 2. If so How can I completely disable prefetching in l2 cache?
>
> Thanks
> Charitha
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Re: [gem5-users] [gem5-dev] gem5 stable release proposal [PLEASE VOTE!]

[Abhishek Singh]

Hello Jason,
Thanks for such a nice and detailed explanation.
My votes are as follows:


*I think master should be development*


*I think gem5 should be released once per year*


Best regards,

Abhishek


On Mon, Dec 16, 2019 at 2:50 PM Jason Lowe-Power 
wrote:

> Hi all,
>
> As many of you have seen on gem5-dev, we are going to be adding a
> "stable" version of gem5. Below is the current proposal. There are a
> couple of points below where there has not been general consensus
> reached. We would appreciate feedback *from everyone in the community*
> on the points where a decision hasn't been made below. gem5 is a
> community-driven project, and we need feedback to make sure we're
> making community-focused decisions.
>
> We will be introducing a new "stable" branch type to gem5. We are
> doing this for the following reasons:
> - Provide a way for developers to communicate major changes to the
> code. We will be providing detailed release notes for each stable
> release.
> - Increase our test coverage. At each stable release, we will test a
> large number of "common" benchmarks and configurations and publicize
> the current state of gem5.
> - Provide a way for researchers to communicate to the rest of the
> community information about their simulation infrastructure (e.g., in
> a paper you can say which version of gem5 you used).
>
> On the stable version of gem5, we will provide bugfixes  until the
> next release, but we will not make any API changes or add new
> features.
>
> We would like your feedback on the following two questions:
>
> **Which branch should be default?**
>
> We can either have the master branch in git be the "stable" or the
> "development" branch. If master is the stable branch, then it's easier
> for users to get the most recent stable branch. If master is the
> development branch, it's more familiar and easier for most developers.
> Either way, we will be updating all of the documentation to make it
> clear.
>
> Please let us know which you prefer by replying "I think master should
> be stable" or "I think master should be development".
>
> **How often should we create a new gem5 release?**
>
> We can have a gem5 release once per year (likely in April) or three
> times per year (April, August, and December). Once per year means that
> if you use the stable branch you will get updates less frequently.
> Three times per year will mean there are more releases to choose from
> (but a newer release should always be better). On the development
> side, I don't think one will be more work than the other. Once per
> year means more backporting, and three times per year means more
> testing and time spent on releases.
>
> Please let us know which you prefer by replying "I think gem5 should
> be released once per year" or "I think gem5 should be released three
> times per year."
>
>
>
>
> A couple of notes to everyone who's been following the discussion on
> the gem5-dev mailing list:
> - We have dropped the proposal for major vs minor releases. Note that
> there was some pushback on having only major releases when this was
> proposed on the gem5 roadmap, but it sounded like the consensus was to
> drop minor releases for now.
> - We will still allow feature branches *in rare circumstances*. This
> will be by request only (send mail to gem5-dev if you would like to
> discuss adding a new branch), and the goal will be integration within
> a few months. All code review will still happen in the open on gerrit.
> The benefits will be
> 1) rebases won't be required as you can just make changes to the head
> of the branch
> 2) many features take more than a few months to implement, so if it's
> not ready by a release it can be pushed to the next
> 3) large changes won't be hidden in AMD or Arm-specific repositories
> and *anyone* will be able to request a branch.
>
> Thanks everyone for the discussions so far! It would be most useful to
> hear back by the end of the week. However, I don't expect any concrete
> actions will be taken until after the holidays.
>
> Cheers,
> Jason
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Re: [gem5-users] Assertion during full system emulation with checkpoint restore and standar switch option

[Abhishek Singh]

Try January 2018 commit

On Fri, Oct 18, 2019 at 2:10 PM Michail Mavropoulos <
mavropo...@ceid.upatras.gr> wrote:

> Hello all,
>
> I am using gem5 revision commit
> 4c38c7c02aca9922d7f30f2f399bbe94c034eb59.
>
> I try to run a full system emulation, after restoring from a checkpoint
> and using standard-switch option, in order to run over DerivO3CPU cpu
> model.
>
> I use the following command:
> ./build/X86/gem5.opt -d /tmp/gem5_test --stats-file=test.csv
> configs/example/fs.py --checkpoint-dir=/tmp/cpts/benchamark
> --checkpoint-restore=1 --caches --l2cache --maxinsts=32
> --standard-switch=30
> --kernel=/home/gem5/binaries/x86_64-vmlinux-2.6.22.9
> --disk-image=/home/gem5/disks/ubuntu-14.04.img ;
>
> The result is that, there are some cases (different checkpoints/
> benchmarks) where I get the following assertion:
>   build/X86/mem/packet.hh:1094: T* Packet::getPtr() [with T = unsigned
> char]: Assertion `flags.isSet(STATIC_DATA|DYNAMIC_DATA)' failed.
>
> Is this a known issue?
> Should I modify the command above?
>
> Thank you
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[gem5-users] Correction: TLB timing model in x86 SE O3CPU

[Abhishek Singh]

Hello Everyone and Gabe,

Does x86 gem5 SE mode using O3CPU considers timing delays of TLB Hit and
TLB miss?
If yes, which file has it?

I could not find any timing parameter in src/arch/tlb.cc in translate
timing function

Is that timing delay overlapped with the cache access timing delay?

Also, how is the tlb function invoked, is it invoked through iew files or
lsq files for data tlb?
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[gem5-users] TLB timing model in x86 SE Mode

[Abhishek Singh]

Hello Everyone,

Does x86 gem5 SE mode considers timing delays of TLB Hit and TLB miss?
If yes, which file has it?

I could not find any timing parameter in src/arch/tlb.cc in translate
timing function

Is that timing delay overlapped with the cache access timing delay?

Also, how is the tlb function invoked, is it invoked through iew files or
lsq files for data tlb?
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Re: [gem5-users] Adding latencies in cache accesses

[Abhishek Singh]

Hi Vector,
You need to search for fill latency in src/mem/cache/base.cc and response
latency in src/mem/cache/cache.cc in serviceMSHR function call.

On Wed, Oct 16, 2019 at 5:38 PM Victor Kariofillis 
wrote:

> Hi Daniel,
>
> First of all thanks for answering. I have some more questions. In my case,
> latencies are added every time data is written to the cache. So for
> example, theoretically latency should be added in handleFill() as well. I
> see that handleFill() doesn't have any latency computation in it. It is
> also absent from recvTimingResp() that calls it. Is this because it is off
> the critical path?
>
> Also, it there any way to multiply a Cycles type variable? What I want to
> do is indicate that a because some things happen serially, a particular
> latency happens n times.
>
> Thanks,
> Victor
>
> On Sun, 13 Oct 2019 at 22:40, Victor Kariofillis 
> wrote:
>
>> Hi,
>>
>> I am interested in adding additional latencies during a cache access. I
>> have implemented some extra functionality that happens in the cache and I
>> am wondering about how to model the extra time it will take for that to
>> happen.
>>
>> Where would I add the extra latency? For example, inside the access()
>> function there is this line of code:
>>
>> // Calculate access latency on top of when the packet arrives.
>> This
>> // takes into account the bus delay.
>> lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency);
>>
>> Right below that, there is a "return false;" line. How is that latency
>> being used? Also, how can I make sure whether the execution stalls until
>> something else has finished or things that can happen concurrently?
>>
>> Thank you,
>> Victor
>>
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Re: [gem5-users] Memory Command

[Abhishek Singh]

Hi yuan,

There is no document detailing those commands except few comments in
packet.hh file.
Whatever commands you are confused about please reply to this email thread,
so that everyone whoever has any knowledge will start sharing and then we
can combine it and put it as a document.

On Fri, Oct 11, 2019 at 10:59 AM yuan  wrote:

> Hi, All
>
>
>
> I am trying to read through the code in src/mem/, but I find that there
> are a lot memory command defined in packet.hh. Are there any docs for these
> memory commands? I am confused with some of these memory commands.
>
>
>
> Best,
>
>
>
> Yuan
>
>
>
> Sent from Mail  for
> Windows 10
>
>
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Re: [gem5-users] Fw: [gem5]: SHA2 and SHA3 on gem5

[Abhishek Singh]

Hi,
Can you explain in detail what is SHA2 and SHA3, any links?

On Thu, Oct 17, 2019 at 3:09 PM ABD ALRHMAN ABO ALKHEEL <
abdkeel...@hotmail.com> wrote:

> Hello everyone,
>
> I wanna run the sha3 and sha2 on gem5. I need your help.
>
> Best Regards
> --
> *From:* ABD ALRHMAN ABO ALKHEEL 
> *Sent:* Thursday, October 17, 2019 3:00:35 AM
> *To:* gem5 users mailing list 
> *Subject:* [gem5]: SHA2 and SHA3 on gem5
>
> Hello everyone,
>
> I wanna run the sha3 and sha2 on gem5. I need your help.
>
> Best Regards
>
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Re: [gem5-users] Difference cpu clock and sys clock

[Abhishek Singh]

I always set it same
System clock is for peripheral
Most times we focus more on cpu clock

On Mon, Nov 25, 2019 at 3:12 PM Nikos Giakoumoglou 
wrote:

> What is the difference in cpu and sys clock?
> Can’t figure it out from any file
>
> NG
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Re: [gem5-users] X86 CLFLUSH Flush Cache Line Instruction

[Abhishek Singh]

Hi ,

I do not know about the secure bit implementation, if you want to implement
something similar, what I would do is to follow what ARM does and try to
replicate it in x86

On Wed, Nov 27, 2019 at 8:49 AM Muralidharan K 
wrote:

> Abhishek,
>
> In a similar query on secure bit/flag, Jason Lowe-Power had mentioned that
> the same (secure bit) is used only for ARM ISA in GEM5 and not for X86
> ISA.. Am I missing something here?
>
> Bala
>
> On Mon, Nov 25, 2019 at 10:12 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hey,
>> You can do that, just go to the decoder code and make the secure flag
>> high
>>
>> The code should be located at src/arch/x86/isa/
>>
>> On Mon, Nov 25, 2019 at 11:20 AM Muralidharan K <
>> kmconsultant...@gmail.com> wrote:
>>
>>> Hello,
>>>
>>> I am aware that the above instruction has been implemented in the latest
>>> build of gem5, but wanted to know if we can make changes in Gem5 to only
>>> allow such instructions to run only in secure processes and with secure
>>> kernel privileges and not allowed to run in user application mode.
>>>
>>> Can we implement such changes in gem5, any ideas/suggestions for
>>> implementing it would be welcome..
>>>
>>> Thanks in advance
>>>
>>> Bala
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Re: [gem5-users] Difference cpu clock and sys clock

[Abhishek Singh]

Hi Javed,

To do that, add these flags in your command line

—cpu-clock=‘xGHz’ —sys-clock=‘yGHz’

On Wed, Nov 27, 2019 at 2:16 AM Javed Osmany 
wrote:

> Hello
>
>
>
> If one wants to set the CPU clock to be different to the system clock, how
> does one go about doing this?
>
>
>
> I could not find the mechanism to set the [cpu, system] clocks separately.
>
>
>
> Regards
>
>
>
> JO
>
>
>
>
>
> *From:* gem5-users [mailto:gem5-users-boun...@gem5.org] *On Behalf Of 
> *Abhishek
> Singh
> *Sent:* 27 November 2019 00:45
> *To:* gem5 users mailing list 
> *Subject:* Re: [gem5-users] Difference cpu clock and sys clock
>
>
>
> I always set it same
>
> System clock is for peripheral
>
> Most times we focus more on cpu clock
>
>
>
> On Mon, Nov 25, 2019 at 3:12 PM Nikos Giakoumoglou 
> wrote:
>
> What is the difference in cpu and sys clock?
> Can’t figure it out from any file
>
> NG
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Re: [gem5-users] Stat of type Formula getting value from function

[Abhishek Singh]

Hi Varun,

Will this stat will be calculated on every tick?

On Fri, Nov 29, 2019 at 7:01 PM Victor Kariofillis 
wrote:

> Hi,
>
> I have created a Stat of type Formula. Since the formula is complicated,
> instead of having it in the regStats file, I want to call another function
> that returns the proper value. The code would be something like this.
>
> zeroPercentage.flags(total);
> zeroPercentage = calcZeroPercentage();
>
> The calcZeroPercentage is a typical function in the file. The numbers that
> I'm crunching to get the value that I want are not stats. Would something
> like this be possible? In the gem5 documentation statistics page, it states
> that if the variables are not stats they should be qualified with constant.
>
> "If bar or num are regular variables, then they must be qualified with
> constant(bar)."
>
> Is this true for this case as well?
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Re: [gem5-users] Running spec2000 benchmarks on se.py

[Abhishek Singh]

There’s is no standard script provided by gem5
But u can search online or make your own

On Wed, Nov 27, 2019 at 1:48 PM Charitha Saumya 
wrote:

> Hi,
>
> How can I run the SPEC 2000 benchmarks with latest gem5? I can not find
> any config script to do this.
> I have SPEC 2000 binaries in alpha ISA format
>
> Thanks,
> Charitha
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Re: [gem5-users] How to suspend a packet in cache

[Abhishek Singh]

Hi Majid,

One way is the schedule the response of packet 1 to a later tick x( current
tick + 1), when the tick x is the system time, you have some sort of a flag
to check whether the packet 2 was serviced by L2 cache or not.
If no packet 2 had arrived in that time frame, you again delay the packet 1
response to y tick (y tick = current tick + n{number of ticks you want to
delay, I would suggest it to be 1})



On Mon, Dec 2, 2019 at 5:35 PM Majid Jalili  wrote:

> Hi,
> What is the best way to suspend a packet  in the cache. Let's say for a
> read access to L2, I have to suspend the request until another
> request comes in, although the main request might be a hit in L2.
>
> One solution might be checking the secondary request in
>  inpuSidePort::recvTimingReq(PacketPtr pkt)
> and then pushing back the main request to higher level, if the secondary
> is missing. But I want to keep the main packet in L2. Do you have any idea?
> Majid
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Re: [gem5-users] X86 CLFLUSH Flush Cache Line Instruction

[Abhishek Singh]

Hey,
You can do that, just go to the decoder code and make the secure flag high

The code should be located at src/arch/x86/isa/

On Mon, Nov 25, 2019 at 11:20 AM Muralidharan K 
wrote:

> Hello,
>
> I am aware that the above instruction has been implemented in the latest
> build of gem5, but wanted to know if we can make changes in Gem5 to only
> allow such instructions to run only in secure processes and with secure
> kernel privileges and not allowed to run in user application mode.
>
> Can we implement such changes in gem5, any ideas/suggestions for
> implementing it would be welcome..
>
> Thanks in advance
>
> Bala
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Re: [gem5-users] Warm up instructions in gem5

[Abhishek Singh]

If -s flag means fast forward then it’s correct.
Check the correct flags using ./build/X86/gem5.opt config/example/se.py -h

On Mon, Nov 25, 2019 at 9:46 PM Charitha Saumya 
wrote:

> Hi,
>
> I want to run my x86 binary for 300M  instructions from which 100M will be
> for warming up the caches. I also want to use DerivO3CPU model for my
> simulation. What is the correct way to do this? And what determines which
> CPU model will be used for warmup and non-warmup portions? For example
> AtomicSimple for warmup and DerivO3 for non-warmup cycles?
>
> Currently I am using ,
> ./build/X86/gem5.opt configs/example/se.py \
> --cmd=./tests/test-progs/simple/simple32 \
> --cpu-type=DerivO3CPU \
> --caches --l2cache \
> --l2_size='256kB' \
> --l1d_size='16kB' \
> --l1i_size='16kB' \
> -s 1 \
> -I 3
>
> Can someone confirm what I did was correct?
>
> Thanks,
> Charitha
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Re: [gem5-users] Warm up instructions in gem5

[Abhishek Singh]

Is there any flag called “fast forward”?

On Mon, Nov 25, 2019 at 9:53 PM Charitha Saumya 
wrote:

> No. -s means
>   -s STANDARD_SWITCH, --standard-switch=STANDARD_SWITCH
> switch from timing to Detailed CPU after warmup
> period
> of 
> But I am still not convinces all these flags are functional. Can someone
> confirm gem5 supports this flag? and what CPU models are used before and
> after switch?
>
> Thanks
>
>
>
> On Mon, Nov 25, 2019 at 9:50 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> If -s flag means fast forward then it’s correct.
>> Check the correct flags using ./build/X86/gem5.opt config/example/se.py -h
>>
>> On Mon, Nov 25, 2019 at 9:46 PM Charitha Saumya 
>> wrote:
>>
>>> Hi,
>>>
>>> I want to run my x86 binary for 300M  instructions from which 100M will
>>> be for warming up the caches. I also want to use DerivO3CPU model for my
>>> simulation. What is the correct way to do this? And what determines which
>>> CPU model will be used for warmup and non-warmup portions? For example
>>> AtomicSimple for warmup and DerivO3 for non-warmup cycles?
>>>
>>> Currently I am using ,
>>> ./build/X86/gem5.opt configs/example/se.py \
>>> --cmd=./tests/test-progs/simple/simple32 \
>>> --cpu-type=DerivO3CPU \
>>> --caches --l2cache \
>>> --l2_size='256kB' \
>>> --l1d_size='16kB' \
>>> --l1i_size='16kB' \
>>> -s 1 \
>>> -I 3
>>>
>>> Can someone confirm what I did was correct?
>>>
>>> Thanks,
>>> Charitha
>>> ___
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>>> gem5-users@gem5.org
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Re: [gem5-users] Warm up instructions in gem5

[Abhishek Singh]

Yes, just use that, flag is designed to warmup or to bypass the booting
process.

On Mon, Nov 25, 2019 at 9:58 PM Charitha Saumya 
wrote:

>   -F FAST_FORWARD, --fast-forward=FAST_FORWARD
> Number of instructions to fast forward before
> switching
>
> I am not sure fast forward can help me here.
>
>
>
> On Mon, Nov 25, 2019 at 9:55 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>>
>> Is there any flag called “fast forward”?
>>
>> On Mon, Nov 25, 2019 at 9:53 PM Charitha Saumya 
>> wrote:
>>
>>> No. -s means
>>>   -s STANDARD_SWITCH, --standard-switch=STANDARD_SWITCH
>>> switch from timing to Detailed CPU after warmup
>>> period
>>> of 
>>> But I am still not convinces all these flags are functional. Can someone
>>> confirm gem5 supports this flag? and what CPU models are used before and
>>> after switch?
>>>
>>> Thanks
>>>
>>>
>>>
>>> On Mon, Nov 25, 2019 at 9:50 PM Abhishek Singh <
>>> abhishek.singh199...@gmail.com> wrote:
>>>
>>>> If -s flag means fast forward then it’s correct.
>>>> Check the correct flags using ./build/X86/gem5.opt config/example/se.py
>>>> -h
>>>>
>>>> On Mon, Nov 25, 2019 at 9:46 PM Charitha Saumya <
>>>> saumyachari...@gmail.com> wrote:
>>>>
>>>>> Hi,
>>>>>
>>>>> I want to run my x86 binary for 300M  instructions from which 100M
>>>>> will be for warming up the caches. I also want to use DerivO3CPU model for
>>>>> my simulation. What is the correct way to do this? And what determines
>>>>> which CPU model will be used for warmup and non-warmup portions? For
>>>>> example AtomicSimple for warmup and DerivO3 for non-warmup cycles?
>>>>>
>>>>> Currently I am using ,
>>>>> ./build/X86/gem5.opt configs/example/se.py \
>>>>> --cmd=./tests/test-progs/simple/simple32 \
>>>>> --cpu-type=DerivO3CPU \
>>>>> --caches --l2cache \
>>>>> --l2_size='256kB' \
>>>>> --l1d_size='16kB' \
>>>>> --l1i_size='16kB' \
>>>>> -s 1 \
>>>>> -I 3
>>>>>
>>>>> Can someone confirm what I did was correct?
>>>>>
>>>>> Thanks,
>>>>> Charitha
>>>>> ___
>>>>> gem5-users mailing list
>>>>> gem5-users@gem5.org
>>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>>
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Re: [gem5-users] [gem5-dev] Announcing the beta of gem5's new website

[Abhishek Singh]

Hi Jason,
Thanks for sharing the website. And a lot of thanks to all those who made
this possible.
I had one question:

Is your tutorial updated to new function call names?for example to
implement new cache replacement policy, your tutorial still use old format
of defining function calls and its implementation in the
“src/mem/cache/tags/“ folder only, so is it still valid?



On Tue, Dec 17, 2019 at 8:15 PM Jason Lowe-Power 
wrote:

> Hi all,
>
> I'm excited to announce that we have a beta version of a re-designed
> website at new.gem5.org! The old wiki has needed a refresh for a few
> years,
> and we’re excited to finally have something to share with the community! We
> hope the new site has better usability and makes it easier to find
> information about gem5 and how to use it. If you have any questions or
> comments, don’t hesitate to reach out by replying to this email.
>
> We will leave this website at new.gem5.org for the next few weeks. Please
> let us know if there’s any blocking issues before we turn off the old wiki
> pages. Before fully transitioning, we will download a static copy of the
> entire old website (including the old code reviews) and move this to
> old.gem5.org for archival purposes (and in case we missed anything!).
>
> I'd like to thank all of those that have contributed so far. Specifically:
> Jingwen Low who designed the site
> Ali Saidi who kicked this off by converting the wiki to markdown almost two
> years ago
> Bobby Bruce who has put it a ton of time moving documentation
> And Jared Barosci, Hoa Nguyen, Krithiga Murugavel, Ayaz Akram, Trivikram
> Reddy, Marjan Fariborz, Mahyar Samani, Julian Toya Angeles, and Muhammet
> Soytürk who have helped move documentation from the old wiki to the new
> site.
> See https://github.com/gem5/new-website/graphs/contributors for details
>
> Details on the current status of the migration can be found on Jira (
> https://gem5.atlassian.net/browse/GEM5-110). We also have a specific issue
> for migrating the old documentation to the new site (
> https://gem5.atlassian.net/browse/GEM5-115). We’ve already moved most of
> the documentation, but there are still a few pages that we could use your
> help with!
>
> There will be some rough edges as we transition. Some links may be broken,
> and it’s possible we missed pages that should be migrated. If you find any
> issues, please let us know via the mailing list or by opening an issue on
> Jira.
>
> The website is currently hosted on GitHub pages. If you’d like to
> contribute, feel free to create a pull request on the source repository (
> https://github.com/gem5/new-website).
>
> Cheers,
> Jason
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Re: [gem5-users] ask for help about simulate with noncherentcahe

[Abhishek Singh]

Hi yuan,
In order to that, you need to call non-coherent cache
instead of cache in config/common/Caches.py file.
>From my experience I am able to use LLC as non coherent cache.
Please note this is how I used in classic cache model.

On Wed, Dec 18, 2019 at 11:54 AM 616653241 <616653...@qq.com> wrote:

> hi, everyone,
> can anybody tell me that how does gem5 O3 CPU simulate with
> noncoherentcache?
> yours
> wuhua
>
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Re: [gem5-users] Multiprogrammed simulation in x86 SE in O3CPU is broken

[Abhishek Singh]

Hi,
I will try my best to get the fix and share with the community. Also, if
you guys need help in testing the commit when submitted to review, please
let the community know. So however is interested can run tests and post the
result on online which is viewable by the maintainer and when important
features like multi core/multithreaded/multi programmed simulations and
others more have problem the developer can fix it so that previous
developers commit are not nullified
In this particular scenario someone did develop the environment for multi
core/multi threaded/multi programmed and now his/her effort needs to be
redone because we as community as whole did not pay attention when a commit
is submitted.
Currently in my free time I have personally started testing all the merged
commit in git review and test atleast the applications which is there in
gem5 directory.
And I have already submitted a Jira ticket. And in the mailing list I did
mention which gem5 commit is still supporting multi programmed simulations.
I will try to fix the problem and submit

On Thu, Feb 13, 2020 at 9:12 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:

> Hi Abhishek,
>
> Let me first thank you for finding and reporting the problem.
> Since you are asking
>
>
> *"please also inform all the developers to not push commit if their commit
> disturbs the dependencies then try to fix them and after everything is
> fixed then only merge to public gem5!" *
>
> I'd like to take the opportunity to explain which is the gem5 contribution
> workflow.
>
> Every time we post a patch for review, before it gets merged we
> automatically run a set of tests to verify the patch isn't breaking anything
> .
> If one (or more) of the tests fails, it won't be possible to merge the
> patch.
> Please have a look at
>
> https://github.com/gem5/gem5/blob/master/TESTING.md
>
> to have an idea on how this works.
>
> So why things break?
>
> Gem5 has a lot of features that could be tested (SE mode, FS mode, Ruby
> mem, Classic mem, AtomicCPU, TimingCPU, MinorCPU, O3CPU, Checkpointing,
> FastForwarding, SMT, SMP ... just to mention few)
>
> We try to cover the most significant ones but the combination of all this
> parameters makes it IMPOSSIBLE to test EVERYTHING.
> What we can do though is to prioritize some tests over some others. Or, if
> the test is fairly simple, we can consider adding it to the regression list.
>
> If you find that a feature is broken, you can use JIRA (
> https://gem5.atlassian.net/jira/your-work) to raise a ticket.
> We try to address the problems in a reasonable amount of time. It usually
> helps if, rather than saying "things are broken", we actually get a link to
> the commit which breaks the feature you are interested on (you can easilly
> bisect until you find the culprit).
>
> This will make it very likely for the bug to get a quick fix; or, by being
> an open source project, we would be very happy to receive a contribution
> fix from you if you feel like handling it yourself. I would be happy to
> provide all the support needed so it is up to you.
>
> Once the issue has been solved we can discuss to add an SMT test to the
> list so that we are sure things won't break again.
>
> Kind Regards
>
> Giacomo
>
> <https://github.com/gem5/gem5/blob/master/TESTING.md>
> gem5/TESTING.md at master · gem5/gem5 · GitHub
> <https://github.com/gem5/gem5/blob/master/TESTING.md>
> With this method, you can only run a single suite at a time. If you want
> to run more than one uid, you must call ./main.py multiple times..
> Currently, you must specify --skip-build if you want to run a single suite
> or run in batch mode. Otherwise, you will build gem5 for all architectures.
> github.com
>
>
>
>
>
>
> --
> *From:* gem5-users  on behalf of Abhishek
> Singh 
> *Sent:* 11 February 2020 19:34
> *To:* gem5 users mailing list 
> *Subject:* [gem5-users] Multiprogrammed simulation in x86 SE in O3CPU is
> broken
>
> Hello Everyone,
>
> The latest commit *135595a* is unable to support multi-core
> (multi-programmed) simulation on x86 O3CPU. I am pasting the terminal
> output showing a simple hello world program. The older commits of gem5 do
> support such multi-core (multi-programmed) simulation.
> Please note if we do not use SMT and use the number of CPUs as 2 for 2
> core simulation, the simulation reaches a point and goes in a never-ending
> loop.
>
> These problems are due to cause of recent commits, *please also inform
> all the developers *to not push commit if their commit disturbs the
> dependencies then try to fix them and after everything is fixed then only
> merge to public gem5!
>
> *Using SMT:*
&g

Re: [gem5-users] MultiProgrammed Workload X86 O3CPU error using SMT

[Abhishek Singh]

With that said
For x86 O3CPU, the multi program workload simulation is also broken.
So basically one can not multi core simulation using x86 O3CPU with and
without SMT.

Also, to all developers who push commit to gem5, please do thorough testing
as both of this support was working in older commits!

On Mon, Feb 10, 2020 at 3:59 PM Kevin Loughlin  wrote:

> Hi all,
>
> I believe there is indeed at least one bug in O3 CPU implementation when
> using SMT in SE mode. Namely, the rename mapping for the zero register on
> additional threads fails assert(prev_reg->isZeroReg()) in rename() in
> /src/cpu/o3/rename_map.cc. This is because the processor logic does not
> consider the mapping of the zero register for additional threads.
>
> There are two ways to solve this. We could (a) change the isZeroReg()
> function to reflect that the architectural zero register does not
> necessarily need to be directly mapped, or (b) share a direct-mapped zero
> register among threads. I've implemented both, and they both successfully
> pass the assert. I'll try to push a patch for one soon.
>
> Unfortunately, SMT in SE mode still fails for x86 despite this change, as
> the processor attempts to read an unmapped address later during execution.
> Still trying to debug that. I've only been able to get SMT working in SE
> mode for ARMv7. I read somewhere that the x86 TLB implementation in gem5
> might have limited support for TLB, but I have yet to confirm this. Any
> help/advice is appreciated.
>
> I second that SMT support in SE mode should be a priority.
>
> Best,
>
> Kevin Loughlin
>
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Re: [gem5-users] Develop branch on github

[Abhishek Singh]

Hello Bobby,

Thank you for taking care of this.

Best regards,

Abhishek


On Fri, Feb 28, 2020 at 3:13 PM Bobby Bruce  wrote:

> Abhishek,
>
> It appears the develop branch is not being properly mirrored correctly to
> GitHub. I'll work to fix this today. Thanks for bringing this to my
> attention.
>
> The feature-gnc3-branch is for the development of a new feature relating
> to the AMD GCN3 ISA architecture. It will be merged to the develop branch
> at a later date.
>
> Kind regards,
> Bobby
> --
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Fri, Feb 28, 2020 at 11:58 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Everyone,
>>
>> Is there a way I can access develop branch on github?
>> In the branches option and tag option, I can not find it.
>>
>> Also, on google what is this branch "feature-gcn3-model
>> <https://gem5.googlesource.com/public/gem5/+/refs/heads/feature-gcn3-model>
>> "?
>>
>>
>>
>>
>> Best regards,
>>
>> Abhishek
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Re: [gem5-users] Develop branch on github

[Abhishek Singh]

Hello Everyone and Bobby,

Are older stable versions removed from GitHub?
Is there a way to access them?


Best regards,

Abhishek


On Fri, Feb 28, 2020 at 4:44 PM Bobby Bruce  wrote:

> The gem5 git repo ( https://github.com/gem5/gem5 ) is now properly
> mirrored!
>
> --
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Fri, Feb 28, 2020 at 12:15 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Bobby,
>>
>> Thank you for taking care of this.
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Fri, Feb 28, 2020 at 3:13 PM Bobby Bruce  wrote:
>>
>>> Abhishek,
>>>
>>> It appears the develop branch is not being properly mirrored correctly
>>> to GitHub. I'll work to fix this today. Thanks for bringing this to my
>>> attention.
>>>
>>> The feature-gnc3-branch is for the development of a new feature relating
>>> to the AMD GCN3 ISA architecture. It will be merged to the develop branch
>>> at a later date.
>>>
>>> Kind regards,
>>> Bobby
>>> --
>>> Dr. Bobby R. Bruce
>>> Room 2235,
>>> Kemper Hall, UC Davis
>>> Davis,
>>> CA, 95616
>>>
>>> web: https://www.bobbybruce.net
>>>
>>>
>>> On Fri, Feb 28, 2020 at 11:58 AM Abhishek Singh <
>>> abhishek.singh199...@gmail.com> wrote:
>>>
>>>> Hello Everyone,
>>>>
>>>> Is there a way I can access develop branch on github?
>>>> In the branches option and tag option, I can not find it.
>>>>
>>>> Also, on google what is this branch "feature-gcn3-model
>>>> <https://gem5.googlesource.com/public/gem5/+/refs/heads/feature-gcn3-model>
>>>> "?
>>>>
>>>>
>>>>
>>>>
>>>> Best regards,
>>>>
>>>> Abhishek
>>>> ___
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[gem5-users] Commit numbers/tags of previous stable version missing

[Abhishek Singh]

Hello everyone,

Can anyone provide me with the commit number of the previous stable version
of gem5?

This stable-tags has been removed recently like 3 days before.

*Bobby and Jason*: Is there any reason for removing it?
I am asking this because there are other simulators (mostly from Prof. Onur
Mutlu’s group are based on it and they have just provided patches to the
old stable versions) which are based on it. And I wanted to use them.

Also, if the tags of them are not coming back, is it possible to get
information on their commit numbers ?
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Re: [gem5-users] Commit numbers/tags of previous stable version missing

[Abhishek Singh]

Thank you Bobby for your reply.

I just found all the tags in my old repos and saved them.



On Sun, Mar 1, 2020 at 11:50 AM Bobby R. Bruce  wrote:

> Abhishek,
>
> I’m not aware of any tags that were previously used to mark stable
> versions. As far as I know, gem5-19 is the first stable release. If patches
> were made to previous versions of the product then I suspect they were made
> to arbitrary revisions, in which case I’d advise getting in contact with
> those who developed these patches for more information. I’m sorry I can’t
> be of more help.
>
> If anyone else has any more information about this then it’d be much
> appreciated.
>
> Kind regards
> Bobby
>
> --
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> On Mar 1, 2020, at 02:50, Abhishek Singh 
> wrote:
>
> 
>
> Hello everyone,
>
> Can anyone provide me with the commit number of the previous stable
> version of gem5?
>
> This stable-tags has been removed recently like 3 days before.
>
> *Bobby and Jason*: Is there any reason for removing it?
> I am asking this because there are other simulators (mostly from Prof.
> Onur Mutlu’s group are based on it and they have just provided patches to
> the old stable versions) which are based on it. And I wanted to use them.
>
> Also, if the tags of them are not coming back, is it possible to get
> information on their commit numbers ?
>
>
>
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Re: [gem5-users] Changing the "inParallelMode"

[Abhishek Singh]

Hi,

This work was started in past
You can the progress information and steps required in this link
http://www.m5sim.org/Parallel_M5

For now seeing the mailing I do not see anyone continuing this work, but
there were people who had started working on this

On Sun, Mar 1, 2020 at 2:25 AM YUCHEN ZHOU  wrote:

> Hi all,
>
>
>
> Recently I  tried to parallelize the gem5's simulation engine to run on
> shared-memory multicore systems.  I changed the value of  "inParallelMode"
> to "true" in eventq.cc which I thought could be used to change the
> execution mode of gem5 and I changed the main.py,  event.mainq =
> event.getEventQueue(0)--> event.mainq = event.getEventQueue(1)  in order
> to generate two threads. Then I used gem5 to simultaneously two programs on
> a multi-core system, then I got a "core dump”.  And I found in
> gem5/src/sim  eventq_ impl:96  assert(!inParallelMode || this ==
> curEventQueue()) failed.
>
> Might I know if there is something wrong with the way I changed the mode
> or the work about Parallelizing M5 is not fully completed?
>
> It would be appreciated if you could reply at your earliest convenience.
>
>
> Thank you!
>
>
> Best regards,
> Yuchen Zhou
>
>
>
>
>
>
>
>
>
>
>
>
>
>
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Re: [gem5-users] Question about CacheLoad/StorePorts

[Abhishek Singh]

Hi,

The configuration in source code are not decided depending on any specific
architecture.
One needs to change it depending on what architecture they are targeting.
If you read papers who have used gem5, they always target a particular
architecture (skylake, coffee lake, or any and or arm, etc) and change
parameters accordingly

On Sun, Mar 1, 2020 at 5:06 PM Chang Hyun Park 
wrote:

> Hello all,
>
> I ran into a question while looking through the `cacheLoadPorts` and
> `cacheStorePorts` variable in `src/cpu/o3/O3CPU.py`[1].
>
> The default values are set to 200, and a search through GitHub shows
> that this default value seems to be always used. (At least for the
> provided example configurations)
>
> My question is doesn't this value look way too large?
> It is known that the Intel Skylake microarchitecture has two loads and
> one store ports.[2]
>
> Should we change the cacheLoadPorts and cacheStorePorts to two and
> one, respectively for more accurate results?
>
> Thank you,
> Chang Hyun Park
>
> [1]
> https://github.com/gem5/gem5/blob/ca1d09608e52f6ca8db8c2288b292731c4cee739/src/cpu/o3/O3CPU.py
> [2]
> https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Scheduler_Ports_.26_Execution_Units
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Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

[Abhishek Singh]

Hi Hao,

I followed all git commands and I get the following error:

(gem5art-env) abs218@comparchT640:~/gem5art_fs/spec2017-experiments$
python3 launch_spec2017_experiments.py

*fatal: your current branch 'master' does not have any commits yet*Traceback
(most recent call last):
  File "launch_spec2017_experiments.py", line 16, in 
documentation = 'local repo to run spec 2017 experiments with gem5'
  File
"/home/abs218/gem5art_fs/spec2017-experiments/gem5art-env/lib/python3.6/site-packages/gem5art/artifact/artifact.py",
line 160, in registerArtifact
data['git'] = getGit(ppath)
  File
"/home/abs218/gem5art_fs/spec2017-experiments/gem5art-env/lib/python3.6/site-packages/gem5art/artifact/artifact.py",
line 82, in getGit
hsh = subprocess.check_output(command, cwd=path)
  File "/usr/lib/python3.6/subprocess.py", line 356, in check_output
**kwargs).stdout
  File "/usr/lib/python3.6/subprocess.py", line 438, in run
output=stdout, stderr=stderr)
subprocess.CalledProcessError: Command '['git', 'log', '-n1',
'--pretty=format:%H']' returned non-zero exit status 128.
(gem5art-env) abs218@comparchT640:~/gem5art_fs/spec2017-experiments$ git
--version
*git version 2.17.1*

*How can I solve this error? *
*Also, is it necessary to use docker and Celery and why? *

Best regards,

Abhishek


On Wed, Mar 4, 2020 at 12:38 AM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hi Hao,
>
> I was able to solve the problem by modifying install-spec2017.sh.
>
> I have skipped all git related commands in "
> https://gem5art.readthedocs.io/en/latest/tutorials/spec2017-tutorial.html;
>
> Also, I do not use docker/celery as I do not understand and I feel it's
> not necessary.
>
> When I run this command "python3 launch_spec2017_experiments.py" (there is
> typo in the website) in Python virtual environment, I get following error:
>
> fatal: not a git repository (or any of the parent directories): .git
> Traceback (most recent call last):
>   File "launch_spec2017_experiments.py", line 16, in 
> documentation = 'local repo to run spec 2017 experiments with gem5'
>   File
> "/home/abs218/gem5art_fs/spec2017-experiments/gem5art-env/lib/python3.6/site-packages/gem5art/artifact/artifact.py",
> line 160, in registerArtifact
> data['git'] = getGit(ppath)
>   File
> "/home/abs218/gem5art_fs/spec2017-experiments/gem5art-env/lib/python3.6/site-packages/gem5art/artifact/artifact.py",
> line 74, in getGit
> raise Exception("git repo doesn't exist for {}".format(path))
> Exception: git repo doesn't exist for
> /home/abs218/gem5art_fs/spec2017-experiments
>
>
> My question is why is it important to make a git repo? also will making
> git repo solve the above error?
>
>
>
>
>
> Best regards,
>
> Abhishek
>
>
> On Tue, Mar 3, 2020 at 9:46 PM Hoa Nguyen  wrote:
>
>> The binaries are compiled on guest.
>>
>> Regards,
>> Hoa Nguyen
>>
>> On Tue, Mar 3, 2020, 6:35 PM Abhishek Singh <
>> abhishek.singh199...@gmail.com> wrote:
>>
>>> Hi,
>>>
>>> I do not understand how it will be different, is it anyway using my host
>>> machine library?
>>>
>>>
>>> When I mount the image, the binaries are present in "/usr" as you
>>> mentioned.
>>>
>>> Also is this sed command correct? sed -i
>>> "s/\/opt\/rh\/devtoolset-7\/root\/usr/\/usr/g"
>>> /home/gem5/spec2017/config/myconfig.x86.cfg
>>>
>>>
>>>
>>>
>>>
>>> Best regards,
>>>
>>> Abhishek
>>>
>>>
>>> On Tue, Mar 3, 2020 at 9:26 PM Hoa Nguyen  wrote:
>>>
>>>> So can you take a look at the path to gcc in
>>>> /home/gem5/spec2017/config/Example-gcc-linux-x86.cfg.
>>>>
>>>> In our SPEC 2017 ISO, the default path is
>>>> /opt/rh/devtoolset-7/root/usr/.
>>>>
>>>> So, in install-spec2017.sh, we use a sed command to replace that
>>>> default path to /usr.
>>>>
>>>> In your case, the default path might be different, so you would need to
>>>> change the sed command in install-spec2017.sh to change the path to /usr.
>>>>
>>>> Regards,
>>>> Hoa Nguyen
>>>>
>>>> On Tue, Mar 3, 2020, 6:10 PM Abhishek Singh <
>>>> abhishek.singh199...@gmail.com> wrote:
>>>>
>>>>> Hi Hoa,
>>>>>
>>>>> I mounted the spec image and found that in file "myconfig.x86.cfg"
>>>>> file which is used to compile spec

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

[Abhishek Singh]

Hi Hao,

I was able to solve the git error. Thank you for that.
I followed commands for setting up docker from your tutorial.
When I enter the command to set "celery" in my database path, I get the
following error:

Error Message:
usage: celery worker [options]
celery: error: unrecognized arguments: of workers],0

My command is "celery -E -A gem5art.tasks.celery worker --autoscale=[number
of workers],0"

I have created a directory called database and my docker command is "sudo
docker run -p 27017:27017 -v */home/abs218/gem5art_fs/database*:/data/db
--name mongo-1 -d mongo"
Is there a way to solve this problem?

Best regards,

Abhishek


On Wed, Mar 4, 2020 at 1:55 AM Hoa Nguyen  wrote:

> Hi Abhishek,
>
> Regarding to the git error, you’ll need to “git commit” the changes in the
> git repos that you created.
>
> Using celery is not required, but it is useful to manage a large amount of
> gem5art runs. You might find these links helpful,
>
> - What is task/celery?
> https://gem5art.readthedocs.io/en/latest/main-doc/tasks.html
> - How to use gem5art without celery?
> https://gem5art.readthedocs.io/en/latest/main-doc/faq.html
>
> Even though using docker is also not required, it is highly recommended
> since it is an easy way to deploy mongodb server.
>
> Regards,
> Hoa Nguyen
>
> On Tue, Mar 3, 2020 at 10:02 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hi Hao,
>>
>> I followed all git commands and I get the following error:
>>
>> (gem5art-env) abs218@comparchT640:~/gem5art_fs/spec2017-experiments$
>> python3 launch_spec2017_experiments.py
>>
>> *fatal: your current branch 'master' does not have any commits yet*Traceback
>> (most recent call last):
>>   File "launch_spec2017_experiments.py", line 16, in 
>> documentation = 'local repo to run spec 2017 experiments with gem5'
>>   File
>> "/home/abs218/gem5art_fs/spec2017-experiments/gem5art-env/lib/python3.6/site-packages/gem5art/artifact/artifact.py",
>> line 160, in registerArtifact
>> data['git'] = getGit(ppath)
>>   File
>> "/home/abs218/gem5art_fs/spec2017-experiments/gem5art-env/lib/python3.6/site-packages/gem5art/artifact/artifact.py",
>> line 82, in getGit
>> hsh = subprocess.check_output(command, cwd=path)
>>   File "/usr/lib/python3.6/subprocess.py", line 356, in check_output
>> **kwargs).stdout
>>   File "/usr/lib/python3.6/subprocess.py", line 438, in run
>> output=stdout, stderr=stderr)
>> subprocess.CalledProcessError: Command '['git', 'log', '-n1',
>> '--pretty=format:%H']' returned non-zero exit status 128.
>> (gem5art-env) abs218@comparchT640:~/gem5art_fs/spec2017-experiments$ git
>> --version
>> *git version 2.17.1*
>>
>> *How can I solve this error? *
>> *Also, is it necessary to use docker and Celery and why? *
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Wed, Mar 4, 2020 at 12:38 AM Abhishek Singh <
>> abhishek.singh199...@gmail.com> wrote:
>>
>>> Hi Hao,
>>>
>>> I was able to solve the problem by modifying install-spec2017.sh.
>>>
>>> I have skipped all git related commands in "
>>> https://gem5art.readthedocs.io/en/latest/tutorials/spec2017-tutorial.html
>>> "
>>>
>>> Also, I do not use docker/celery as I do not understand and I feel it's
>>> not necessary.
>>>
>>> When I run this command "python3 launch_spec2017_experiments.py" (there
>>> is typo in the website) in Python virtual environment, I get following
>>> error:
>>>
>>> fatal: not a git repository (or any of the parent directories): .git
>>> Traceback (most recent call last):
>>>   File "launch_spec2017_experiments.py", line 16, in 
>>> documentation = 'local repo to run spec 2017 experiments with gem5'
>>>   File
>>> "/home/abs218/gem5art_fs/spec2017-experiments/gem5art-env/lib/python3.6/site-packages/gem5art/artifact/artifact.py",
>>> line 160, in registerArtifact
>>> data['git'] = getGit(ppath)
>>>   File
>>> "/home/abs218/gem5art_fs/spec2017-experiments/gem5art-env/lib/python3.6/site-packages/gem5art/artifact/artifact.py",
>>> line 74, in getGit
>>> raise Exception("git repo doesn't exist for {}".format(path))
>>> Exception: git repo doesn't exist for
>>> /home/abs218/gem5art_fs/spec2017-experiments
>>>
>>>
>>> My question is why is it important to make a git repo? also will making
>>

[gem5-users] Tutorial on Porting Spec 2017 benchmarks to SE x86 cpu

[Abhishek Singh]

Hello Everyone,

Does anyone has ported spec 2017 benchmarks to SE gem5?
If yes, can you share some steps?

Currently, I am trying FS from gem5art but having some error with the
scripts and I am trying to solve but FS mode according to gem5art, can be
used only with 1 CPU in o3 CPU mode with the commit specified.
This will limit multi-core simulations, that is why I wanted to see if
there's anyone who ported spec 2017 to gem5 SE mode.



Best regards,

Abhishek
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Re: [gem5-users] gem5 X86 full system simulation with a recent version of ubuntu(18.04)

[Abhishek Singh]

Hello Ayaz,

Can this image accept the rcS script provided using the Command line?

For example in this way:

 ./build/X86/gem5.opt
--outdir=/home/abs218/whisper_gem5_setup/gem5_latest/scalibility_chkpt/
--stats-file=scalibility_chkpt.simout --dump-config=scalibility_chkpt.ini
--redirect-stderr --stderr-file=scalibility_chkpt.e configs/example/fs.py
--checkpoint-dir=/home/abs218/whisper_gem5_setup/gem5_latest/scalibility_chkpt/
--disk-image=/home/abs218/whisper_gem5_setup/benchmarks/gem5art/base.img
--kernel=/home/abs218/new_fs/gem5/linux-4.8.13/vmlinux
--script=scalibility.rcS


Best regards,

Abhishek


On Fri, Jan 24, 2020 at 2:05 AM Ayaz Akram  wrote:

> Hi Rubel,
>
> You can download a disk image with ubuntu 18.04 using the following link:
>
> http://dist.gem5.org/images/x86/ubuntu-18-04/base.img
>
> We have also uploaded some linux kernel binaries and associated kernel
> config files, which you can download from the following links:
>
> http://dist.gem5.org/kernels/x86/static/vmlinux-4.14.134
> http://dist.gem5.org/kernels/x86/static/vmlinux-4.14.134.config
>
> In the above links, replace vmlinux-4.14.134
>   with any
> kernel from this list:  vmlinux-4.19.83
> , vmlinux-4.4.1
> *86*,
> vmlinux-5.2.3 ,
> vmlinux-4.9.186  to
> download that kernel binary or the kernel config file used to build the
> kernel.
>
> In order to find out which kernel versions work on which gem5 configs, you
> can refer to the status plots shown at the bottom of the following tutorial:
>
> https://gem5art.readthedocs.io/en/latest/tutorials/boot-tutorial.html
>
> Please, note that these status plots are generated using gem5 commit:
> d40f0bc579fb8b10da7181.
>
> We will soon release more details on the methodology (gem5art: libraries
> for artifacts, reproducibility and testing) used to generate these plots.
>
> Regards,
> Ayaz
>
>
> On Thu, Jan 23, 2020 at 8:11 AM Md Rubel Ahmed 
> wrote:
>
>> Hi all,
>> I want to run ubuntu 18.04 on top of X86 gem5.opt full system. I am
>> specifically interested in running a multi-threaded program on this OS.  I
>> have followed the below tutorials but could not get my required version
>> booted.
>> Tutorials:
>> 1. http://www.lowepower.com/jason/setting-up-gem5-full-system.html
>> 2. https://docs.simplessd.org/tips/kernel.html
>> I also tried with the kernel and disk img provided with the tutorial [2].
>> But still getting similar errors:
>>
>> ```
>> VFS: Cannot open root device "hda1" or unknown-block(3,1)
>> Please append a correct "root=" boot option; here are the available
>> partitions:
>> 0300 16 hda driver: ide-disk
>> 0340 524160 hdb driver: ide-disk
>>   0341 524128 hdb1
>> ```
>>
>> Now I am asking if anyone has a good kernel and image built with some
>> latest version of ubuntu/Linux and publicly available, or can someone tell
>> me the steps needed to overcome the errors and getting my job done.
>>
>> Thanks for your time.
>> Regards,
>> Rubel
>> ___
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>
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Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

[Abhishek Singh]

Hi Hoa,
Are you able to run on o3 cpu.
Also, is it same gem5 commit as mentioned on the website?

On Tue, Mar 3, 2020 at 4:35 AM Hoa Nguyen  wrote:

> Hi there,
>
> We're actually able to run SPEC 2017 workloads in FS mode using the
> gem5art's tutorial.
>
> The table should have been updated.
>
> Sorry about the confusion!
>
> Regards,
> Hoa Nguyen
>
>
> On Mon, Mar 2, 2020, 7:55 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hi,
>>
>> This is the i got in past when I was trying to run SPEC in SE mode
>>
>> If you check mailing list there are suggestions about it
>>
>> I have not yet ported the spec 2017 to gem5, I was trying to use FS but
>> then I saw that 03 CPU in gem5art shows unsuccessful
>>
>> I am planning to port spec benchmarks in coming weeks
>>
>> If you or ANYONE have already posted SPEC 2017 benchmarks for O3CPU
>> please share your knowledge and steps ?
>>
>> On Mon, Mar 2, 2020 at 10:50 PM 616653241 <616653...@qq.com> wrote:
>>
>>> Hi Abhishek ,
>>>   I am running the spec 2017 in the gem5 simulator(X86). But a
>>> lot of benchmarks didnt works.
>>>   It shown tha :
>>>   warn:instruction 'movntdq_Mo_Vo' unimplemented.
>>>So,what I do for it?
>>>  And anyone can tell me how to deal with it? Thank you.
>>>
>>> -- 原始邮件 --
>>> *发件人:* "Abhishek Singh";
>>> *发送时间:* 2020年3月3日(星期二) 凌晨5:09
>>> *收件人:* "gem5 users mailing list";"yazakram"<
>>> yazak...@ucdavis.edu>;
>>> *主题:* Re: [gem5-users] Installing Shared Libraries to Image in Full
>>> Simulation
>>>
>>> Hi Ayaz,
>>>
>>> I am using gem5art to get spec 2017 installed in the image.
>>> I am at this "Building the Disk Image" step
>>> When I use this command "./packer build spec2017/spec2017.json"
>>> I get the following error:
>>>
>>> qemu output will be in this color.
>>>
>>> ==> qemu: Retrieving ISO
>>> ==> qemu: Trying
>>> http://old-releases.ubuntu.com/releases/18.04.2/ubuntu-18.04.2-server-amd64.iso
>>> ==> qemu: Trying
>>> http://old-releases.ubuntu.com/releases/18.04.2/ubuntu-18.04.2-server-amd64.iso?checksum=md5%3A34416ff83179728d54583bf3f18d42d2
>>> ==> qemu:
>>> http://old-releases.ubuntu.com/releases/18.04.2/ubuntu-18.04.2-server-amd64.iso?checksum=md5%3A34416ff83179728d54583bf3f18d42d2
>>> =>
>>> /home/abs218/spec2017-experiments/disk-image/packer_cache/8ecbb06d2a38105b7d1cb3316cf5b970ee389dad.iso
>>> ==> qemu: Creating floppy disk...
>>> qemu: Copying files flatly from floppy_files
>>> qemu: Copying file: shared/preseed.cfg
>>> qemu: Done copying files from floppy_files
>>> qemu: Collecting paths from floppy_dirs
>>> qemu: Resulting paths from floppy_dirs : []
>>> qemu: Done copying paths from floppy_dirs
>>> ==> qemu: Creating required virtual machine disks
>>> ==> qemu: Starting HTTP server on port 8208
>>> ==> qemu: Found port for communicator (SSH, WinRM, etc): 4049.
>>> ==> qemu: Looking for available port between 5900 and 6000 on 127.0.0.1
>>> ==> qemu: Starting VM, booting from CD-ROM
>>> qemu: The VM will be run headless, without a GUI. If you want to
>>> qemu: view the screen of the VM, connect via VNC without a password
>>> to
>>> qemu: vnc://127.0.0.1:5993
>>> ==> qemu: Overriding defaults Qemu arguments with QemuArgs...
>>> ==> qemu: Error launching VM: Qemu failed to start. Please run with
>>> PACKER_LOG=1 to get more info.
>>> ==> qemu: Deleting output directory...
>>>
>>>
>>>
>>> *Build 'qemu' errored: Build was halted.==> Some builds didn't complete
>>> successfully and had errors:--> qemu: Build was halted.*
>>>
>>> Please note I am doing ssh into the machine and I ssh using "ssh -Y" for
>>> getting x11 display.
>>>
>>> I am not able to bypass this error, do you have any tips how to overcome
>>> this error?
>>>
>>>
>>>
>>> Best regards,
>>>
>>> Abhishek
>>>
>>>
>>> On Sat, Feb 8, 2020 at 5:42 PM Ayaz Akram  wrote:
>>>
>>>> Hi  Abhishek,
>>>>
>>>> That was at least the case with the gem5 version we tested (commit

Re: [gem5-users] how to Run spec cpu 2006 on gem5-Fs

[Abhishek Singh]

Hi,

Follow this
https://gem5art.readthedocs.io/en/latest/

On Mon, Mar 2, 2020 at 12:50 PM FARIDEH ZIAEE 
wrote:

> Hi,
> I need to run spec cpu 2006 on gem5-Fs mode but I don't know how to run it.
> also ,according to  site""
> https://yulistic.gitlab.io/2016/05/gem5-make-a-new-boot-image/"; I make a
> new boot image :
>d if=/dev/zero of=ubuntu.img bs=1M count=12288
> ls -alh
> fdisk -l ubuntu.img
>   sudo fdisk ubuntu.img
>   fdisk -l ubuntu.img
> sudo losetup -f
> sudo losetup -o $((512*2048)) /dev/loop8 ubuntu.img
> sudo mke2fs /dev/loop8
> sudo losetup -d /dev/loop8
> //
> and copy  all of file form 
> aarch32-ubuntu-natty-headless.img(aar20ch-system-14-10
> ) to new boot image. Then I istall and compile spec cpu 2006 on
>  linux(ubuntu-18.04-desktop-amd64) according to this site:"
> https://www.spec.org/cpu2006/Docs/install-guide-unix.html; :
>  *cd  SPEC_CPU2006*
>  *./install.sh *
>  *cd /cpu2006/*
>  *. ./shrc*
>  *cd config*
>  *cp Example-linux64-amd64-gcc43+.cfg mytest.cfg*
> * runspec --config=mytest.cfg --action=build --tune=base bzip2*
>  *runspec --config=mytest.cfg --size=test --noreportable
> --tune=base --iterations=1 bzip2*
>  *runspec --config=mytest.cfg --size=ref --noreportable
> --tune=base --iterations=1 bzip2*
> */*
> *Also I learn how to add file to the image , according to this site:"*
> https://spark.nitk.ac.in/r/GEM5-FS-Run.pdf;
> ,but I don't know wich files of spec cpu 2006 add to image and how to
> write runscrip  for spe cpu 2006 .
> Can any one help and giude me? and I did  those things, were those correct?
>
> Best Regards.
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Re: [gem5-users] Question about CacheLoad/StorePorts

[Abhishek Singh]

Hi,

You are right about values of ports not being sensible.
Set the values depending on the architecture (coffee lake, skylake, etc)

Correct values of hardware components can be found in their manual

On Tue, Mar 3, 2020 at 5:32 PM Chang Hyun Park 
wrote:

> Thank you, Abhishek for your reply.
> (For some reason your mail didn't make it into my inbox).
>
> The reason I brought the question up was because the other parameters
> (ROB size, register file size, dispatch width, etc) look like sensible
> values, but the cacheLoad/StorePorts just seemed way off.
> And Also I was not sure if I should be setting the values to two and
> one respectively.
>
> Best,
> - Chang Hyun Park
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Re: [gem5-users] gem5 X86 full system simulation with a recent version of ubuntu(18.04)

[Abhishek Singh]

Hi Ayaz,

Thanks for getting back, I was able to solve this problem by using another
method.

Best regards,

Abhishek


On Tue, Mar 3, 2020 at 6:37 PM Ayaz Akram  wrote:

> Hi Abhishek,
>
> By default, the root/.bashrc on this image has an m5 exit call and will
> lead to simulation termination after linux boot up. If you update the
> .bashrc file by adding a m5 readfile, you should be able to use an rcS
> script with this image. Please, refer to the following script on how to use
> m5 readfile:
>
> https://github.com/darchr/gem5art/blob/master/docs/disks/npb/runscript.sh
>
> -Ayaz
>
>
> On Tue, Mar 3, 2020 at 7:32 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Ayaz,
>>
>> Can this image accept the rcS script provided using the Command line?
>>
>> For example in this way:
>>
>>  ./build/X86/gem5.opt
>> --outdir=/home/abs218/whisper_gem5_setup/gem5_latest/scalibility_chkpt/
>> --stats-file=scalibility_chkpt.simout --dump-config=scalibility_chkpt.ini
>> --redirect-stderr --stderr-file=scalibility_chkpt.e configs/example/fs.py
>> --checkpoint-dir=/home/abs218/whisper_gem5_setup/gem5_latest/scalibility_chkpt/
>> --disk-image=/home/abs218/whisper_gem5_setup/benchmarks/gem5art/base.img
>> --kernel=/home/abs218/new_fs/gem5/linux-4.8.13/vmlinux
>> --script=scalibility.rcS
>>
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Fri, Jan 24, 2020 at 2:05 AM Ayaz Akram  wrote:
>>
>>> Hi Rubel,
>>>
>>> You can download a disk image with ubuntu 18.04 using the following link:
>>>
>>> http://dist.gem5.org/images/x86/ubuntu-18-04/base.img
>>>
>>> We have also uploaded some linux kernel binaries and associated kernel
>>> config files, which you can download from the following links:
>>>
>>> http://dist.gem5.org/kernels/x86/static/vmlinux-4.14.134
>>> http://dist.gem5.org/kernels/x86/static/vmlinux-4.14.134.config
>>>
>>> In the above links, replace vmlinux-4.14.134
>>> <http://dist.gem5.org/kernels/x86/static/vmlinux-4.14.134>  with any
>>> kernel from this list:  vmlinux-4.19.83
>>> <http://dist.gem5.org/kernels/x86/static/vmlinux-4.19.83>, vmlinux-4.4.1
>>> <http://dist.gem5.org/kernels/x86/static/vmlinux-4.4.189>*86*,
>>> vmlinux-5.2.3 <http://dist.gem5.org/kernels/x86/static/vmlinux-5.2.3>,
>>> vmlinux-4.9.186
>>> <http://dist.gem5.org/kernels/x86/static/vmlinux-4.9.186> to download
>>> that kernel binary or the kernel config file used to build the kernel.
>>>
>>> In order to find out which kernel versions work on which gem5 configs,
>>> you can refer to the status plots shown at the bottom of the following
>>> tutorial:
>>>
>>> https://gem5art.readthedocs.io/en/latest/tutorials/boot-tutorial.html
>>>
>>> Please, note that these status plots are generated using gem5 commit:
>>> d40f0bc579fb8b10da7181.
>>>
>>> We will soon release more details on the methodology (gem5art: libraries
>>> for artifacts, reproducibility and testing) used to generate these plots.
>>>
>>> Regards,
>>> Ayaz
>>>
>>>
>>> On Thu, Jan 23, 2020 at 8:11 AM Md Rubel Ahmed <
>>> mdrubelah...@mail.usf.edu> wrote:
>>>
>>>> Hi all,
>>>> I want to run ubuntu 18.04 on top of X86 gem5.opt full system. I am
>>>> specifically interested in running a multi-threaded program on this OS.  I
>>>> have followed the below tutorials but could not get my required version
>>>> booted.
>>>> Tutorials:
>>>> 1. http://www.lowepower.com/jason/setting-up-gem5-full-system.html
>>>> 2. https://docs.simplessd.org/tips/kernel.html
>>>> I also tried with the kernel and disk img provided with the tutorial
>>>> [2]. But still getting similar errors:
>>>>
>>>> ```
>>>> VFS: Cannot open root device "hda1" or unknown-block(3,1)
>>>> Please append a correct "root=" boot option; here are the available
>>>> partitions:
>>>> 0300 16 hda driver: ide-disk
>>>> 0340 524160 hdb driver: ide-disk
>>>>   0341 524128 hdb1
>>>> ```
>>>>
>>>> Now I am asking if anyone has a good kernel and image built with some
>>>> latest version of ubuntu/Linux and publicly available, or can someone tell
>>>> me the steps needed to overcome the errors and getting my job done.
>>>>
>>>> Thanks for your time.
>>>> Regards,
>>>> Rubel
>>>> ___
>>>> gem5-users mailing list
>>>> gem5-users@gem5.org
>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

[Abhishek Singh]

Hi,

In order to run SPEC2k17 benchmarks, should we follow the same tutorial "
https://gem5art.readthedocs.io/en/latest/tutorials/spec2017-tutorial.html;?


Best regards,

Abhishek


On Tue, Mar 3, 2020 at 6:45 PM Hoa Nguyen  wrote:

> Hi Abhishek,
>
> We ran a few spec2017 workloads on O3CPU, and they ran successfully.
>
> We used gem5 19.
>
> Regards,
> Hoa Nguyen
>
> On 3/3/20, Abhishek Singh  wrote:
> > Hi Hoa,
> > Are you able to run on o3 cpu.
> > Also, is it same gem5 commit as mentioned on the website?
> >
> > On Tue, Mar 3, 2020 at 4:35 AM Hoa Nguyen  wrote:
> >
> >> Hi there,
> >>
> >> We're actually able to run SPEC 2017 workloads in FS mode using the
> >> gem5art's tutorial.
> >>
> >> The table should have been updated.
> >>
> >> Sorry about the confusion!
> >>
> >> Regards,
> >> Hoa Nguyen
> >>
> >>
> >> On Mon, Mar 2, 2020, 7:55 PM Abhishek Singh <
> >> abhishek.singh199...@gmail.com> wrote:
> >>
> >>> Hi,
> >>>
> >>> This is the i got in past when I was trying to run SPEC in SE mode
> >>>
> >>> If you check mailing list there are suggestions about it
> >>>
> >>> I have not yet ported the spec 2017 to gem5, I was trying to use FS but
> >>> then I saw that 03 CPU in gem5art shows unsuccessful
> >>>
> >>> I am planning to port spec benchmarks in coming weeks
> >>>
> >>> If you or ANYONE have already posted SPEC 2017 benchmarks for O3CPU
> >>> please share your knowledge and steps ?
> >>>
> >>> On Mon, Mar 2, 2020 at 10:50 PM 616653241 <616653...@qq.com> wrote:
> >>>
> >>>> Hi Abhishek ,
> >>>>   I am running the spec 2017 in the gem5 simulator(X86). But a
> >>>> lot of benchmarks didnt works.
> >>>>   It shown tha :
> >>>>   warn:instruction 'movntdq_Mo_Vo' unimplemented.
> >>>>So,what I do for it?
> >>>>  And anyone can tell me how to deal with it? Thank you.
> >>>>
> >>>> -- 原始邮件 --
> >>>> *发件人:* "Abhishek Singh";
> >>>> *发送时间:* 2020年3月3日(星期二) 凌晨5:09
> >>>> *收件人:* "gem5 users mailing list";"yazakram"<
> >>>> yazak...@ucdavis.edu>;
> >>>> *主题:* Re: [gem5-users] Installing Shared Libraries to Image in Full
> >>>> Simulation
> >>>>
> >>>> Hi Ayaz,
> >>>>
> >>>> I am using gem5art to get spec 2017 installed in the image.
> >>>> I am at this "Building the Disk Image" step
> >>>> When I use this command "./packer build spec2017/spec2017.json"
> >>>> I get the following error:
> >>>>
> >>>> qemu output will be in this color.
> >>>>
> >>>> ==> qemu: Retrieving ISO
> >>>> ==> qemu: Trying
> >>>>
> http://old-releases.ubuntu.com/releases/18.04.2/ubuntu-18.04.2-server-amd64.iso
> >>>> ==> qemu: Trying
> >>>>
> http://old-releases.ubuntu.com/releases/18.04.2/ubuntu-18.04.2-server-amd64.iso?checksum=md5%3A34416ff83179728d54583bf3f18d42d2
> >>>> ==> qemu:
> >>>>
> http://old-releases.ubuntu.com/releases/18.04.2/ubuntu-18.04.2-server-amd64.iso?checksum=md5%3A34416ff83179728d54583bf3f18d42d2
> >>>> =>
> >>>>
> /home/abs218/spec2017-experiments/disk-image/packer_cache/8ecbb06d2a38105b7d1cb3316cf5b970ee389dad.iso
> >>>> ==> qemu: Creating floppy disk...
> >>>> qemu: Copying files flatly from floppy_files
> >>>> qemu: Copying file: shared/preseed.cfg
> >>>> qemu: Done copying files from floppy_files
> >>>> qemu: Collecting paths from floppy_dirs
> >>>> qemu: Resulting paths from floppy_dirs : []
> >>>> qemu: Done copying paths from floppy_dirs
> >>>> ==> qemu: Creating required virtual machine disks
> >>>> ==> qemu: Starting HTTP server on port 8208
> >>>> ==> qemu: Found port for communicator (SSH, WinRM, etc): 4049.
> >>>> ==> qemu: Looking for available port between 5900 and 6000 on
> 127.0.0.1
> >>>> ==> qemu: Starting VM, booting from CD-ROM
> >>>> qemu: The VM will be run headless, without a GUI. If

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

[Abhishek Singh]

/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
500.perlbench_r/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
510.parest_r/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/g++: Command not found
625.x264_s/build/build_base_mytest-m64./make.imagevalidate_625.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
520.omnetpp_r/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/g++: Command not found
621.wrf_s/build/build_base_mytest-m64./make.diffwrf_621.out:40:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
531.deepsjeng_r/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/g++: Command not found
544.nab_r/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
602.gcc_s/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
519.lbm_r/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
620.omnetpp_s/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/g++: Command not found
541.leela_r/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/g++: Command not found
644.nab_s/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
508.namd_r/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/g++: Command not found
628.pop2_s/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
525.x264_r/build/build_base_mytest-m64./make.imagevalidate_525.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
627.cam4_s/build/build_base_mytest-m64./make.cam4_s.out:21:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
623.xalancbmk_s/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/g++: Command not found
605.mcf_s/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
507.cactuBSSN_r/build/build_base_mytest-m64./make.out:2:specmake:
/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found

Error Message (qemu)

qemu: Build errors for intspeed: 600.perlbench_s(base; CE),
602.gcc_s(base; CE), 605.mcf_s(base; CE), 620.omnetpp_s(base; CE),
623.xalancbmk_s(base; CE), 625.x264_s(base; CE), 631.deepsjeng_s(base; CE),
641.leela_s(base; CE), 648.exchange2_s(base; CE), 657.xz_s(base; CE),
998.specrand_is(base; CE)
qemu: Build errors for intrate: 500.perlbench_r(base; CE),
502.gcc_r(base; CE), 505.mcf_r(base; CE), 520.omnetpp_r(base; CE),
523.xalancbmk_r(base; CE), 525.x264_r(base; CE), 531.deepsjeng_r(base; CE),
541.leela_r(base; CE), 548.exchange2_r(base; CE), 557.xz_r(base; CE),
999.specrand_ir(base; CE)
qemu: Build errors for fpspeed: 603.bwaves_s(base; CE),
607.cactuBSSN_s(base; CE), 619.lbm_s(base; CE), 621.wrf_s(base; CE),
627.cam4_s(base; CE), 628.pop2_s(base; CE), 638.imagick_s(base; CE),
644.nab_s(base; CE), 649.fotonik3d_s(base; CE), 654.roms_s(base; CE),
996.specrand_fs(base; CE)
qemu: Build errors for fprate: 503.bwaves_r(base; CE),
507.cactuBSSN_r(base; CE), 508.namd_r(base; CE), 510.parest_r(base; CE),
511.povray_r(base; CE), 519.lbm_r(base; CE), 521.wrf_r(base; CE),
526.blender_r(base; CE), 527.cam4_r(base; CE), 538.imagick_r(base; CE),
544.nab_r(base; CE), 549.fotonik3d_r(base; CE), 554.roms_r(base; CE),
997.specrand_fr(base; CE)


Best regards,

Abhishek


On Tue, Mar 3, 2020 at 7:53 PM Hoa Nguyen  wrote:

> Hi Abhishek,
>
> Yes, but the gem5 config only has one-core O3CPU. It could be tweaked to
> multiple cores.
>
> Regards,
> Hoa Nguyen
>
> On Tue, Mar 3, 2020, 3:48 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hi,
>>
>> In order to run SPEC2k17 benchmarks, should we follow the same tutorial "
>> https://gem5art.readthedocs.io/en/latest/tutorials/spec2017-tutorial.html
>> "?
>>
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Tue, Mar 3, 2020 at 6:45 PM Hoa Nguyen  wrote:
>>
>>> Hi Abhishek,
>>>
>>> We ran a few spec2017 workloads on O3CPU, and they ran successfully.
>>>
>>> We used gem5 19.
>>>
>>> Regards,
>>> Hoa Nguyen
>>>
>>> On 3/3/20, Abhishek Singh  wrote:
>>> > Hi Hoa,
>>> > Are you 

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

[Abhishek Singh]

Hi Hoa,

I mounted the spec image and found that in file "myconfig.x86.cfg" file
which is used to compile spec benchmarks have this gcc linking to
"/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0"

Did you guys use this "myconfig.x86.cfg" file in the result shown on the "
https://gem5art.readthedocs.io/en/latest/tutorials/spec2017-tutorial.html;?


Best regards,

Abhishek


On Tue, Mar 3, 2020 at 8:52 PM Hoa Nguyen  wrote:

> Did you modify any file downloaded from gem5art repo?
>
> Regards,
> Hoa Nguyen
>
> On Tue, Mar 3, 2020, 5:44 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> I mounted the image and there was no SW folder
>>
>> On Tue, Mar 3, 2020 at 8:42 PM Hoa Nguyen  wrote:
>>
>>> Hi,
>>>
>>> I'm not sure where is the error, but I would look into why the path to
>>> gcc is "/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc".
>>>
>>> Regards,
>>> Hoa Nguyen
>>>
>>> On Tue, Mar 3, 2020, 5:28 PM Abhishek Singh <
>>> abhishek.singh199...@gmail.com> wrote:
>>>
>>>> Hi Hoa,
>>>>
>>>> For now, I will try to get a single-core.
>>>>
>>>> In Building the Disk Image Step, I get an error in compiling spec
>>>> benchmarks in the image i.e., after this command ./packer build
>>>> spec2017/spec2017.json
>>>>
>>>>
>>>> I have posted the long error message, I also looked into most of the
>>>> make.out the file, the error is due to the missing gcc and gfortran 
>>>> library.
>>>>
>>>> I did not look up much in detail, as there can be other errors too
>>>>
>>>> Please let me know if I missed some steps in between. I tried twice but
>>>> the error is the same.
>>>>
>>>> Error Message(short version):
>>>> From
>>>> /home/gem5/spec2017/benchspec/CPU/998.specrand_is/build/build_base_mytest-m64./make.out
>>>> file
>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc -std=c99   -m64 -c
>>>> -o main.o -DSPEC -DNDEBUG -Ispecrand-common  -g -O3
>>>>  -fno-unsafe-math-optimizations  -fno-tree-loop-vectorize
>>>> -fopenmp -DSPEC_OPENMP -fno-strict-aliasing   -DSPEC_LP64  main.c
>>>>
>>>> specmake: /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not
>>>> found
>>>>
>>>> specmake: *** [/home/gem5/spec2017/benchspec/Makefile.defaults:347:
>>>> main.o] Error 127
>>>>
>>>> This error is common in all the files along with other libraries such
>>>> as:
>>>>
>>>> 603.bwaves_s/build/build_base_mytest-m64./make.out:3:specmake:
>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gfortran: Command not found
>>>> 600.perlbench_s/build/build_base_mytest-m64./make.out:2:specmake:
>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>>>> 521.wrf_r/build/build_base_mytest-m64./make.diffwrf_521.out:40:specmake:
>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>>>> 523.xalancbmk_r/build/build_base_mytest-m64./make.out:2:specmake:
>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/g++: Command not found
>>>> 557.xz_r/build/build_base_mytest-m64./make.out:2:specmake:
>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>>>> 526.blender_r/build/build_base_mytest-m64./make.blender_r.out:2:specmake:
>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>>>> 505.mcf_r/build/build_base_mytest-m64./make.out:2:specmake:
>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>>>> 607.cactuBSSN_s/build/build_base_mytest-m64./make.out:2:specmake:
>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>>>> 648.exchange2_s/build/build_base_mytest-m64./make.out:3:specmake:
>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gfortran: Command not found
>>>> 527.cam4_r/build/build_base_mytest-m64./make.cam4_r.out:21:specmake:
>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>>>> 503.bwaves_r/build/build_base_mytest-m64./make.out:4:specmake:
>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gfortran: Command not found
>>>> 996.specrand_fs/build/build_base_mytest-m64./make.out:2:specmake:
>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Com

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

[Abhishek Singh]

Hi,

I do not understand how it will be different, is it anyway using my host
machine library?


When I mount the image, the binaries are present in "/usr" as you mentioned.

Also is this sed command correct? sed -i
"s/\/opt\/rh\/devtoolset-7\/root\/usr/\/usr/g"
/home/gem5/spec2017/config/myconfig.x86.cfg





Best regards,

Abhishek


On Tue, Mar 3, 2020 at 9:26 PM Hoa Nguyen  wrote:

> So can you take a look at the path to gcc in
> /home/gem5/spec2017/config/Example-gcc-linux-x86.cfg.
>
> In our SPEC 2017 ISO, the default path is /opt/rh/devtoolset-7/root/usr/.
>
> So, in install-spec2017.sh, we use a sed command to replace that default
> path to /usr.
>
> In your case, the default path might be different, so you would need to
> change the sed command in install-spec2017.sh to change the path to /usr.
>
> Regards,
> Hoa Nguyen
>
> On Tue, Mar 3, 2020, 6:10 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hi Hoa,
>>
>> I mounted the spec image and found that in file "myconfig.x86.cfg" file
>> which is used to compile spec benchmarks have this gcc linking to
>> "/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0"
>>
>> Did you guys use this "myconfig.x86.cfg" file in the result shown on the "
>> https://gem5art.readthedocs.io/en/latest/tutorials/spec2017-tutorial.html
>> "?
>>
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Tue, Mar 3, 2020 at 8:52 PM Hoa Nguyen  wrote:
>>
>>> Did you modify any file downloaded from gem5art repo?
>>>
>>> Regards,
>>> Hoa Nguyen
>>>
>>> On Tue, Mar 3, 2020, 5:44 PM Abhishek Singh <
>>> abhishek.singh199...@gmail.com> wrote:
>>>
>>>> I mounted the image and there was no SW folder
>>>>
>>>> On Tue, Mar 3, 2020 at 8:42 PM Hoa Nguyen 
>>>> wrote:
>>>>
>>>>> Hi,
>>>>>
>>>>> I'm not sure where is the error, but I would look into why the path to
>>>>> gcc is "/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc".
>>>>>
>>>>> Regards,
>>>>> Hoa Nguyen
>>>>>
>>>>> On Tue, Mar 3, 2020, 5:28 PM Abhishek Singh <
>>>>> abhishek.singh199...@gmail.com> wrote:
>>>>>
>>>>>> Hi Hoa,
>>>>>>
>>>>>> For now, I will try to get a single-core.
>>>>>>
>>>>>> In Building the Disk Image Step, I get an error in compiling spec
>>>>>> benchmarks in the image i.e., after this command ./packer build
>>>>>> spec2017/spec2017.json
>>>>>>
>>>>>>
>>>>>> I have posted the long error message, I also looked into most of the
>>>>>> make.out the file, the error is due to the missing gcc and gfortran 
>>>>>> library.
>>>>>>
>>>>>> I did not look up much in detail, as there can be other errors too
>>>>>>
>>>>>> Please let me know if I missed some steps in between. I tried twice
>>>>>> but the error is the same.
>>>>>>
>>>>>> Error Message(short version):
>>>>>> From
>>>>>> /home/gem5/spec2017/benchspec/CPU/998.specrand_is/build/build_base_mytest-m64./make.out
>>>>>> file
>>>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc -std=c99   -m64
>>>>>> -c -o main.o -DSPEC -DNDEBUG -Ispecrand-common  -g -O3
>>>>>>  -fno-unsafe-math-optimizations  -fno-tree-loop-vectorize
>>>>>> -fopenmp -DSPEC_OPENMP -fno-strict-aliasing   -DSPEC_LP64  main.c
>>>>>>
>>>>>> specmake: /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command
>>>>>> not found
>>>>>>
>>>>>> specmake: *** [/home/gem5/spec2017/benchspec/Makefile.defaults:347:
>>>>>> main.o] Error 127
>>>>>>
>>>>>> This error is common in all the files along with other libraries such
>>>>>> as:
>>>>>>
>>>>>> 603.bwaves_s/build/build_base_mytest-m64./make.out:3:specmake:
>>>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gfortran: Command not found
>>>>>> 600.perlbench_s/build/build_base_mytest-m64./make.out:2:specmake:
>>>>>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>>>>>> 

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

[Abhishek Singh]

I mounted the image and there was no SW folder

On Tue, Mar 3, 2020 at 8:42 PM Hoa Nguyen  wrote:

> Hi,
>
> I'm not sure where is the error, but I would look into why the path to gcc
> is "/SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc".
>
> Regards,
> Hoa Nguyen
>
> On Tue, Mar 3, 2020, 5:28 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hi Hoa,
>>
>> For now, I will try to get a single-core.
>>
>> In Building the Disk Image Step, I get an error in compiling spec
>> benchmarks in the image i.e., after this command ./packer build
>> spec2017/spec2017.json
>>
>>
>> I have posted the long error message, I also looked into most of the
>> make.out the file, the error is due to the missing gcc and gfortran library.
>>
>> I did not look up much in detail, as there can be other errors too
>>
>> Please let me know if I missed some steps in between. I tried twice but
>> the error is the same.
>>
>> Error Message(short version):
>> From
>> /home/gem5/spec2017/benchspec/CPU/998.specrand_is/build/build_base_mytest-m64./make.out
>> file
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc -std=c99   -m64 -c
>> -o main.o -DSPEC -DNDEBUG -Ispecrand-common  -g -O3
>>  -fno-unsafe-math-optimizations  -fno-tree-loop-vectorize
>> -fopenmp -DSPEC_OPENMP -fno-strict-aliasing   -DSPEC_LP64  main.c
>>
>> specmake: /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not
>> found
>>
>> specmake: *** [/home/gem5/spec2017/benchspec/Makefile.defaults:347:
>> main.o] Error 127
>>
>> This error is common in all the files along with other libraries such as:
>>
>> 603.bwaves_s/build/build_base_mytest-m64./make.out:3:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gfortran: Command not found
>> 600.perlbench_s/build/build_base_mytest-m64./make.out:2:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>> 521.wrf_r/build/build_base_mytest-m64./make.diffwrf_521.out:40:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>> 523.xalancbmk_r/build/build_base_mytest-m64./make.out:2:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/g++: Command not found
>> 557.xz_r/build/build_base_mytest-m64./make.out:2:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>> 526.blender_r/build/build_base_mytest-m64./make.blender_r.out:2:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>> 505.mcf_r/build/build_base_mytest-m64./make.out:2:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>> 607.cactuBSSN_s/build/build_base_mytest-m64./make.out:2:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>> 648.exchange2_s/build/build_base_mytest-m64./make.out:3:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gfortran: Command not found
>> 527.cam4_r/build/build_base_mytest-m64./make.cam4_r.out:21:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>> 503.bwaves_r/build/build_base_mytest-m64./make.out:4:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gfortran: Command not found
>> 996.specrand_fs/build/build_base_mytest-m64./make.out:2:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>> 657.xz_s/build/build_base_mytest-m64./make.out:2:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>> 638.imagick_s/build/build_base_mytest-m64./make.imagevalidate_638.out:2:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>> 549.fotonik3d_r/build/build_base_mytest-m64./make.out:2:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gfortran: Command not found
>> 538.imagick_r/build/build_base_mytest-m64./make.imagevalidate_538.out:2:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>> 654.roms_s/build/build_base_mytest-m64./make.out:220:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gfortran: Command not found
>> 631.deepsjeng_s/build/build_base_mytest-m64./make.out:2:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/g++: Command not found
>> 998.specrand_is/build/build_base_mytest-m64./make.out:2:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Command not found
>> 619.lbm_s/build/build_base_mytest-m64./make.out:2:specmake:
>> /SW/compilers/GCC/Linux/x86_64/gcc-6.3.0/bin/gcc: Comman