Re: [ARTIQ] ARTIQ Digest, Vol 50, Issue 9

On Sat, Aug 11, 2018 at 12:12 PM Thomas Harty wrote: > - Moninj: Chris B/David N will be able to give a better-informed view on this > than me, but my feeling is that moninj isn't actually that useful for the > SAWG. What would SAWG moninj include? Leaving aside the work/funding required > to

Re: [ARTIQ] ARTIQ Digest, Vol 50, Issue 9

On Sat, Aug 11, 2018 at 12:28 PM Thomas Harty wrote: > Remind me, for the current design, what's a 1 LSB spur in dBc? How does that > scale with the width parameters? 1 LSB is -96 dBc. But e.g. the AA filter is currently -58 dB stopband. > > And regarding the benefit I don't see a reason why

Re: [ARTIQ] ARTIQ Digest, Vol 50, Issue 9

On Wed, Aug 8, 2018 at 9:15 PM Thomas Harty wrote: > I think a short exploratory project would be a good idea, as I have no real > means of making an informed decision about where to shoot for on the > performance/flexibility v complexity scale. 8 CORDICS + accumulators on 8 > channels sounds

Re: [ARTIQ] ARTIQ Digest, Vol 50, Issue 7

On Wed, Jul 18, 2018 at 5:48 PM Thomas Harty via ARTIQ wrote: > > * Is (f0+f1, f0+f2) better than (f0+f1-f2, f0+f1+f2)? (with f0 coarse, > > and f1/f2 fine) etc. Or other parametrizations. > > * What is the maximum step size of f0 in terms of the f1/f2 rate? > > By `(f0 + f1)` do you mean the

Re: [ARTIQ] ARTIQ Digest, Vol 50, Issue 2

On Tue, Jul 17, 2018 at 5:52 PM Slichter, Daniel H. (Fed) via ARTIQ wrote: > > You just need to get away from specifying sample rates and > > details of the DSP chain and start specifying the actual use cases. > > My apologies; I thought I had sent an email to the entire list but it turns > out

Re: [ARTIQ] ARTIQ Digest, Vol 50, Issue 2

On Fri, Jul 13, 2018 at 6:06 PM Slichter, Daniel H. (Fed) via ARTIQ wrote: > I think we will really need the 8x interleaving at the RTIO clock rate, > because 1 GSPS is pretty critical (600 MSPS is marginal or a non-starter for > most of our use cases). This to me seems much more important

[ARTIQ] [JOB] Quantum Control Systems Designer for opticlock

ARTIQ/Sinara related job postings and announcements on this mailing list. Best regards, -- Robert Jördens. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] [ANNOUNCEMENT] optIclock

Official english text below. -- Robert Jördens. Press release „optIclock“ German Quantum Initiative QUTEGA starts with optical single ion clock The German Federal Ministry of Education and Research (BMBF) has initiated a strategy process within the field of quantum technologies that stressed

[ARTIQ] [ANNOUNCEMENT] optIclock

Hello ARTIQ users, we are pleased to officially announce that optIclock, a German 6 Million Euro project to build a portable single-ion optical clock targeting end users, will use and contribute significantly to ARTIQ and Sinara. The German press release text is included below. Feel free to

Re: [ARTIQ] [RFC] remove RTIOCollision

state is kept can be non-idempotent. I don't see how we can track that at the master. Why not do blind submission and do the replacement at the satellite side plus asynchronous error reporting like RTIOBusy? -- Robert Jördens. ___ ARTIQ mailing list ht

[ARTIQ] [NEWS] phaser2 progress

and active phase alignment of the JESD204B device clocks and SYSREF. -- Robert Jördens. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] [RFC] remove output event replacement feature

buffer would require gateware there that depends on channel features on remote DRTIO devices. What one could do is add another bit that marks an event as replaceable. Then the gateware could be agnostic. > * The remote side also has a synchronous FIFO which is easier to handle than >

Re: [ARTIQ] [RFC] remove output event replacement feature

confusing because you can always do both: ttl.pulse(0) and ttl.pulse(10*ns) though they have very different results. But sometimes you can't do: ttl.pulse(5*ns) That raises an exception depending on the exact fine timestamp. -- Robert Jördens. ___ ARTIQ

Re: [ARTIQ] [RFC] remove output event replacement feature

0 you'd have two back to back pi/2 pulses. How would that > need to be coded differently? Explicitly, > > ttl.pulse(t_pi/2) > delay(t) > ttl.pulse(t_pi/2) > > and we scan t from 0 onwards. ttl.on() delay(t_pi/2) ttl.pulse_off(t) delay(t_pi/2) ttl.off() would be a natural

Re: [ARTIQ] [RFC] remove output event replacement feature

s to want to set the frequency of a DDS twice at the same time. -- Robert Jördens. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] [RFC] remove output event replacement feature

PI a logical "address" that discriminates replaceable "register data". That additional address field directly impacts and increases the amount of data that is written on each RTIO event submission. We expect a significant speed up in event rate by removing it. It also bloats DRTIO

[ARTIQ] [RFC] remove output event replacement feature

ise result in RTIOCollision exceptions. We are uncertain to what extent this feature is actually know and used/relied upon in practice. Any comments on removing this feature and making it *always* an RTIOCollision exception when two events are scheduled for the same timestamp on the same channel? -- Robe

Re: [ARTIQ] Fwd: Sinara multi-crate / DRTIO switches

a device that forms a tighter control loop with that Sayma in some extension of DRTIO where that devices can drive other (child) devices. -- Robert Jördens. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

[ARTIQ] Fwd: Sinara multi-crate / DRTIO switches

TIO hierarchy might be more limiting than the number of ADC/DAC channels. -- Robert Jördens. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] Reliable Input Event Handling

lf.pmt0.timestamp_mu() if r > 0: # pulse received during gate at_mu(r + latency) self.ttl1.on() -- Robert Jördens. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

[ARTIQ] Fwd: shared SPI clock

u'll need to learn migen/misoc. It would look something like self.comb += clk.eq(Mux(spi0.cs_n, spi1.clk, spi0.clk)) but it depends on a bunch of other things as well and there is absolutely no safety net or access control. -- Robert Jördens. ___

[ARTIQ] [NEWS] Phaser: JED204B fast multichannel DAC/DDS with ARTIQ RTIO

feel free to forward this to other interested parties. Regards, -- Robert Jördens. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

[ARTIQ] Fwd: Sinara clocking

nd the DAC clocking might not ed up using the same SYSREF. -- Robert Jördens. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

[ARTIQ] ARTIQ 2.0 released

tem design of the various ARTIQ hardware components. A separate announcement and progress report should follow soon. Please feel free to forward this message to other interested users. The ARTIQ team. -- Robert Jördens. ___ ARTIQ mailing

Re: [ARTIQ] 3.3 V I/O on kc705

anual-release-2/core_device.html#vadj -- Robert Jördens. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

[ARTIQ] ARTIQ 2.0rc2

loses #552 -- Robert Jördens. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

[ARTIQ] ARTIQ 2.0rc1

described in the manual). Please feel free to forward this announcement to other interested users and to report your experience in the form of issue reports or to the mailing list, even and especially if it just the one-liner "works fine here". The ARTIQ team.

[ARTIQ] ARTIQ 1.3 released

Hi, ARTIQ 1.3 is out and packages are available under our main Anaconda label. This is a pure bugfix release and we recommend that all 1.0, 1.1, and 1.2 users upgrade to 1.3. Thanks to everyone who submitted detailed bug reports, helped resolve them, or submitted patches. Best, Robert for the

Re: [ARTIQ] DSP gateware

Hi Dave, On Mon, Aug 1, 2016 at 5:15 PM, Leibrandt, David R. (Fed) wrote: > 1. I assume this logic would be followed by some sort of digital filter to > remove the unwanted Nyquist images. Have you thought about how good of > suppression you might be able to achieve,

Re: [ARTIQ] DSP gateware

On Mon, Aug 1, 2016 at 3:59 PM, Jonathan Mizrahi wrote: > I have one question, just out of curiosity: What is the motivation of > linking two "buddy" channels in the way you described, with the b and c > flags to turn these on and off? What application uses this feature? A pair

Re: [ARTIQ] DSP gateware

so be happy to generate a quote for an implementation and/or a hardware demonstrator system. Regards, -- Robert Jördens. phaser_2fd7bfd.pdf Description: Adobe PDF document ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] modifying hardware configurations in ARTIQ

ll have to dive into coding for FPGAs and the usage of these tools, no matter how much documentation we add. -- Robert Jördens. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

[ARTIQ] request for testers

Hello, we expect to publish the first release candidate for the ARTIQ 2.0 release soon. There are a few issues scheduled to be resolved (https://github.com/m-labs/artiq/milestone/2) before 2.0rc1 but there is currently nothing on the radar that implies a critical bug or involves a major change to

Re: [ARTIQ] connecting to KC705

Thanks, Daniel, for helping here. Jonathan: yes. I think most of us have sumbled over that M012 setting. Should go into the documentation I guess. There are also the LEDs, the SMA connectors, and that XADC header (all depending on the adapter bitstream/runtime you are using). Those are

Re: [ARTIQ] connecting to KC705

bit) what does it say? -- Robert Jördens. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

[ARTIQ] ARTIQ 1.0

Hello, we are pleased to announce the first stable release of ARTIQ. A big thanks to all users, contributors, testers, bug hunters, and participants in the mailing list, issue, and offline discussions! Instructions on how to get started with ARTIQ are at

Re: [ARTIQ] DSP gateware

On Fri, Apr 1, 2016 at 1:09 AM, Slichter, Daniel H. (Fed) wrote: >> And a 16 ns pulse would be just about 20 samples. Why would you want to >> describe that using ~4 spline knots each being maybe 16 times 16 bits in >> data. >> If you need the full bandwidth, the idea

Re: [ARTIQ] TTL + slow DACs

On Thu, Mar 31, 2016 at 5:29 PM, Slichter, Daniel H. (Fed) wrote: >> We'll probably want a few dozen TTLs, broken out on SMA, so the FMC panel >> is not an option there. >> >> We can remove PCIe indeed, but keeping the WR oscillators is probably a >> good idea as they

Re: [ARTIQ] Fwd: FW: initial specification of the project

On Wed, Mar 30, 2016 at 10:22 PM, Grzegorz Kasprowicz wrote: > Actually, we can fit a lot to single FMC > Look here: > https://scontent-waw1-1.xx.fbcdn.net/hphotos-xpa1/v/t1.0-9/66620_1649317561668_2595483_n.jpg?oh=982ee50c1a1d8ecc444346c9eae1fe1c=578FA78C > I managed to place

Re: [ARTIQ] FW: initial specification of the project

On Wed, Mar 30, 2016 at 10:25 PM, Slichter, Daniel H. (Fed) wrote: > Now, as you suggest we could just change the level at which we make this > break from the AMC card, shift the DACs and ADCs onto the daughter card as > well, and use FMC to communicate with the whole

Re: [ARTIQ] FW: initial specification of the project

On Wed, Mar 30, 2016 at 5:57 PM, Slichter, Daniel H. (Fed) wrote: >> > What are you thinking for number of daughter cards? I suppose that >> > more would give us more flexibility, but less would be more economical >> > in terms of cost and layout area. Perhaps two

Re: [ARTIQ] FW: initial specification of the project

On Tue, Mar 29, 2016 at 11:56 AM, Sébastien Bourdeauducq wrote: > On Monday, 28 March 2016 6:30:52 PM HKT Slichter, Daniel H. (Fed) wrote: >> Thus for the two examples above, using digital connectors with a 9 mm or 11 >> mm total stackup height would give 250 um axial misalignment

Re: [ARTIQ] FW: initial specification of the project

On Mon, Mar 28, 2016 at 9:14 PM, Slichter, Daniel H. (Fed) wrote: > http://suddendocs.samtec.com/testreports/hsc-report-seam-seaf-07mm_web.pdf > > There is too much crosstalk in FMC connectors (~40-65 dB typical @ 3 GHz) for > us to use them for the RF/analog

[ARTIQ] Fwd: analog extension cards

Nobody wants to use the FMC connectors without testing them. The FMC connectors will in all likelihood only be the limiting factor if _no_ shielding is used for the other parts. That includes shielding for the clock generation, the DACs/ADCs the connection to the analog daughter boards, and the

Re: [ARTIQ] ARTIQ hardware proposal

On Sat, Mar 19, 2016 at 8:54 PM, Tan, Ting Rei (IntlAssoc) wrote: > For complicated trap users, the most common use case is to drive trap > electrode so we will need much more DAC channels and ADC channels. One > possible solution is to have two kind of DSP boards? One with

Re: [ARTIQ] ARTIQ hardware proposal

On Sat, Mar 19, 2016 at 12:09 PM, Sébastien Bourdeauducq wrote: > What about grounding the FMC pins near the analog signals, would that help? Yes. This is also what the USRP hardware does. And FMC does ground shielding for its regular digital pairs as well. Given that nobody

Re: [ARTIQ] installing ARTIQ

Hey Jonathan, On Wed, Mar 16, 2016 at 4:55 AM, Jonathan Mizrahi wrote: > What do you think is the fastest way to get to the point of controlling the > KC705 board? You should be able to use both ISE or Vivado to flash the three images to the KC705 flash. Robert.

Re: [ARTIQ] [RFC] timeline behavior of coredevice API kernels

On Fri, Mar 4, 2016 at 4:00 AM, Slichter, Daniel H. (Fed) wrote: > I think SPI writes should occur in the "past" and SPI reads should occur in > the "future". This is based on the notion that the time you care about (and > the one which is simplest to think about)

Re: [ARTIQ] turning experiment docks into MDI windows

On Mon, Feb 15, 2016 at 1:43 PM, Sébastien Bourdeauducq wrote: > what would you think about making the ARTIQ GUI look like this, with the > experiment argument editors replacing the *.ui files: >

[ARTIQ] [API change] flash storage moved

Hello, the flash storage area has moved as of 0.1+793.g9fb5ef4 and later. Users of the flash storage area (e.g. IP address on kc705 and idle kernel on any device) need to flash the new runtime and then re-write the desired data. This change became necessary since the runtime size increased to

[ARTIQ] [API change] artiq namespace for experiments

Hello, if you previously did "from artiq import *" at the top of your code, you now should do "from artiq.experiment import *". Something like this should rewrite your code in-place (or use your editor): perl -i -pe 's/^from artiq import \*$/from artiq.experiment import */'

Re: [ARTIQ] linked XY/histogram plot

On Mon, Dec 28, 2015 at 4:15 AM, Sebastien Bourdeauducq wrote: > please provide feedback on the attached prototype of a linked XY/histogram > plotting applet. Looks good to me. > It is currently stand-alone and the data is hardcoded. Data supplied > consists of three arrays, all

Re: [ARTIQ] API for kernel-CPU to add data to RTIO debug traces

On Fri, Dec 11, 2015 at 1:22 AM, Peter Zotov wrote: >> I could do a lot with a single 2x32 bit channel and would interpret it >> as key-value for debugging. > > This sounds fairly user-hostile, what about using arbitrary ARTIQ Python > objects for keys and values? They're

Re: [ARTIQ] API for kernel-CPU to add data to RTIO debug traces

On Fri, Dec 11, 2015 at 1:49 AM, Sebastien Bourdeauducq <s...@m-labs.hk> wrote: > On Friday, December 11, 2015 04:41 PM, Robert Jördens wrote: >> Also, timestamps should include both values, the software time pointer >> and the actual rtio couter. > > The VCD f

Re: [ARTIQ] API for kernel-CPU to add data to RTIO debug traces

On Thu, Dec 10, 2015 at 11:39 PM, Sebastien Bourdeauducq <s...@m-labs.hk> wrote: > On Friday, December 11, 2015 01:27 PM, Robert Jördens wrote: >> >> The same type of data going over the RTIO channels is sufficient: >> integers. > > So, 32-bit integers? How

Re: [ARTIQ] changing "experiment" terminology

On Fri, Dec 11, 2015 at 1:37 AM, Sebastien Bourdeauducq wrote: > On Friday, December 11, 2015 04:36 PM, Sebastien Bourdeauducq wrote: >> My thinking is that the word "experiment" evokes something more advanced > Or more precisely: something that produces science results directly.

Re: [ARTIQ] API for kernel-CPU to add data to RTIO debug traces

On Thu, Dec 10, 2015 at 8:25 PM, Sebastien Bourdeauducq wrote: > the ARTIQ2 specs say: "There is an API for the kernel-cpu to emit data to be > timestamped and added to the buffer". > > What type of data are we talking about? This is in the context of the gateware logic analyzer

Re: [ARTIQ] linked histogram/XY plot

On Thu, Dec 10, 2015 at 8:16 PM, Sebastien Bourdeauducq wrote: > Does anyone need the "linked histogram/XY plot" display? What I was > imagining is: > * there is a N-point scan of the X axis. > * for each point of the scan, a histogram is generated. Each histogram > contains M

Re: [ARTIQ] changing "experiment" terminology

On Thu, Dec 10, 2015 at 8:32 PM, Sebastien Bourdeauducq wrote: > a number of "experiments" used with ARTIQ are actually not experiments at > all: they are small programs that e.g. clear the reference histogram, set > DDS frequencies, configure the rotating wall, etc. > > I think

Re: [ARTIQ] New compiler announcement

Hey Peter, thanks for the now lexer/parser/compiler/transformation chain. I would hope that this is also picked up by similar users like cython, 2to3 etc. On Thu, Dec 10, 2015 at 8:30 AM, Peter Zotov wrote: > * The 'assert' statement has gained much functionality; > in an

Re: [ARTIQ] precisions on GUI features

On Sun, Nov 22, 2015 at 12:57 AM, Sébastien Bourdeauducq <s...@m-labs.hk> wrote: > On 11/21/2015 08:26 AM, Robert Jördens wrote: >> Alternatively, if buttons are really needed, they could become >> part of the arguments of an experiment (e.g. pressing button "foo&quo

Re: [ARTIQ] displays/plotting v2

Hello, On Mon, Nov 23, 2015 at 4:11 AM, Sebastien Bourdeauducq wrote: > * Each display is operated by one subprocess, which displays and manages one > window on the screen. The window gets embedded into a pyqtgraph dock by > artiq_gui. The embedding can be done with XEmbed on

Re: [ARTIQ] ARTIQ shortcuts

Hello, On Tue, Oct 27, 2015 at 4:28 AM, Sébastien Bourdeauducq wrote: > Done. Delete = graceful termination, Shift+Delete = kill. Ack. The idiomatic keybindings are ok by me. Maybe others prefer letter bindings (ctrl-c for kill, ctrl-q for graceful). >> enter: open in explorer?

Re: [ARTIQ] ARTIQ hotkeys

On Sat, Oct 24, 2015 at 1:21 PM, Sébastien Bourdeauducq wrote: > On 10/24/2015 05:38 AM, Britton, Joe wrote: >> * Submit Experiment :: Submit to scheduler new instance of whatever program >> is selected in Explorer. >> * use case is obvious >> * Say, CTRL-S > > Done. Not

Re: [ARTIQ] ARTIQ hotkeys

On Fri, Oct 23, 2015 at 6:56 PM, Sébastien Bourdeauducq wrote: > What exactly should the hotkeys do in ARTIQ, and what are their use cases? > > As I understand, the idea is to assign hotkeys to experiments in the > explorer, and pressing one will run the associated experiment with

Re: [ARTIQ] ARTIQ hotkeys

On Fri, Oct 23, 2015 at 7:18 PM, Sébastien Bourdeauducq wrote: > On 10/24/2015 01:17 AM, Tan, Ting Rei wrote: >> 2. Can be programmed as a 'panic button'. Where this experiment will >> stop whatever that is running and put the system back to a 'safe' >> state. > > How exactly

Re: [ARTIQ] GUI spec.

Hello, On Thu, May 21, 2015 at 7:26 AM, Sébastien Bourdeauducq s...@m-labs.hk wrote: On 05/21/2015 10:48 AM, Robert Jördens wrote: On Tue, May 19, 2015 at 9:48 PM, Sebastien Bourdeauducq s...@m-labs.hk wrote: The description of the fits in this document is problematic. The fits are done

Re: [ARTIQ] GUI spec.

Hello, On Tue, May 19, 2015 at 9:48 PM, Sebastien Bourdeauducq s...@m-labs.hk wrote: The description of the fits in this document is problematic. The fits are done in the analyze() method of the experiments, running on the master and possibly updating the parameter database, independently of

Re: [ARTIQ] AD9914 programming details

On Wed, May 20, 2015 at 9:38 PM, Sebastien Bourdeauducq s...@m-labs.hk wrote: On the QC1 hardware, there is no possibility to send a common FUD. When programming several DDSes in a batch, the core device will issue tight programming+FUD sequences and compensate each POW for the dispersion in

Re: [ARTIQ] AD9914 programming details

On Tue, May 19, 2015 at 10:49 AM, Slichter, Daniel H. daniel.slich...@nist.gov wrote: The new DDS chips (AD9914) normally operate with a 32-bit FTW, which gives them 0.8 Hz resolution in frequency with a 3.5 GHz clock. The chip is capable of operating in a special mode called programmable

Re: [ARTIQ] Pipistrello build process

On Thu, Apr 16, 2015 at 4:14 PM, Robert Jördens jord...@gmail.com wrote: On Thu, Apr 16, 2015 at 3:13 PM, Zach Smith iamsparti...@gmail.com wrote: OSError: libLLVMObjCARCOpts.so: cannot open shared object file: No such file or directory At this point, I feel like it is probably either of 1

Re: [ARTIQ] Pipistrello build process

On Thu, Apr 16, 2015 at 3:13 PM, Zach Smith iamsparti...@gmail.com wrote: OSError: libLLVMObjCARCOpts.so: cannot open shared object file: No such file or directory At this point, I feel like it is probably either of 1) A missing flag to the llvmlite setup.py 2) A missing flag during the

Re: [ARTIQ] Pipistrello build process

On Tue, Apr 14, 2015 at 5:36 PM, Robert Jördens jord...@gmail.com wrote: I'll send the bitstream later. http://www.phys.ethz.ch/~robertjo/bscan_spi_lx45_csg324.bit -- Robert Jordens. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo

Re: [ARTIQ] Pipistrello build process

On Tue, Apr 14, 2015 at 4:00 PM, Neal Pisenti npise...@umd.edu wrote: We're trying to get ARTIQ up and running on a Pipistrello board here at the JQI, but are running into a few issues. The getting started documentation seems to work fine, up to the point we want to build flash the

Re: [ARTIQ] shallow parameter histories

Hello, On Thu, Mar 19, 2015 at 11:38 AM, Sebastien Bourdeauducq s...@m-labs.hk wrote: Hi, On Wednesday, March 18, 2015 09:22 PM, Joe Britton wrote: Ok. How deep should the history be, and what is the algorithm that takes the history and outputs the expected mass at a given time? Does

Re: [ARTIQ] ARTIQ future details

On Fri, Mar 6, 2015 at 10:08 AM, Gaebler, John john.gaeb...@nist.gov wrote: I would keep the duty cycle stuff simple for now. The first thing would be a program that could analyze an Artiq experiment and print out the duty cycles of any of the ttl lines (or combinations of the ttl lines).

Re: [ARTIQ] artiq future

On Mon, Mar 9, 2015 at 7:37 AM, Sebastien Bourdeauducq s...@m-labs.hk wrote: thank you, we will send you those estimates shortly. (Cc'ing list) One item we forgot is the handling of worker timeouts (e.g. if the experiments goes into an infinite loop). I would propose a watchdog context

Re: [ARTIQ] Thorlabs TPZ001 get_output_lut

Hello Yann, On Thu, Mar 5, 2015 at 6:45 AM, Yann Sionneau y...@m-labs.hk wrote: I have some question about Thorlabs TPZ001 API. 1°) Do you use the read-back function of the Waveform Generator Mode (WMG) LUT? (command MGMSG_PZ_REQ_OUTPUTLUT)? 2°) If so, how does it work? I am not aware of

Re: [ARTIQ] handling device disconnections and controller freezes

On Tue, Feb 17, 2015 at 3:47 AM, Sebastien Bourdeauducq s...@m-labs.hk wrote: On Tuesday, February 17, 2015 12:57 AM, Robert Jördens wrote: Since we don't know how expensive it is to attempt to start a controller that is a bit naive. There could be calibration/license stuff loaded over

Re: [ARTIQ] Installing and trying ARTIQ is now easier

On Fri, Feb 13, 2015 at 9:33 AM, Yann Sionneau y...@m-labs.hk wrote: ARTIQ is now easier to install and to try [0] (Is ARTIQ right for my lab?) as we now distribute is as a Conda [1] packages [2][3] which allow to install the host-side ARTIQ software on Linux and Windows in just 3 quick steps

Re: [ARTIQ] [ionstorage] hardware design proposal for ARTIQ DDS/TTL system

On Mon, Feb 9, 2015 at 2:17 PM, Slichter, Daniel H. daniel.slich...@nist.gov wrote: However, I don't have the time to design a nice solution, something like a rack-mounted chassis with slots for DDS cards, and there is also then the issue of getting signals from the FPGA card to the chassis.

Re: [ARTIQ] controller management

Hello, On Sun, Jan 4, 2015 at 2:29 AM, Sébastien Bourdeauducq s...@m-labs.hk wrote: On 01/03/2015 10:51 AM, Robert Jördens wrote: How does the master depend on the controllers? Upon startup, the master immediately attempts to run an experiment, which typically requires controllers. Ack

Re: [ARTIQ] logging in controllers

On Wed, Jan 28, 2015 at 6:56 AM, Yann Sionneau y...@m-labs.hk wrote: Was that the idea you had in mind? I've put the loglevel.py containing the factorized code in artiq.frontend but I guess it must go somewhere else, except that I'm not sure what location would be the best. If this is OK

Re: [ARTIQ] controller management

Hello, On Tue, Dec 23, 2014 at 4:32 PM, Sébastien Bourdeauducq s...@m-labs.hk wrote: On 12/20/2014 06:11 AM, Robert Jördens wrote: My idea is to keep a list of controllers to run on each machine, with parameters such as the TCP port, the type of controller, and the device serial number

Re: [ARTIQ] controller management

On Wed, Dec 17, 2014 at 11:05 AM, Slichter, Daniel H. daniel.slich...@nist.gov wrote: I think we will want the ability to have controllers on Windows. For better or for worse, there will likely be majority Windows 7 computers in the lab, and there may well be various hardware devices we

Re: [ARTIQ] November 2014 status report

Hello Sebastien, thanks for the report. * JSON/PYON: As mentioned on IRC, you could still have used JSON with a bit of type annotation. The other arguments against JSON appear to only count if you want to build a fully bijective python data (de)serializer wich may not be needed. The reason why

[ARTIQ] Fwd: TTL/DDS breakout meeting report

-- Forwarded message -- From: Robert Jördens jord...@gmail.com Date: Wed, Oct 29, 2014 at 11:01 PM Subject: Re: [ARTIQ] TTL/DDS breakout meeting report To: Slichter, Daniel H. daniel.slich...@nist.gov On Wed, Oct 29, 2014 at 1:29 PM, Slichter, Daniel H. daniel.slich...@nist.gov