I've commented before that OPCODE table contain all the assembler mnemonics
available when that OPCODE table was introduced to HLASM, it is not the list of
instructions available at that Z?? machine. So IILF instruction was introduced
with z9 hardware But the LFI extended mnemonic was added to
I remember (a long time ago) we had "first time" code preceded by a NOP, which
altered the NOP condition code to branch around the "first time" code on
subsequent invocations.
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Abe Kornelis
Sent:
Assuming you have an assembly listing, you just need to look at the "R-Loc"
(i.e. offset) value.
We use two LOCTR's for data, one for data that needs to be within 4K of the
base register, and another for data referenced with relative long, or long
displacement instructions. That single base
When I first saw "Complex immediate fields", I thought of this code one of our
emulation macros used to generate:
CGIJL R01,132-(L'BKwa_Module+1+L'BK_LPAOS+1),BK250
+ CGHI R01,(1-132-(L'BKwa_Module+1+L'BK_LPAOS+1))-((132-(L'X
+
That fails with an arithmetic overflow if the byte value has the high order bit
set.
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Charles Mills
Sent: Friday, March 29, 2024 14:27
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Complex
For comparing instructions available by hardware generation, that doesn't work.
OPTABLE(Zn) does not give you the instructions available for the Zn hardware.
It gives you the assembler mnemonics available in HLASM when support for the Zn
series hardware was added to HLASM.
So LFI is an
We're only at 2022-04, I'll have to get our level of HLASM updated.
Thanks,
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Jonathan Scott
Sent: Tuesday, December 19, 2023 12:42
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Macro variable
Prior to this APAR, I was forced to do the SETA against the equate before the
macro call and then pass the resolved value into the macro i.e.
SETA equ_name
MacroName LEN=
The ability to do the SETA inside the macro really simplifies our code, but
it's implementation seem to be
For values of "several" up to 16, you might want to look at VFAE.
I haven't had a chance to use it yet, but it's on my list of vector
instructions potentially useful for general coding.
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Paul
Oops, didn't notice the "code is executing in getmained area" part. Doesn't
that cause performance issues with Instruction/Data caches though?
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Ngan, Robert (DXC Luxoft)
Sent: Wednesd
al Message-
From: IBM Mainframe Assembler List On Behalf
Of Ngan, Robert (DXC Luxoft)
Sent: Tuesday, June 7, 2022 6:44 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: MVCRL
If the source is relative to the instruction address, the code would most like
be non-reentrant.
Robert Ngan
If the source is relative to the instruction address, the code would most like
be non-reentrant.
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Schmitt, Michael
Sent: Tuesday, June 7, 2022 17:29
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject:
Of Paul Gilmartin
Sent: Thursday, May 19, 2022 14:49
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Quadword constant
On May 19, 2022, at 12:16:45, Ngan, Robert (DXC Luxoft) wrote:
>
> FD is a fixed point doubleword.
>
Alas, there's no way to define a doubleword constant containing
FD is a fixed point doubleword.
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Schmitt, Michael
Sent: Thursday, May 19, 2022 13:09
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Quadword constant
Today I learned that there isn't a fixed
STRL/STGRLl?
Is the GCC compiler generating non-reentrant code?
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Ian Worthington
Sent: Thursday, April 14, 2022 08:05
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Signed/unsigned operations
I
Hmmm, you mention "speculative execution". Maybe that make it vulnerable to
meltdown/spectre type attacks.
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Dan Greiner
Sent: Wednesday, April 6, 2022 17:47
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Removal of
code using the transactional execution facility might feel
kinda "had" now...
Mike Shaw
MVS/QuickRef Support Group
Chicago-Soft, Ltd.
On Wed, Apr 6, 2022 at 4:17 PM Ngan, Robert (DXC Luxoft) < robert.n...@dxc.com>
wrote:
> In the Statement of general direction in t
In the Statement of general direction in the z16 announcement at:
https://www.ibm.com/common/ssi/ShowDoc.wss?docURL=/common/ssi/rep_ca/1/897/ENUS122-001/index.html
It says IBM will remove support for the transactional execution facility, I
guess there's no point in attempting to exploit this
Not much in the way of details, but information on new z16 instructions that
might be of interest to members of this list:
https://www.phoronix.com/scan.php?page=news_item=IBM-Z-Arch14-GCC
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Dan
We have a similar issue when following pointer chains that could have be
corrupted.
If you're only reading the storage, I think transactionalizing the code with
TBEGIN/TEND will do this for you. If the transaction is successful, you have
access, if it's not you don't.
Don't know if this
What IBM told us (sometime last century) is that when you get a CC=3 and you
really want to know more, you establish a recovery routine, reference the
storage (with a CLI or something similar) and then (after cleanup) re-issue the
TPROT.
Robert Ngan
DXC Luxoft
-Original Message-
From:
Before the advent of the COMPARE AND TRAP type instructions, we all use to use
EX Rnn,* to force a S0C3 abend for "this should never happen" conditions.
But with baseless code, if you change EX Rnn,* to EXRL Rnn,* then you may not
get your expected S0C3 when Rnn is a register other than zero.
I originally just coded the obvious VUPKZ/MVI/TR like a UNPK/MVI/TR or
UNPKA/MVI/TR instruction sequence, but found the performance was within 10% for
all three variations. It looks like most of the time is spent in the TR
instruction. So, we need to eliminate the TR, and I came up with two
This is just a LG, just like L for 32-bits. It doesn't matter whether it's
signed or unsigned. There's nowhere for a sign to be extended.
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Dave Clark
Sent: Tuesday, February 1, 2022 10:39
To:
Basically, yes. Some instructions always use all 64-bis of the register.
However others, like LA are addressing mode sensitive.
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Dave Clark
Sent: Wednesday, January 19, 2022 12:45
To:
Assuming you eventually want the value to be in character format, the COBOL
compiler doc says that with the appropriate ARCH() level, it'll generate DFP
instructions to do this instead of using CVD/UNPK so I assume DFP is faster,
and you can use:
CDLFTR FP00,0,R02,0 Convert
Under "Saving the caller program's registers", the assembler services guide
states:
Vector registers (VRs) 8 - 15, bytes 0 - 7, and the entirety of VRs 16 - 23 are
unchanged.
16-23 only! Not 16-31. Is this correct?
Robert Ngan
DXC Luxoft
As per the FPR usage thread, you could also save GR(s) to FP registers 0 thru 7.
Robert
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Charles Mills
Sent: Monday, November 29, 2021 18:03
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Base-less macros
I did not
, November 29, 2021 14:01
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Base-less macros
On Nov 29, 2021, at 12:41:51, Ngan, Robert (DXC Luxoft) wrote:
>
> DON'T DO THAT!
> I had to find/redo all our code that did this when our subroutine return
> logic was changed to use a BIC
DON'T DO THAT!
I had to find/redo all our code that did this when our subroutine return logic
was changed to use a BIC instruction.
Robert
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Steve Smith
Sent: Thursday, November 25, 2021 13:49
To:
We got rid of all of this form of branch tables way back when, after IBM added
a new RC for the OPEN macro (i.e. 16 for RLS), and our code jumped beyond the
branch table into the RC=0 code!
Robert
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Steve Smith
Sent:
: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of Ngan, Robert (DXC Luxoft)
Sent: Tuesday, November 23, 2021 11:40 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: ASMA030E?
Why can't I code:
DCA(=C'blah')
This give an ASMA030E error, but wanting
: ASMA030E?
On Nov 23, 2021, at 14:14:44, Ngan, Robert (DXC Luxoft) wrote:
>
> That complicates my code, where I wanted to do this to generate table
> entries. Now I need a separate named field for each generated table entry!
>
Would a MACRO using LOCTR and simplify it?
> -O
14:31
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: ASMA030E?
On Nov 23, 2021, at 12:40:13, Ngan, Robert (DXC Luxoft) wrote:
>
> Why can't I code:
>
> DCA(=C'blah')
>
> This give an ASMA030E error, but wanting the address of a literal string
> seems legiti
Oops, I didn't notice Pieter's response.
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Ngan, Robert (DXC Luxoft)
Sent: Tuesday, November 23, 2021 13:44
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Base-less macros
Or even simpler:
CLIJE
Or even simpler:
CLIJE R15,0,RC0ROUTINE
CLIJE R15,4,RC4ROUTINE
CLIJE R15,8,RC8ROUTINE
CLIJE R15,12,RC12ROUTINE
J UnexpectedRC
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Pieter Wiid
Sent: Tuesday, November 23, 2021 12:29
To:
Why can't I code:
DCA(=C'blah')
This give an ASMA030E error, but wanting the address of a literal string seems
legitimate to me as I don't otherwise need a named field with this value.
Robert Ngan
DXC Luxoft
I suggested the "omitted uses implied length" syntax since RISBG etc.
instructions already have "omitted implies zero" for the fifth operand.
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Jonathan Scott
Sent: Friday, October 1, 2021 03:21
One use case:
It has been mentioned here that EXECUTE'd instructions are expensive.
So for variable length MVCs up to 16 bytes, an executed MVC could be replaced
by VLL/VSTL.
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Ngan, Robert (DXC
Thank you Dan,
This is a lot easier to understand than what's in the Principles of Operations.
I've only gotten thru to Chapter 21 and I've already found three cases where I
can use vector instructions in our code.
One nit (nothing to do with your Powerpoints), the third VPKZ/VUPKZ operand
Thanks,
I'll try AINSERT. For my current use case, this limitation is acceptable.
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Jonathan Scott
Sent: Thursday, September 30, 2021 08:17
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: How can I
invoke an arbitrary macro with arbitrary KEYWORD
parameters?
Robert,
IIRC (I hope so) I got it to work with all parms concatenated into a single
variable.
You might give it a try ...
Success!
Abe
===
Op 30/09/2021 om 01:10 schreef Ngan, Robert (DXC Luxoft):
> I’m trying to invoke a ma
I’m trying to invoke a macro specifying keyword parameters within another
macro, where the keyword and its value were passed to the outer macro. However,
the assembler is always interpreting keyword=value as a SYSLIST value.
Anyone know how this can be done, or even if it is possible?
The code
Or: DC 0F
Robert Ngan
HCL Technologies
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Paul Gilmartin
Sent: Friday, April 30, 2021 19:48
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Ensuring LRL 2nd operand alignment
On 2021-04-30, at 16:17:06, Charles Mills
I found out the hard way that, if you code EXECUTABLE=YES of the STORAGE
OBTAIN, you must also code it on the associated STORAGE RELEASE.
Evidently, it's implemented as a subpool under the covers, so like subpool
getmains, you must have matching values on OBTAIN and RELEASE.
Robert Ngan
HCL
SA22-7832-15???
The latest version I have is SA22-7832-12, and I've been looking for
SA22-7832-13 since the z15 T02 was GA'd last month with 30 new instructions.
Has anyone seen the POPS for the z15 T02?
Robert Ngan
HCL Technologies (USA)
-Original Message-
From: IBM Mainframe Assembler
You can specify GR's via:
R0 EQU 0,8,,,GR
HLASM also supports a bunch of other register types.
However when you do this, use of non-register equates (i.e. by CICS macros)
gets flagged by the assembler.
Robert Ngan
-Original Message-
From: IBM Mainframe Assembler List On
We use TWO LOCTR's, one for constants required to be within 4K of the base
register and a second for constants only referenced by relative long or long
displacement instructions. Useful when your combined constants size exceeds 4K
as it moves the "yonder" fields out of the 4K space.
I wish
ughkeepsie NY
"IBM Mainframe Assembler List" wrote on
10/31/2019 01:30:13 PM:
> From: "Ngan, Robert"
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Date: 11/01/2019 11:36 AM
> Subject: Vector enablement control?
> Sent by: "IBM Mainframe Assembler List"
Thanks, exactly what I wanted to know.
Robert Ngan
HCL Technologies
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Peter Relson
Sent: Friday, November 1, 2019 06:49
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Vector enablement control?
If you're running z/OS
With the new COBOL compilers capable of generating vector instructions for
handling packed fields, I'm looking at modifying our ESTAE routines to dump the
contents of the vector registers.
The PoOPs says you should not issue a vector instruction unless both the vector
enablement control and
question
> On Jun 26, 2019, at 3:15 PM, Ngan, Robert wrote:
>
> Or use AD when the value is an expression.
>
… but not a 64-bit expression. If the value is negative, will it sign-extend?
— gil
DXC Technology Company - Headquarters: 1775 Tysons Boulevard, Tysons, Virginia
221
Or use AD when the value is an expression.
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Charles Mills
Sent: Tuesday, June 25, 2019 20:23
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: ltorg question
DS D defines a floating point field. 4110 is a
O' does not need to used within a macro, nor with SETC symbols or parameters.
We use it in open code (at the top of a module) to determine whether a specific
macro is available in the SYSLIB concatenation. Very useful in determining
whether optional features should be enabled, based on the
a doubleword boundary?
Keven
On Mon, Jan 14, 2019 at 4:17 PM -0600, "Ngan, Robert" wrote:
Protection for readers is only necessary when the storage in question is larger
than a doubleword.
For quadwords, you can use either LPQ or PLO
Protection for readers is only necessary when the storage in question is larger
than a doubleword.
For quadwords, you can use either LPQ or PLO function 3 (CLX).
Robert Ngan
HCL Technologies
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Joe Owens
Sent: Thursday,
I'm so use to splitting the name after the 3rd character I did not even notice
this, until one of our younger programmers pronounced it as "I EAT DUMP"
Robert Ngan
HCL Technologies
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Jim Mulder
Sent: Sunday, August 26,
Hmm, didn't think of using CRTE etc, since I was fixated on CLFITxx
instructions. The immediate value is a halfword, so you can code a lot more
variations of the CLFIT instruction to uniquely identify which specific
instance produced the S0C7.
Robert Ngan
HCL
P.S. I always seem to code the
Not sure why no one has mentioned the COMPARE AND TRAP type instructions, in
most(?) cases they'll do the test and force the abend when required.
My only gripe is there's no extended mnemonic for an unconditional TRAP when
there's no appropriate "compare" (e.g. I need to do a TM).
I had to code
00:14:46 +
>From: "Ngan, Robert" <rn...@dxc.com>
>Subject: LOC=64 executable code?
>Just noticed that the z/OS 2.3 manuals mention EXECUTABLE=YES|NO parameter for
>IARV64 GETSTOR requests.
>Anyone have a summary of what kinds of code we can move above th
Just noticed that the z/OS 2.3 manuals mention EXECUTABLE=YES|NO parameter for
IARV64 GETSTOR requests.
Anyone have a summary of what kinds of code we can move above the bar in z/OS
2.3?
Robert Ngan
CeleritiFinTech Services
DXC Technology Company - Headquarters: 1775 Tysons Boulevard, Tysons,
When using multiple EX instructions within a program to generate S0C3's, I'd
use different registers to differentiate the S0C3's.
However, with EXRL, if you use a non-zero register, and it modifies the
low-order nybble, the target instruction in no longer a EXRL!
Robert Ngan
CeleritiFinTech
Hmm,
Looks like we don't have PI34981 on either our z/OS 2.1 or 2.2 systems, will
have to have a tale with our sysprogs.
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Peter Relson
Sent: Saturday, March 25, 2017 13:16
To:
My "favorite" is the warning you get when the target of your JAS/BRAS shifts to
an offset more that 64K from the instruction. You only get a ASMA320W warning
(when would this not be an error?), and at execution time the truncated
immediate offset branches you to some arbitrary address!
Thank
I looked into it, but we don't have the appropriate h/w so I can't play with it
yet.
The unconstrained version may always fail, so you need to always create a
non-transactional version of the code just in case (so this doubles your coding
effort).
The only immediate use I could think of for
The " Compare and swap and double store" function of PLO?
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of John McKown
Sent: Thursday, March 02, 2017 15:32
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Transactional Execution -
frame Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Paul Gilmartin
Sent: Wednesday, March 01, 2017 20:40
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: HLASM anomaly
On 2017-03-01, at 17:35, Ngan, Robert wrote:
> I noticed the new COBOL compiler was generating:
>
>
I noticed the new COBOL compiler was generating:
MVHHI target,0
MVHHI target+2,48000
instead of:
MVC target,=F'48000'
and I thought I'd look into using 2 MVHHI's instead of a MVC with a literal
even when the top half of the value is non-zero. The assembler happily accepts:
MVHHI
2010?
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Steve Thompson
Sent: Thursday, October 06, 2016 07:40
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Test of List
The last email I've gotten from the list was 10JUN2010.
Is
Hmm, there's always something new to learn with the assembler. I've never
encountered the boundary and offset operands of ORG. That's useful to know for
future coding.
The only thing that ORG doesn't do vs. DC is emit the potential filler byte.
Is uninitialized csect/rsect storage still an
: Friday puzzle: CNOP 1,2
From: "Ngan, Robert" <rn...@csc.com>
Sent: Saturday, August 20, 2016 4:47 AM
I'm writing a macro to build length prefixed character strings. The length is
one byte, and the actual string is referenced by LARL so it needs to be
halfword aligned.
So I c
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Friday puzzle: CNOP 1,2
On 2016-08-19 16:01, Ngan, Robert wrote:
> I wanted the length aligned on the odd byte, so the immediately following
> (labeled) string was on a halfword boundary and could therefore be referenced
> using a LARL.
&g
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Tony Harminc
Sent: Friday, August 19, 2016 15:31
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Friday puzzle: CNOP 1,2
On 19 August 2016 at 14:47, Ngan, Robert <rn...@csc.com> wrote:
> I'm writing a macro to build length prefixed characte
I'm writing a macro to build length prefixed character strings. The length is
one byte, and the actual string is referenced by LARL so it needs to be
halfword aligned.
So I coded (what would be a CNOP 1,2 - if it was valid):
DC(1-(*-)/2)X'00' Simulate a CNOP 1,2
However, this
For non-relocatable values, the range of Y values is the same as a signed
halfword.
In my case, I want unsigned values so I can't use Y.
I ended up coding:
DCAL2(expr)
DS0XL(65536-expr) ASSERT: expr was not truncated
-Original Message-
From: IBM Mainframe
I had a program that was generating a (non-relocatable) value larger than 65535
within an AL2 constant, and it's being silently truncated.
A (brief) look at the manuals did not reveal any options for flagging this type
of error. Did I miss something, or is there no way to flag this condition?
Would PRINT OFF suppress error messages too?
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of John Ehrman
Sent: Thursday, February 11, 2016 17:49
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Return code 8 from assembler no
IILF with an immediate value less than 65536 does what you want, and would be
my choice.
Robert Ngan
CeleritiFinTech
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of John P. Hartmann
Sent: Wednesday, January 20, 2016 1:54 PM
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