[coreboot] Does coreboot table still exist in F000 segment?

Hi, all Beside placing coreboot table (lb_header) in low RAM (0x0-0x1000), I remember a copy of coreboot table should be placed at F000 segment and it can be controlled with a Kconfig flag, does this feature still exist? I just can't find it right now. -Fei -- coreboot mailing list:

Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works

I can confirm coreboot has no issue to support 64 bit UEFI payload, it's already verified. Can you please provide more information of your coreboot/payload? Like, coreboot revision/commit ID, payload revision/commid ID, FSP revision, platform details (CRB or OEM platform) etc. On Thu, Sep 21,

Re: [coreboot] How to change config of SDRAM of intel mohonpeak EVB on coreboot?

YuSeok, It looks your platform has enabled the Memory Down function. The MEM_DOWN_DIMM_SPD_DATA structure supposed to be filled with the relative DIMM SPD data as described in comments, for example, DRAMDeviceType =>>> SPD Byte Offset 2 ModuleType =>>> SPD Byte offset 3 DramManufacturerIdLsb

Re: [coreboot] How can extract descriptor.bin from bios image?

Looking at the logs you've got, the final bios only have BIOS/coreboot and descriptor.bin, the GbE/ME areas are not used, I think as long as your enable the descripor.bin, it should be good enough. poplinux@raw rangeley $ > ./tools/ifdtool -x ./oem_dumped.bin File ./oem_dumped.bin is 8388608

Re: [coreboot] The GbE is not activated on my Board.

Here is a sample, Please select INCLUDE_ME to y and set ME_PATH to point to your descriptor.bin (Path/descriptor.bin, refer to FSP_FILE as a sample). On Mon, Jun 20, 2016 at 10:48 PM, WANG FEI <wangfei.ji...@gmail.com> wrote: > YuSeok, how did you attach the descriptor.bin to your core

Re: [coreboot] bootfail on my Mohon Peak CRB.

gt; > You must write start address is 0x00000000(offset 0MByte) > > > This time, coreboot work is very fine. > > Thank you. > > 2016-02-04 오후 11:02에 WANG FEI 이(가) 쓴 글: > > *RANGELEY_POSTGOLD4_FSP_004_20150924.fd is the FSP binary, you can rename > it to FvFsp.bin and

Re: [coreboot] Question about Intel's documentation notations

xxH - xx means these two numbers could be a hex number from 00 - FF, which is depend on the SoC/processors. On Mon, May 9, 2016 at 4:25 PM, Rafael Machado < rafaelrodrigues.mach...@gmail.com> wrote: > Make sense. Now I saw the notes. Stupid question, sorry. > > That about the *xx*H ? > > Thanks

Re: [coreboot] A talk about coreboot

Wow, Iru, it's a great presentation, I bet you have spent quite a lot time to make it happen. I'm excited more contributors from China too, I noticed some Chinese companies have deployed coreboot/FSP on their platform in recent years, I would like to encourage them involving in the coreboot

Re: [coreboot] bootfail on my Mohon Peak CRB.

configuration of your board, if it's wrong, you definitely will not have any output on serial console. On Thu, Feb 4, 2016 at 2:02 PM, WANG FEI <wangfei.ji...@gmail.com> wrote: > *RANGELEY_POSTGOLD4_FSP_004_20150924.fd is the FSP binary, you can rename > it to FvFsp.bin and placed it

Re: [coreboot] bootfail on my Mohon Peak CRB.

*RANGELEY_POSTGOLD4_FSP_004_20150924.fd is the FSP binary, you can rename it to FvFsp.bin and placed it to the path defined in coreboot, ie, * `../intel/fsp/rangeley/Fv*, to generate coreboot image.* On Thu, Feb 4, 2016 at 5:19 AM, 김유석 wrote: > Dear Martin. > > Thank's your

Re: [coreboot] bootfail on my Mohon Peak CRB.

Mohon Peak coreboot can only power on your system with a Rangeley SoC FSP included in your coreboot. Please download the Rangeley FSP binary from http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html , *Intel® Atom™ processor C2000

Re: [coreboot] noob question

can you share the coreboot serial log with community? I used to have a splash on my system, sometime I have to use a new splash file if the original one does not show up correctly. On Mon, Aug 10, 2015 at 1:04 PM, Johan S johan...@yahoo.fr wrote: Hi there, i m trying to understand few

Re: [coreboot] How to check if DRAM init is OK?

How about MemTest86? See this link http://www.coreboot.org/Memtest86, I never use it before. On Tue, Aug 4, 2015 at 6:16 AM, Iru Cai mytbk920...@gmail.com wrote: Hi, I'm now porting coreboot to CubieTruck, a development board with an Allwinner A20 SoC. I use Mr.Nuke's code[1] and

Re: [coreboot] minnowboardmax coreboot intel uefi payload :Failed to find the required acpi table

My understanding is that your coreboot does not have ACPI table, you possible 1) add ACPI support in coreboot, or 2) modify UEFI payload to remove the assert if ACPI table not exist, or 3) trying the latest coreboot package from edk2 source tree. On Tue, Jul 7, 2015 at 2:58 AM, DM365

Re: [coreboot] How to build SPI ROM 8MB image

Update BOARD_ROMSIZE_KB_2048 in src\mainboard\intel\bayleybay_fsp\Kconfig to BOARD_ROMSIZE_KB_8192, re-generate .config and make sure .config the ROM size is 8MB, now you can run make to generate 8MB ROM. On Tue, Jul 7, 2015 at 10:32 AM, Cao Duc Quan caoducq...@gmail.com wrote: Dear all, I am

Re: [coreboot] ACPI resource problem

Siyuan, did you reserved 0xFEDC2000 - 0xFEDC2FFF in ASL file? what you've done in your code is to reserve this MMIO area in E820 table, OS will not take this area, but it's not enough for ACPI. Here is a sample to reserve MMIO area in asl file. // TPM Area (0xfed4-0xfed44fff) DWordMemory

Re: [coreboot] Using SeaBIOS as coreboot paylod fail

Yu-Cheng, looking through the log and just have two suggestions here. 1. It mentions the payload size is 0xc5a5, is it too small for a payload? My understanding is that something wrong in payload compressing, please set CONFIG_COMPRESSED_PAYLOAD_LZMA to N and try again, I remember I saw similar

[coreboot] How to assign a fixed resource to PCI BAR?

Hi, coreboot folks, I'm trying to assign a fixed resource to a specific PCI BAR, does any know how to do it? Also is there a switch to change the PCI enumeration order? for example, PCI devices enumerate from high device number to low device number? Thanks. -- coreboot mailing list:

Re: [coreboot] Question on VGA BIOS extraction

TP X220 suppose to have a UEFI compatible BIOS, is it possible it has a UEFI DXE VGA driver (not sure what's the proper name of it) except a legacy video? Maybe you should boot up system with original BIOS and check the content in 0xC000 segment, is it a legacy VBIOS or it's empty... On Mon, Mar

Re: [coreboot] 0xE0000/0xF0000 segment issue

I'm curious why your seabios payload is loading to shadow RAM (C/D/E/F000 segment), this area suppose to be used by seabios, I guess since seabios is a legacy BIOS. My suggestion is to load your seabios to a over 1MB address. On Thu, Mar 19, 2015 at 2:38 PM, Naresh G. Solanki

Re: [coreboot] VGA doesn't work on Mohon Peak

Viktor, I've messed around VGA function on my platform before, I got the problem to display seabios messages on VGA as well, finally I fed up and enabled the bootsplash in coreboot instead, as along as the coreboot splash can be shown on monitor, which proves the VGA function works, it's what I

Re: [coreboot] [Intel Atom C2000 Rangeley] SPI Descriptor issue related to coreboot

Guo Jia, It's not easy to figure out the problem in your case, it would be great if you can have an ITP hooked on your system to debug coreboot instead of guessing. I'm glad you've tried to dump descriptor bin from ADI's binary, but I remember even without descriptor binary, Mohon Peak platform

Re: [coreboot] grub2 as SeaBIOS payload

I bet the solution you mentioned is to build GRUB2 as the payload of coreboot instead of seabios. Seabios is a legacy bios and support legacy boot, it possible can not load grub2.elf. Please correct me if I'm wrong. I think memdisk is only a blank disk with grub.cfg and can be created with Linux

Re: [coreboot] SeaBIOS, serial output, grub, sgabios does not seem to load

Kuzmichev, Changing the seabios serial port base address, you should modify it via make menuconfig command, it's much easy and efficiency. It's not recommended to modify the actual source files. -Fei On Tue, Jan 13, 2015 at 3:33 AM, Martin Roth gauml...@gmail.com wrote: Hi Viktor, Yes, I

Re: [coreboot] [SOLVED] Internal Ethernet controller on Mohon Peak CRB failed to get activated

Patrick, It's great to know the issue has been solved with my suggestion. Thanks your update. -Fei On Wed, Jan 7, 2015 at 4:21 PM, Patrick Agrain patrick.agr...@alcatel-lucent.com wrote: Hello, This issue is solved. Fei, your tip concerning the Intel Firmware Descriptor was good.

Re: [coreboot] No video output with Bay Trail

Fred, as long as the video output in Linux environment, it seems the video controller is configured properly, so maybe something wrong in seabios in configuring video to text mode (I remember seabios will configure video to text mode as default, correct me if I am wrong). I would suggest you

Re: [coreboot] questions about Rangerley

coreboot already supports Intel Mohon Peak platform, I noticed the source code has been committed to coreboot source tree. The mainboard path is coreboot\src\mainboard\intel\mohonpeak. On Fri, Dec 5, 2014 at 5:41 AM, maypar...@163.com maypar...@163.com wrote: Hi Martin, I am kinda have this

Re: [coreboot] WOL/PCI PME wakeup from S3 Baytrail SoC (Bayleybay CRB)

described how to configure the PCI/PCIE devices to wake themselves from PME signals. This job suppose to be done before system sleep(S1/S3/S4/S5). -Fei On Fri, Nov 28, 2014 at 6:42 AM, Gailu Singh gail...@gmail.com wrote: Hi Wang Fei, Thank you very much for your help. I checked the things you

Re: [coreboot] WOL/PCI PME wakeup from S3 Baytrail SoC (Bayleybay CRB)

I remember WOL PME wakeup function need configure 3-4 different areas, 1) SoC ACPI registers: Enable PCIE PME in PM and GPE registers. 2) PCIE Card ACPI register: Yeah, you need set some registers of the PCIE card to allow it waked by packages. 3) Report WOL PME single in ASL _GPE{} with _Lxx

Re: [coreboot] 转发: Coreboot with Intel FSP on BayleyBay Help

Meng Qiaohui, I noticed a file called ChangesRequiredForRambiWinboot.txt in Intel released UEFI package, it can tell you how to modify coreboot/ACPI files to boot Windows 7, you can download the package @ http://uefidk.intel.com/sites/default/files/2014-WW26-UEFI.CoreBoot.Payload.zip, its

Re: [coreboot] Coreboot console_init() doesn't work on Rangeley board?

As I remember, Rangeley FSP is using UART1(0x2F8) as default, can you try to configure UART1 on your platform? On Tue, Sep 16, 2014 at 11:50 PM, Qinqxin Wei q...@infinera.com wrote: Hi, I am managing to replace BIOS with coreboot on a Rangeley evaluation board, but the serial console cannot

Re: [coreboot] Wiki access

I've sent out for Wiki access few days ago, but still have not got any response yet. On Mon, Oct 13, 2014 at 10:50 PM, Nico Huber nic...@gmx.de wrote: Hi, looks like I don't have an account for the coreboot wiki, yet. Well, at least I don't remember, and can't find any stale email... Nico

[coreboot] Can anyone grant me the permission to edit corboot wiki?

I'm planning to update few pages on coreboot.org, do I need specify the page(s) I am going to edit? If so, http://www.coreboot.org/TianoCore. -Fei -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Suggested readings

The most useful boot refer to legacy system I believe: http://www.amazon.com/The-Undocumented-PC-Programmers-Edition/dp/0201479508 Beside Aaron's suggestion of Intel manuals, I also recommend AMD programming manuals,

Re: [coreboot] Lanner 7525 , Intel Atom C2000 Rangeley

Franz, Intel Rangeley SoC and Intel Mohon Peak platform have been supported in coreboot, mainboard directory path is src\mainboard\intel\mohonpeak. You need download coreboot source code and Rangeley FSP binary from

Re: [coreboot] [Heads up] CPU_ADDR_BITS set to 36 bits again on most Intel device

Good news! On Wed, Aug 13, 2014 at 9:48 PM, Paul Menzel paulepan...@users.sourceforge.net wrote: Am Dienstag, den 12.08.2014, 11:01 +0100 schrieb WANG FEI: I noticed this issue before, Kconfig will take default CPU_ADDR_BITS with the value 32 in src\cpu\intel\model_106cx\Kconfig instead

Re: [coreboot] [Heads up] CPU_ADDR_BITS set to 36 bits again on most Intel device (was: [coreboot-gerrit] Patch merged into coreboot/master: a438049 model_106cx: don't blindly set Kconfig settings)

I noticed this issue before, Kconfig will take default CPU_ADDR_BITS with the value 32 in src\cpu\intel\model_106cx\Kconfig instead of the value 36 src\cpu\x86\Kconfig. To avoid this issue, you have to override CPU_ADDR_BITS in your own Kconfig file same as what Baytrail project has done. On

Re: [coreboot] Will an ASUS M5A97 R2.0 work with coreboot?

Tom, I'm not an expert of AMD products, I just have a quick search on the Device IDs in your mail, your platform's southbridge is SB800, which is already supported by coreboot, AMD's processor/northbridge is definitely supported by coreboot, but I dont believe the mainboard is supported by

[coreboot] Something wrong in last week's check-in

coreboot guys, I noticed the source code check-in last week have a problem - modifying some items with make menuconfig, such as bootsplash file, then building with make command, the new bootsplash file will be **NOT** compiled into new coreboot image. I dont notice this issue one week before (I

Re: [coreboot] BayleyBay FSP booting

Tuan, Your platform's northbirdge and GFX device ID is 0x0 and 0x0031? It's definitely wrong, I would suggest you to download the Bayley Bay platform's official UEFI BIOS from Intel IBL and flash it to you Bayley Bay platform, then see what's the correct ID. On Fri, Jul 11, 2014 at 4:36 AM,

Re: [coreboot] sgabios no console output from Seabios (was: coreboot Digest, Vol 113, Issue 17)

to 0x2f8, let us know any difference. -Wang Fei On Mon, Jul 14, 2014 at 9:53 PM, Paul Menzel paulepan...@users.sourceforge.net wrote: Dear Wen, Am Montag, den 14.07.2014, 11:32 -0400 schrieb Wen Wang: Thanks for looking into to it! I pulled the seabios tree and built seabios manually

Re: [coreboot] compiling error with fsp_baytrail's asl code

I'm using IASL 20140214-32, it does report a lot warning, but no errors, it does not cause compiling failed. On Wed, Jun 4, 2014 at 7:31 AM, Mike Hibbett mhibb...@ircona.com wrote: When did that error appear Tank? And what version of the iasl compiler are you using? Mike Sent with

Re: [coreboot] Intel FSP on Bayley Bay CRB: No output

I thought microcode files are kind of patches for CPU, it suppose to be loaded before MRC just in case it fixes any issues related with CPU. I actually did encounter an system random halt issue related with no loading microcode before MRC training. Martin, how do you think to display a warning

Re: [coreboot] [ANNOUNCE] SeaBIOS 1.7.5

XHCI support is what I want, currently what's payload have a better XHCI support? Seabios or U-Boot? On Wed, May 28, 2014 at 3:34 PM, Peter Stuge pe...@stuge.se wrote: Kevin O'Connor wrote: New in this release: * SeaVGABIOS improvements * New driver for coreboot native vga support

Re: [coreboot] Errors in Memtest86 with 4 or 8GB memory

I noticed the MTRR(base:2944MB, range:64MB, type WB ) has covered the TSEG hole(Adding hole at 2992MB-3008MB), I can not remember if this will cause a problem or not. Anyone knows? BTW, what is the value of B0:D0:F0:REG70h? On Tue, May 27, 2014 at 9:30 AM, Krzysztof Pierwieniecki

[coreboot] Is there a proper way to skip a specific PCI device during PCI enumeration

Gents, What I'm doing is to avoid PCI enumeration code allocating/setting/configuring resource to a specific PCI device (Bus:Device:Function), is there a mechanism in coreboot to achieve this? I've achieved this by setting this specific PCI device's read_resources to NULL, just wondering what's

Re: [coreboot] Errors in Memtest86 with 4 or 8GB memory

I guess the errors might related with MTRR/E820 Memory reporting etc. System with 2GB RAM definitely does have a memory allocated to 2990.8MB. I would suggest you uploading the coreboot log and MTRR dump here to review. On Mon, May 26, 2014 at 8:28 AM, Krzysztof Pierwieniecki

[coreboot] Latest coreboot compiling failure on ubuntu 14.04

Hi, all I noticed coreboot compiles failed on my system since the following change committed. *Author: Furquan Shaikh furq...@google.com furq...@google.com 2014-04-23 18:18:48Committer: Furquan Shaikh furq...@google.com furq...@google.com 2014-05-06 19:23:31Parent:

Re: [coreboot] Compling error in ubuntu 14.04

Many thanks. On Fri, May 9, 2014 at 12:41 AM, Furquan Shaikh furquan.m.sha...@gmail.comwrote: Hello Wang Fei, This CL has been submitted which fixes the issue: http://review.coreboot.org/#/c/5701/ Thanks, Furquan On Thu, May 8, 2014 at 4:36 PM, WANG FEI wangfei.ji...@gmail.com wrote

Re: [coreboot] FSP, SNB, and a new board

Ron, The current coreboot already supported Sandy Bridge FSP, downloading a Sandy Bridge FSP form Intel website and placing it to current coreboot, it might work immediately. -Fei On Fri, May 9, 2014 at 9:21 PM, ron minnich rminn...@gmail.com wrote: Oh no, I don't want to try FSP, I just

[coreboot] Compling error in ubuntu 14.04

Hi, all I noticed coreboot compiles failed on my ubuntu 14.04 since the following change committed. *Author: Furquan Shaikh furq...@google.com furq...@google.com 2014-04-23 18:18:48 Committer: Furquan Shaikh furq...@google.com furq...@google.com 2014-05-06 19:23:31Parent:

Re: [coreboot] Bug in your code

', ' ') for PAYLOAD_SEGMENT_BSS that should fix little endian target machines 2. fix the runtime in coreboot to match cbfsutil where it sucks out the data as big endian and compares against the correct value. thanks ron On Fri, Apr 18, 2014 at 7:39 AM, WANG FEI wangfei.ji