://reviews.gem5.org/r/2711/#review6008
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On March 30, 2015, 9:16 a.m., Andreas Hansson wrote:
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On April 1, 2015, 4:28 p.m., Steve Reinhardt wrote:
src/mem/cache/cache_impl.hh, line 1724
http://reviews.gem5.org/r/2717/diff/1/?file=44386#file44386line1724
is this really necessary? I'm curious why setting this flag actually
breaks things
Andreas Hansson wrote:
We
/Options.py 8a7285d6197e
configs/dram/sweep.py 8a7285d6197e
Diff: http://reviews.gem5.org/r/2723/diff/
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at the right time.
Diffs
-
src/mem/cache/cache_impl.hh 8a7285d6197e
src/mem/cache/mshr.cc 8a7285d6197e
Diff: http://reviews.gem5.org/r/2724/diff/
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Diff: http://reviews.gem5.org/r/2725/diff/
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/lru.hh 8a7285d6197e
src/mem/cache/tags/lru.cc 8a7285d6197e
src/mem/cache/tags/random_repl.hh 8a7285d6197e
src/mem/cache/tags/random_repl.cc 8a7285d6197e
Diff: http://reviews.gem5.org/r/2711/diff/
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points [1.5 hours]
* Wrap-up and next steps [45 minutes]
More information will be available at: http://www.gem5.org/User_workshop_2015
We look forward to your contributions and hope to see you there.
Workshop organisers:
Ali Saidi, ARM
Andreas Hansson, ARM
Anthony Gutierrez, AMD
Nilay Vaish, Univ
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Diffs (updated)
-
configs/common/Caches.py 8a7285d6197e
configs/common/O3_ARM_v7a.py 8a7285d6197e
src/arch/arm/stage2_mmu.hh 8a7285d6197e
src/arch/x86/pagetable_walker.hh 8a7285d6197e
Diff: http://reviews.gem5.org/r/2716/diff/
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in the end.
- Andreas
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On March 30, 2015, 9:17 a.m., Andreas Hansson wrote
there is a risk that a downstream cache considers
the line exclusive when it really isn't.
Diffs (updated)
-
src/mem/cache/cache_impl.hh 8a7285d6197e
Diff: http://reviews.gem5.org/r/2715/diff/
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On March 31, 2015, 5:41 a.m., Steve Reinhardt wrote:
How about adding something like
static const FlagsType ORDERED_UNCACHABLE = UNCACHEABLE | STRICT_ORDER;
then using that in place of all the Request::UNCACHEABLE |
Request::STRICT_ORDER expressions?
Andreas Hansson wrote
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Diff: http://reviews.gem5.org/r/2713/diff/
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/pal.isa 8a7285d6197e
src/arch/alpha/tlb.cc 8a7285d6197e
src/arch/alpha/types.hh 8a7285d6197e
src/mem/request.hh 8a7285d6197e
Diff: http://reviews.gem5.org/r/2719/diff/
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: http://reviews.gem5.org/r/2720/diff/
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ordered memory.
Diffs
-
src/arch/arm/tlb.cc 8a7285d6197e
Diff: http://reviews.gem5.org/r/2721/diff/
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: http://reviews.gem5.org/r/2716/diff/
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/ArmSystem.py 8a7285d6197e
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8a7285d6197e
src/mem/coherent_xbar.cc 8a7285d6197e
src/mem/snoop_filter.cc 8a7285d6197e
src/cpu/o3/cpu.cc 8a7285d6197e
src/dev/dma_device.cc 8a7285d6197e
src/mem/cache/cache_impl.hh 8a7285d6197e
Diff: http://reviews.gem5.org/r/2717/diff/
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8a7285d6197e
src/mem/cache/tags/random_repl.cc 8a7285d6197e
src/mem/cache/tags/random_repl.hh 8a7285d6197e
Diff: http://reviews.gem5.org/r/2711/diff/
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- Andreas Hansson
On March 25, 2015, 3:50 p.m
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On Feb. 6, 2015, 10:07 p.m
changeset b32578b2af99 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b32578b2af99
description:
mem: Align all MSHR entries to block boundaries
This patch aligns all MSHR queue entries to block boundaries to
simplify checks for matches. Previously
changeset b2071d0eb5f1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b2071d0eb5f1
description:
mem: Modernise MSHR iterators to C++11
This patch updates the iterators in the MSHR and MSHR queues to use
C++11 range-based for loops. It also does a bit
changeset 9a34e28cd2c2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9a34e28cd2c2
description:
mem: Ignore uncacheable MSHRs when finding matches
This patch changes how we search for matching MSHRs, ignoring any MSHR
that is allocated for an
changeset 993c2baa485a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=993c2baa485a
description:
mem: Remove redundant allocateUncachedReadBuffer in cache
This patch removes the no-longer-needed
allocateUncachedReadBuffer. Besides the checks it is
changeset 8a7285d6197e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8a7285d6197e
description:
arm, configs: Do not forward snoops from I cache
This fix simply tells the I cache to not forward snoops to the fetch
unit (since there is really no
changeset 9e521c0c3877 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9e521c0c3877
description:
mem: Cleanup flow for uncacheable accesses
This patch simplifies the code dealing with uncacheable timing
accesses, aiming to align it with the existing
changeset c48310de1a51 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c48310de1a51
description:
mem: Allocate cache writebacks before new MSHRs
This patch changes the order of writeback allocation such that any
writebacks resulting from a tag lookup
/2708/diff/
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Heavily used in our ISPASS'15 paper
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src/dev/arm/UFSHostDevice.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2709/diff/
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Heavily used in our ISPASS'15 paper
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Again, the summary should start with sim :
- Andreas Hansson
) The summary should start with dev : (see http://gem5.org/Commit_Access
for details)
2) Are any regressions affected? (or is this not impacting linux)
- Andreas Hansson
On March 25, 2015, 11:10 a.m., Ruslan Bukin wrote
changeset c7e392e343eb in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c7e392e343eb
description:
cpu: Fix InstPBTrace inheritance
This patch fixes an issue that prevented gem5 to be built with C++
config and without Python.
diffstat:
8f5993cfa916
Diff: http://reviews.gem5.org/r/2704/diff/
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Diff: http://reviews.gem5.org/r/2698/diff/
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src/mem/cache/cache_impl.hh 8f5993cfa916
Diff: http://reviews.gem5.org/r/2703/diff/
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Hi all,
I’d like to get the following fixes to the cache model pushed before the end of
the week. The changes are not particularly complicated (rather subtle and
elegant if you ask me), and the impact on the regressions is restricted to a
handful tests with some minor changes.
changeset 02621b4f013b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=02621b4f013b
description:
tests: Final reclassification of quick regressions
A few regressions were still considered long, but finished well within
the 180 seconds. They are only a
changeset dcd7cf19f7c5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=dcd7cf19f7c5
description:
mem: Tidy up Request
This patch does a bit of house keeping, fixing up typos, removing dead
code etc.
diffstat:
src/mem/request.hh | 32
is present in the cache. Would
it make sense to flush/downgrade somehow and then treat this like a miss?
- Andreas Hansson
On March 14, 2015, 5:19 p.m., Steve Reinhardt wrote:
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8a4040874157
src/mem/cache/cache_impl.hh 8a4040874157
Diff: http://reviews.gem5.org/r/2703/diff/
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we don't have to bother
with the assert at the bottom?
Andreas Hansson wrote:
Could do if you think it makes things prettier. I think I'd rather create
a new variable with a different name if you think it is needed.
Steve Reinhardt wrote:
I don't understand your response
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On March 22, 2015, 7:35 a.m., Andreas Hansson wrote
we don't have to bother
with the assert at the bottom?
Andreas Hansson wrote:
Could do if you think it makes things prettier. I think I'd rather create
a new variable with a different name if you think it is needed.
Steve Reinhardt wrote:
I don't understand your response
, they are still needed.
- Andreas
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On March 22, 2015, 7:35 a.m., Andreas Hansson
we don't have to bother
with the assert at the bottom?
Andreas Hansson wrote:
Could do if you think it makes things prettier. I think I'd rather create
a new variable with a different name if you think it is needed.
Steve Reinhardt wrote:
I don't understand your response
Diff: http://reviews.gem5.org/r/2703/diff/
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On March 21, 2015, 1:32 p.m., Andreas Hansson wrote:
I like the idea of getting it sorted (hopefully we can retire the
RubyMemoryControl). I am not sure about the solution though. Surely all the
stats for the DRAMCtrl object(s) would be all confused if time advances,
but no accesses
the
RubyMemoryControl). I am not sure about the solution though. Surely all the
stats for the DRAMCtrl object(s) would be all confused if time advances, but no
accesses are counted? Do we not also need to reset all stats once the warmup is
sorted?
- Andreas Hansson
On March 20, 2015, 7:48 p.m., Lena
Indeed. Next comes the rename of quick to short, and split into short,
medium and long.
Short = 180 s
Medium = 1800 s
Long = everything else
Andreas
On 19/03/2015 08:16, Gabe Black gabebl...@google.com wrote:
Awesome :-)
On Mar 19, 2015 1:10 AM, Andreas Hansson andreas.hans...@arm.com
wrote
changeset 62b24818c8c6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=62b24818c8c6
description:
tests: Recategorise regressions based on run time
This patch takes a first stab at recategorising the regression tests
based on actual run times. The
19 04:06:17 2015 -0400
+++ b/configs/example/memtest.pyThu Mar 19 04:06:18 2015 -0400
@@ -40,11 +40,20 @@
# Andreas Hansson
import optparse
+import random
import sys
import m5
from m5.objects import *
+# This example script stress tests the memory system by creating false
changeset cb77dfd5db54 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cb77dfd5db54
description:
tests: Bump timeout to 5 hours
Align with observed run-times just above 4 hours for some hosts.
diffstat:
tests/SConscript | 6 +++---
1 files changed, 3
changeset 062c820aef24 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=062c820aef24
description:
config: Fix DRAM rank option in sweep script
Align with changes in the common bits.
diffstat:
configs/dram/sweep.py | 9 +++--
1 files changed, 3
changeset 791e4619919d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=791e4619919d
description:
mem: Use emplace front/back for deferred packets
Embrace C++11 for the deferred packets as we actually store the
objects in the data structure, and not
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- Andreas Hansson
On March 18, 2015, 12:45 p.m
it using
postreview?
- Andreas Hansson
On March 11, 2015, 4:13 p.m., Nikos Nikoleris wrote:
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/i2cdev.hh PRE-CREATION
src/dev/SConscript 655ff3f6352d
src/dev/i2cbus.hh PRE-CREATION
src/dev/i2cbus.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/2700/diff/
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., Andreas Hansson wrote:
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(Updated March 17, 2015, 8:30 a.m.)
Review
Hi Lokesh,
I suspect the kernel you are using is not compatible with the disk image in
question.
We should have instructions for how to run KitKat online shortly, along with
pointers to a recent kernel (with DVFS support etc).
Andreas
From: Lokesh Jindal
Hi all,
I intend to push the following patches at the end of the week. If you have
comments or need more time please let me know.
# KitKat enablement
http://reviews.gem5.org/r/2671/
# ARM GIC updates
http://reviews.gem5.org/r/2681/
http://reviews.gem5.org/r/2682/
# Improved testing
/diff/
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, and then proceeds to ignore any existing MSHR for the
block in question. This unifies the flow for cacheable and uncacheable
accesses.
Diffs
-
src/mem/cache/cache_impl.hh 655ff3f6352d
Diff: http://reviews.gem5.org/r/2698/diff/
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On March 14, 2015, 5:17 p.m
/prefetch/stride.cc 655ff3f6352d
Diff: http://reviews.gem5.org/r/2696/diff/
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655ff3f6352d
src/mem/cache/cache_impl.hh 655ff3f6352d
Diff: http://reviews.gem5.org/r/2695/diff/
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/mshr_queue.cc 655ff3f6352d
Diff: http://reviews.gem5.org/r/2693/diff/
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Diff: http://reviews.gem5.org/r/2697/diff/
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in the writeback MSHRs of upper level caches
continues to be covered by the MEM_INHIBIT flag.
Diffs
-
src/mem/cache/cache_impl.hh 655ff3f6352d
src/mem/packet.hh 655ff3f6352d
Diff: http://reviews.gem5.org/r/2692/diff/
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/mshr.cc 655ff3f6352d
src/mem/cache/mshr_queue.cc 655ff3f6352d
Diff: http://reviews.gem5.org/r/2694/diff/
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the changed order of the write buffer allocation and dealing with the
writebacks is important?
- Andreas Hansson
On March 14, 2015, 5:19 p.m., Steve Reinhardt wrote:
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On March 14, 2015, 5:16 p.m
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On March 14, 2015, 5:16 p.m
Hi Renju,
We use quite a variety of big.LITTLE system configurations, and all the
building blocks are already part of gem5.
All you need is a custom python script to configure the system, and a
suitable kernel and DTB file. See e.g.
http://www.gem5.org/Running_gem5#Experimenting_with_DVFS for an
Hi Steve,
Thanks for chasing this down. I guess zizzer is not too modern (and
perhaps running with a large number of threads?), as the 4 hour limit was
picked to give us a ~40% headroom based on what I see on my old-ish
workstation.
Ironically the regression in question is only the third slowest
PRE-CREATION
Diff: http://reviews.gem5.org/r/2685/diff/
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-checkpoint/stats.txt
PRE-CREATION
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/system.terminal
8a20e2a1562d
Diff: http://reviews.gem5.org/r/2684/diff/
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Should this perhaps be a probe rather?
- Andreas Hansson
On March 4
Hi Marcus,
I’d also say this would be a great topic for the User Workshop at ISCA:
http://www.gem5.org/User_workshop_2015
Andreas
On 03/03/2015 15:14, Ali Saidi via gem5-dev gem5-dev@gem5.org wrote:
Hi Marcus,
Option 1 is probably the most preferred route as the code is much more
likely to
. Thanks for getting
this in shape.
- Andreas Hansson
On March 3, 2015, 2:53 a.m., Dibakar Gope wrote:
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was that the response from the cache with the
write-buffer copy was causing an assertion, since the receiving cache wasn't
expecting a response because it had squashed the prefetch.
Andreas Hansson wrote:
Here is the fix: http://reviews.gem5.org/r/2654/
The fix has been pushed. I believe this patch can
changeset 9ba5e70964a4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9ba5e70964a4
description:
mem: Tidy up the cache debug messages
Avoid redundant inclusion of the name in the DPRINTF string.
diffstat:
src/mem/cache/base.cc | 10 +-
changeset d1387fcd94b8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d1387fcd94b8
description:
mem: Unify all cache DPRINTF address formatting
This patch changes all the DPRINTF messages in the cache to use
'%#llx' every time a packet address is
changeset 8a20e2a1562d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8a20e2a1562d
description:
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing,
changeset 4f8c1bd6fdb8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4f8c1bd6fdb8
description:
arm: Share a port for the two table walker objects
This patch changes how the MMU and table walkers are created such that
a single port is used to connect
changeset 67b3e74de9ae in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=67b3e74de9ae
description:
mem: Move crossbar default latencies to subclasses
This patch introduces a few subclasses to the CoherentXBar and
NoncoherentXBar to distinguish the
changeset 1072b1381560 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1072b1381560
description:
mem: Fix cache MSHR conflict determination
This patch fixes a rather subtle issue in the sending of MSHR requests
in the cache, where the logic previously
changeset 9b71309d29f9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9b71309d29f9
description:
tests: Run regression timeout as foreground
Allow the user to send signals such as Ctrl C to the gem5 runs. Note
that this assumes coreutils = 8.13, which
changeset b1d90d88420e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b1d90d88420e
description:
mem: Add byte mask to Packet::checkFunctional
This patch changes the valid-bytes start/end to a proper byte
mask. With the changes in timing introduced in
On Feb. 19, 2015, 10:50 p.m., Andreas Hansson wrote:
Ship It!
Could someone be kind enough to push this?
- Andreas
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Great. Let us know if there are still any remaining issues.
We’ve got some additional cache fixes that should be on RB before the end of
the week.
Andreas
From: Steve Reinhardt ste...@gmail.commailto:ste...@gmail.com
Date: Monday, 2 March 2015 16:47
To: Andreas Hansson andreas.hans
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This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2673/#review5918
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Ship it!
Ship It!
- Andreas Hansson
On Feb. 28, 2015, 10:34 p.m
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This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2674/#review5919
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Ship it!
Ship It!
- Andreas Hansson
On Feb. 28, 2015, 10:37 p.m
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This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2675/#review5920
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Ship it!
Ship It!
- Andreas Hansson
On Feb. 28, 2015, 10:39 p.m
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