[gem5-dev] Change in public/gem5[master]: arch-arm: Corrected encoding for T32 HVC instruction

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5541 )


Change subject: arch-arm: Corrected encoding for T32 HVC instruction
..

arch-arm: Corrected encoding for T32 HVC instruction

This patch corrects the encoding of the HVC (Hypervisor Call) for the
T32 instruction set.

Change-Id: I6f77eaf5c586697e9ccd588419c61e6d90c6c7bf
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Chuan Zhu 
Reviewed-on: https://gem5-review.googlesource.com/5541
Maintainer: Andreas Sandberg 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/arm/isa/formats/branch.isa
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/arch/arm/isa/formats/branch.isa  
b/src/arch/arm/isa/formats/branch.isa

index 513506d..df85b08 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010, 2012-2013 ARM Limited
+// Copyright (c) 2010,2012-2013,2017 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -247,7 +247,7 @@
 }
 }
 }
-  case 0xfe:
+  case 0x7e:
 {
 uint32_t imm16 = (bits(machInst, 19, 16) << 12) |
  (bits(machInst, 11,  0) <<  0);

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I6f77eaf5c586697e9ccd588419c61e6d90c6c7bf
Gerrit-Change-Number: 5541
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Assignee: Giacomo Gabrielli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-CC: Giacomo Gabrielli 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Add assertions when extracting an ArmSystem from a TC

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/6161 )


Change subject: arch-arm: Add assertions when extracting an ArmSystem from  
a TC

..

arch-arm: Add assertions when extracting an ArmSystem from a TC

We sometimes need to cast the System pointer stored in a
ThreadContext to an ArmSystem pointer to query global
system setting.
Add an assertion to make sure that the cast resulted in a
valid pointer.

Change-Id: Id382d0c1dceefee8f74d070c205c7b43b83ab215
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/6161
Maintainer: Andreas Sandberg 
---
M src/arch/arm/system.cc
M src/arch/arm/system.hh
2 files changed, 25 insertions(+), 30 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 50d0af9..1fe7060 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2015 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -169,15 +169,18 @@
 }
 }

+ArmSystem*
+ArmSystem::getArmSystem(ThreadContext *tc)
+{
+ArmSystem *a_sys = dynamic_cast(tc->getSystemPtr());
+assert(a_sys);
+return a_sys;
+}
+
 bool
 ArmSystem::haveSecurity(ThreadContext *tc)
 {
-if (!FullSystem)
-return false;
-
-ArmSystem *a_sys = dynamic_cast(tc->getSystemPtr());
-assert(a_sys);
-return a_sys->haveSecurity();
+return FullSystem? getArmSystem(tc)->haveSecurity() : false;
 }


@@ -201,63 +204,49 @@
 bool
 ArmSystem::haveLPAE(ThreadContext *tc)
 {
-if (!FullSystem)
-return false;
-
-ArmSystem *a_sys = dynamic_cast(tc->getSystemPtr());
-assert(a_sys);
-return a_sys->haveLPAE();
+return FullSystem? getArmSystem(tc)->haveLPAE() : false;
 }

 bool
 ArmSystem::haveVirtualization(ThreadContext *tc)
 {
-if (!FullSystem)
-return false;
-
-ArmSystem *a_sys = dynamic_cast(tc->getSystemPtr());
-assert(a_sys);
-return a_sys->haveVirtualization();
+return FullSystem? getArmSystem(tc)->haveVirtualization() : false;
 }

 bool
 ArmSystem::highestELIs64(ThreadContext *tc)
 {
-return FullSystem ?
-dynamic_cast(tc->getSystemPtr())->highestELIs64() :
-true;
+return FullSystem? getArmSystem(tc)->highestELIs64() : true;
 }

 ExceptionLevel
 ArmSystem::highestEL(ThreadContext *tc)
 {
-return FullSystem ?
-dynamic_cast(tc->getSystemPtr())->highestEL() :
-EL1;
+return FullSystem? getArmSystem(tc)->highestEL() : EL1;
 }

 Addr
 ArmSystem::resetAddr64(ThreadContext *tc)
 {
-return dynamic_cast(tc->getSystemPtr())->resetAddr64();
+return getArmSystem(tc)->resetAddr64();
 }

 uint8_t
 ArmSystem::physAddrRange(ThreadContext *tc)
 {
-return dynamic_cast(tc->getSystemPtr())->physAddrRange();
+return getArmSystem(tc)->physAddrRange();
 }

 Addr
 ArmSystem::physAddrMask(ThreadContext *tc)
 {
-return dynamic_cast(tc->getSystemPtr())->physAddrMask();
+return getArmSystem(tc)->physAddrMask();
 }

 bool
 ArmSystem::haveLargeAsid64(ThreadContext *tc)
 {
-return dynamic_cast*>(tc->getSystemPtr())->haveLargeAsid64();

+return getArmSystem(tc)->haveLargeAsid64();
 }

 ArmSystem *
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index 9776933..b81ec05 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2015-2016 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015-2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -228,6 +228,12 @@
  */
 const AddrRange () const { return _m5opRange; }

+/**
+ * Returns a valid ArmSystem pointer if using ARM ISA, it fails
+ * otherwise.
+ */
+static ArmSystem* getArmSystem(ThreadContext *tc);
+
 /** Returns true if the system of a specific thread context implements  
the

  * Security Extensions
  */

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Id382d0c1dceefee8f74d070c205c7b43b83ab215
Gerrit-Change-Number: 6161
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Add haveEL pseudocode function

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/6162 )


Change subject: arch-arm: Add haveEL pseudocode function
..

arch-arm: Add haveEL pseudocode function

This patch introduces the ARM pseudocode haveEL function
into gem5.

Change-Id: I0d96070959e8e13773eb7fa9964894ec0ff2cac2
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/6162
Maintainer: Andreas Sandberg 
---
M src/arch/arm/system.cc
M src/arch/arm/system.hh
2 files changed, 22 insertions(+), 2 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 1fe7060..097a87b 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -225,6 +225,23 @@
 return FullSystem? getArmSystem(tc)->highestEL() : EL1;
 }

+bool
+ArmSystem::haveEL(ThreadContext *tc, ExceptionLevel el)
+{
+switch (el) {
+  case EL0:
+  case EL1:
+return true;
+  case EL2:
+return haveVirtualization(tc);
+  case EL3:
+return haveSecurity(tc);
+  default:
+warn("Unimplemented Exception Level\n");
+return false;
+}
+}
+
 Addr
 ArmSystem::resetAddr64(ThreadContext *tc)
 {
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index b81ec05..46103f4 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -259,8 +259,11 @@
  */
 static ExceptionLevel highestEL(ThreadContext *tc);

-/** Returns the reset address if the highest implemented exception  
level for

- * the system of a specific thread context is 64 bits (ARMv8)
+/** Return true if the system implements a specific exception level */
+static bool haveEL(ThreadContext *tc, ExceptionLevel el);
+
+/** Returns the reset address if the highest implemented exception  
level

+ * for the system of a specific thread context is 64 bits (ARMv8)
  */
 static Addr resetAddr64(ThreadContext *tc);


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Gerrit-Change-Number: 6162
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Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Add assertions when extracting an ArmSystem from a TC

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/6161

to look at the new patch set (#2).

Change subject: arch-arm: Add assertions when extracting an ArmSystem from  
a TC

..

arch-arm: Add assertions when extracting an ArmSystem from a TC

We sometimes need to cast the System pointer stored in a
ThreadContext to an ArmSystem pointer to query global
system setting.
Add an assertion to make sure that the cast resulted in a
valid pointer.

Change-Id: Id382d0c1dceefee8f74d070c205c7b43b83ab215
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/system.cc
M src/arch/arm/system.hh
2 files changed, 25 insertions(+), 30 deletions(-)


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Gerrit-Change-Number: 6161
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Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Add assertions when extracting an ArmSystem from a TC

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/6161

to review the following change.


Change subject: arch-arm: Add assertions when extracting an ArmSystem from  
a TC

..

arch-arm: Add assertions when extracting an ArmSystem from a TC

If ArmSystem utility functions are used for non-ARM system, we want a
predictable simulation failure.  Previously relying on deferencing
nullptr.

Change-Id: Id382d0c1dceefee8f74d070c205c7b43b83ab215
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/system.cc
M src/arch/arm/system.hh
2 files changed, 25 insertions(+), 30 deletions(-)



diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 50d0af9..1fe7060 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2015 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -169,15 +169,18 @@
 }
 }

+ArmSystem*
+ArmSystem::getArmSystem(ThreadContext *tc)
+{
+ArmSystem *a_sys = dynamic_cast(tc->getSystemPtr());
+assert(a_sys);
+return a_sys;
+}
+
 bool
 ArmSystem::haveSecurity(ThreadContext *tc)
 {
-if (!FullSystem)
-return false;
-
-ArmSystem *a_sys = dynamic_cast(tc->getSystemPtr());
-assert(a_sys);
-return a_sys->haveSecurity();
+return FullSystem? getArmSystem(tc)->haveSecurity() : false;
 }


@@ -201,63 +204,49 @@
 bool
 ArmSystem::haveLPAE(ThreadContext *tc)
 {
-if (!FullSystem)
-return false;
-
-ArmSystem *a_sys = dynamic_cast(tc->getSystemPtr());
-assert(a_sys);
-return a_sys->haveLPAE();
+return FullSystem? getArmSystem(tc)->haveLPAE() : false;
 }

 bool
 ArmSystem::haveVirtualization(ThreadContext *tc)
 {
-if (!FullSystem)
-return false;
-
-ArmSystem *a_sys = dynamic_cast(tc->getSystemPtr());
-assert(a_sys);
-return a_sys->haveVirtualization();
+return FullSystem? getArmSystem(tc)->haveVirtualization() : false;
 }

 bool
 ArmSystem::highestELIs64(ThreadContext *tc)
 {
-return FullSystem ?
-dynamic_cast(tc->getSystemPtr())->highestELIs64() :
-true;
+return FullSystem? getArmSystem(tc)->highestELIs64() : true;
 }

 ExceptionLevel
 ArmSystem::highestEL(ThreadContext *tc)
 {
-return FullSystem ?
-dynamic_cast(tc->getSystemPtr())->highestEL() :
-EL1;
+return FullSystem? getArmSystem(tc)->highestEL() : EL1;
 }

 Addr
 ArmSystem::resetAddr64(ThreadContext *tc)
 {
-return dynamic_cast(tc->getSystemPtr())->resetAddr64();
+return getArmSystem(tc)->resetAddr64();
 }

 uint8_t
 ArmSystem::physAddrRange(ThreadContext *tc)
 {
-return dynamic_cast(tc->getSystemPtr())->physAddrRange();
+return getArmSystem(tc)->physAddrRange();
 }

 Addr
 ArmSystem::physAddrMask(ThreadContext *tc)
 {
-return dynamic_cast(tc->getSystemPtr())->physAddrMask();
+return getArmSystem(tc)->physAddrMask();
 }

 bool
 ArmSystem::haveLargeAsid64(ThreadContext *tc)
 {
-return dynamic_cast*>(tc->getSystemPtr())->haveLargeAsid64();

+return getArmSystem(tc)->haveLargeAsid64();
 }

 ArmSystem *
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index 9776933..b81ec05 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2015-2016 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015-2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -228,6 +228,12 @@
  */
 const AddrRange () const { return _m5opRange; }

+/**
+ * Returns a valid ArmSystem pointer if using ARM ISA, it fails
+ * otherwise.
+ */
+static ArmSystem* getArmSystem(ThreadContext *tc);
+
 /** Returns true if the system of a specific thread context implements  
the

  * Security Extensions
  */

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[gem5-dev] Change in public/gem5[master]: arch-arm: Add haveEL pseudocode function

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/6162

to review the following change.


Change subject: arch-arm: Add haveEL pseudocode function
..

arch-arm: Add haveEL pseudocode function

This patch introduces the ARM pseudocode haveEL function
into gem5.

Change-Id: I0d96070959e8e13773eb7fa9964894ec0ff2cac2
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/system.cc
M src/arch/arm/system.hh
2 files changed, 22 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 1fe7060..097a87b 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -225,6 +225,23 @@
 return FullSystem? getArmSystem(tc)->highestEL() : EL1;
 }

+bool
+ArmSystem::haveEL(ThreadContext *tc, ExceptionLevel el)
+{
+switch (el) {
+  case EL0:
+  case EL1:
+return true;
+  case EL2:
+return haveVirtualization(tc);
+  case EL3:
+return haveSecurity(tc);
+  default:
+warn("Unimplemented Exception Level\n");
+return false;
+}
+}
+
 Addr
 ArmSystem::resetAddr64(ThreadContext *tc)
 {
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index b81ec05..46103f4 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -259,8 +259,11 @@
  */
 static ExceptionLevel highestEL(ThreadContext *tc);

-/** Returns the reset address if the highest implemented exception  
level for

- * the system of a specific thread context is 64 bits (ARMv8)
+/** Return true if the system implements a specific exception level */
+static bool haveEL(ThreadContext *tc, ExceptionLevel el);
+
+/** Returns the reset address if the highest implemented exception  
level

+ * for the system of a specific thread context is 64 bits (ARMv8)
  */
 static Addr resetAddr64(ThreadContext *tc);


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[gem5-dev] Change in public/gem5[master]: arch-arm: HVC instruction undefined in secure EL1

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5921 )


Change subject: arch-arm: HVC instruction undefined in secure EL1
..

arch-arm: HVC instruction undefined in secure EL1

Since EL2 is not available in secure mode, any HVC call from secure mode
should be treated as undefined. This behaviour was implemented in
aarch32 HVC but not in 64 bit version

Change-Id: Ibaa4d8b1e8fe01d2ba3ef07494c09a4d3e7e87b0
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/5921
Maintainer: Andreas Sandberg 
---
M src/arch/arm/isa/insts/misc64.isa
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/isa/insts/misc64.isa  
b/src/arch/arm/isa/insts/misc64.isa

index 58f08f5..00724c0 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -53,7 +53,7 @@
 SCR scr = Scr64;

 if (!ArmSystem::haveVirtualization(xc->tcBase()) ||
-(ArmSystem::haveSecurity(xc->tcBase()) && !scr.hce)) {
+(ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
 fault = disabledFault();
 } else {
 fault = std::make_shared(machInst, bits(machInst,  
20, 5));


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Gerrit-Change-Id: Ibaa4d8b1e8fe01d2ba3ef07494c09a4d3e7e87b0
Gerrit-Change-Number: 5921
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Gabrielli 
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[gem5-dev] Change in public/gem5[master]: arm: Enable ns registers access in secure mode

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/6201



Change subject: arm: Enable ns registers access in secure mode
..

arm: Enable ns registers access in secure mode

Arm security extension introduced register banking between secure and
non-secure mode. This has been removed in armv8 using AArch64 in EL3,
where the decoded register is by default the non-secure version. Using
non-secure register infos(flags) was preventing secure execution to
access the register with the MRC/MCR at EL1.
The patch updates the following banked registers' flags so that their
non-secure version can be accessed in secure mode:

MISCREG_CSSELR, MISCREG_SCTLR, MISCREG_ACTLR, MISCREG_TTBR0,
MISCREG_TTBR1, MISCREG_TTBCR, MISCREG_DACR, MISCREG_DFSR, MISCREG_IFSR,
MISCREG_ADFSR, MISCREG_AIFSR, MISCREG_DFAR, MISCREG_IFAR, MISCREG_PAR,
MISCREG_PRRR, MISCREG_MAIR0, MISCREG_NMRR, MISCREG_MAIR1,
MISCREG_AMAIR0, MISCREG_AMAIR1, MISCREG_VBAR, MISCREG_CONTEXTIDR,
MISCREG_TPIDRURW, MISCREG_TPIDRURO, MISCREG_TPIDRPRW, MISCREG_CNTP_TVAL,
MISCREG_CNTP_CTL, MISCREG_CNTP_CVAL

For those registers the following permission bits have been set:

MISCREG_PRI_S_RD
MISCREG_PRI_S_WR

Change-Id: Ib881c526e75d69e313f8ef66eb78fc704de6bf59
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Giacomo Gabrielli 
---
M src/arch/arm/miscregs.cc
1 file changed, 28 insertions(+), 28 deletions(-)



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index d31c84c..d08f751 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -344,7 +344,7 @@
 // MISCREG_CSSELR
 bitset(string("00010001")),
 // MISCREG_CSSELR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_CSSELR_S
 bitset(string("001100110011")),
 // MISCREG_VPIDR
@@ -354,13 +354,13 @@
 // MISCREG_SCTLR
 bitset(string("00010001")),
 // MISCREG_SCTLR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_SCTLR_S
 bitset(string("001100110011")),
 // MISCREG_ACTLR
 bitset(string("00010001")),
 // MISCREG_ACTLR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_ACTLR_S
 bitset(string("001100110011")),
 // MISCREG_CPACR
@@ -388,19 +388,19 @@
 // MISCREG_TTBR0
 bitset(string("00010001")),
 // MISCREG_TTBR0_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_TTBR0_S
 bitset(string("001100110011")),
 // MISCREG_TTBR1
 bitset(string("00010001")),
 // MISCREG_TTBR1_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_TTBR1_S
 bitset(string("001100110011")),
 // MISCREG_TTBCR
 bitset(string("00010001")),
 // MISCREG_TTBCR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_TTBCR_S
 bitset(string("001100110011")),
 // MISCREG_HTCR
@@ -410,31 +410,31 @@
 // MISCREG_DACR
 bitset(string("00010001")),
 // MISCREG_DACR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_DACR_S
 bitset(string("001100110011")),
 // MISCREG_DFSR
 bitset(string("00010001")),
 // MISCREG_DFSR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_DFSR_S
 bitset(string("001100110011")),
 // MISCREG_IFSR
 bitset(string("00010001")),
 // MISCREG_IFSR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_IFSR_S
 bitset(string("001100110011")),
 // MISCREG_ADFSR
 bitset(string("00010100")),
 // MISCREG_ADFSR_NS
-bitset(string("1100110011100100")),
+bitset(string("110011100100")),
 // MISCREG_ADFSR_S
 bitset(string("0011001100100100")),
 // MISCREG_AIFSR
 bitset(string("00010100")),
 // MISCREG_AIFSR_NS
-bitset(string("1100110011100100")),
+bitset(string("110011100100")),
 // MISCREG_AIFSR_S
 bitset(string("0011001100100100")),
 // MISCREG_HADFSR
@@ -446,13 +446,13 @@
 // MISCREG_DFAR
 bitset(string("00010001")),
 // MISCREG_DFAR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_DFAR_S
 bitset(string("001100110011")),
 // MISCREG_IFAR
 bitset(string("00010001")),
 // MISCREG_IFAR_NS
-

[gem5-dev] Change in public/gem5[master]: arm: Change access permission in TPIDRURO and TPIDRURW

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/6381

to review the following change.


Change subject: arm: Change access permission in TPIDRURO and TPIDRURW
..

arm: Change access permission in TPIDRURO and TPIDRURW

This patch corrects the TPIDRURO and TPIDRURW access flags: TPIDRURO is
now readable in secure user mode, an TPIDRURW is readable and writable
in secure user mode.

Change-Id: I6293d9a3bcc7adc0f655bf98d29aca51eca5a002
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-by: Chuan Zhu 
---
M src/arch/arm/miscregs.cc
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 826e567..ece5524 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -686,13 +686,13 @@
 // MISCREG_TPIDRURW_NS
 bitset(string("11001111")),
 // MISCREG_TPIDRURW_S
-bitset(string("001100110011")),
+bitset(string("0011001100110011")),
 // MISCREG_TPIDRURO
 bitset(string("00010001")),
 // MISCREG_TPIDRURO_NS
 bitset(string("110011010111")),
 // MISCREG_TPIDRURO_S
-bitset(string("001100110011")),
+bitset(string("0011001100010011")),
 // MISCREG_TPIDRPRW
 bitset(string("00010001")),
 // MISCREG_TPIDRPRW_NS

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[gem5-dev] Change in public/gem5[master]: arch-arm: Hyp routed undef fault need to change its syndrome

[Giacomo Travaglini (Gerrit)]

Hello Nikos Nikoleris, Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/6621

to review the following change.


Change subject: arch-arm: Hyp routed undef fault need to change its syndrome
..

arch-arm: Hyp routed undef fault need to change its syndrome

If undefined instruction has to be routed to EL2, the HSR register
must change the HSR.EC and HSR.ISS accordingly, which means not using
the EL1 exception syndrome, but the unknown reason one (EC=0, ISS=0)

Change-Id: I1540c713ab545bf307c1dad3ae305de4178443f4
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 27 insertions(+), 8 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 0293ee1..a41452f 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -391,6 +391,7 @@
 uint32_t value;
 uint32_t exc_class = (uint32_t) ec(tc);
 uint32_t issVal = iss();
+
 assert(!from64 || ArmSystem::highestELIs64(tc));

 value = exc_class << 26;
@@ -438,12 +439,15 @@
 from64 = true;

 // Determine target exception level
-if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc))
+if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) {
 toEL = EL3;
-else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc))
+} else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) {
 toEL = EL2;
-else
+hypRouted = true;
+} else {
 toEL = opModeToEL(nextMode());
+}
+
 if (fromEL > toEL)
 toEL = fromEL;

@@ -486,12 +490,14 @@
 armInst->annotateFault(this);
 }

-if (have_security && routeToMonitor(tc))
+if (have_security && routeToMonitor(tc)) {
 cpsr.mode = MODE_MON;
-else if (have_virtualization && routeToHyp(tc))
+} else if (have_virtualization && routeToHyp(tc)) {
 cpsr.mode = MODE_HYP;
-else
+hypRouted = true;
+} else {
 cpsr.mode = nextMode();
+}

 // Ensure Secure state if initially in Monitor mode
 if (have_security && saved_cpsr.mode == MODE_MON) {
@@ -747,6 +753,12 @@
 uint32_t
 UndefinedInstruction::iss() const
 {
+
+// If UndefinedInstruction is routed to hypervisor, iss field is 0.
+if (hypRouted) {
+return 0;
+}
+
 if (overrideEc == EC_INVALID)
 return issRaw;

@@ -836,7 +848,12 @@
 ExceptionClass
 UndefinedInstruction::ec(ThreadContext *tc) const
 {
-return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
+// If UndefinedInstruction is routed to hypervisor,
+// HSR.EC field is 0.
+if (hypRouted)
+return EC_UNKNOWN;
+else
+return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
 }


diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 3191ceb..fa6740a 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -73,6 +73,8 @@
 ExceptionLevel toEL;  // Target exception level
 OperatingMode fromMode;  // Source operating mode

+bool hypRouted; // True if the fault has been routed to Hypervisor
+
 Addr getVector(ThreadContext *tc);
 Addr getVector64(ThreadContext *tc);

@@ -173,7 +175,7 @@

 ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
 machInst(_machInst), issRaw(_iss), from64(false), to64(false),
-fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED) {}
+fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED), hypRouted(false)  
{}


 // Returns the actual syndrome register to use based on the target
 // exception level

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Gerrit-Project: public/gem5
Gerrit-Branch: master
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Gerrit-Change-Id: I1540c713ab545bf307c1dad3ae305de4178443f4
Gerrit-Change-Number: 6621
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Fixed WFE/WFI trapping behaviour

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/6622

to review the following change.


Change subject: arch-arm: Fixed WFE/WFI trapping behaviour
..

arch-arm: Fixed WFE/WFI trapping behaviour

This patch fixes the WFx trapping behaviour by introducing the arm arm
v8 pseudocode functions: checkForWFxTrap32 and checkForWFxTrap64

Change-Id: I3db0d78b5c4ad46860e6d199c2f2fc7b41842840
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/isa/insts/misc.isa
3 files changed, 164 insertions(+), 33 deletions(-)



diff --git a/src/arch/arm/insts/static_inst.cc  
b/src/arch/arm/insts/static_inst.cc

index 8501715..eeda3ad 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2014, 2016 ARM Limited
+ * Copyright (c) 2010-2014, 2016-2017 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -735,6 +735,129 @@
 return NoFault;
 }

+inline bool
+ArmStaticInst::isWFxTrapping(ThreadContext *tc,
+ ExceptionLevel tgtEl,
+ bool isWfe) const
+{
+bool trap = false;
+SCTLR sctlr = ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL1));
+HCR hcr = ((HCR)tc->readMiscReg(MISCREG_HCR_EL2));
+SCR scr = ((SCR)tc->readMiscReg(MISCREG_SCR_EL3));
+
+switch (tgtEl) {
+  case EL1:
+trap = isWfe? !sctlr.ntwe : !sctlr.ntwi;
+break;
+  case EL2:
+trap = isWfe? hcr.twe : hcr.twi;
+break;
+  case EL3:
+trap = isWfe? scr.twe : scr.twi;
+break;
+  default:
+break;
+}
+
+return trap;
+}
+
+Fault
+ArmStaticInst::checkForWFxTrap32(ThreadContext *tc,
+ ExceptionLevel targetEL,
+ bool isWfe) const
+{
+// Check if target exception level is implemented.
+assert(ArmSystem::haveEL(tc, targetEL));
+
+// Check for routing to AArch64: this happens if the
+// target exception level (where the trap will be handled)
+// is using aarch64
+if (ELIs64(tc, targetEL)) {
+return checkForWFxTrap64(tc, targetEL, isWfe);
+}
+
+// Check if processor needs to trap at selected exception level
+bool trap = isWFxTrapping(tc, targetEL, isWfe);
+
+if (trap) {
+uint32_t iss = isWfe? 0x1E1 : /* WFE Instruction syndrome */
+  0x1E0;  /* WFI Instruction syndrome */
+switch (targetEL) {
+  case EL1:
+return std::make_shared(
+machInst, iss,
+EC_TRAPPED_WFI_WFE, mnemonic);
+  case EL2:
+return std::make_shared(machInst, iss,
+EC_TRAPPED_WFI_WFE);
+  case EL3:
+return std::make_shared(machInst, iss,
+   EC_TRAPPED_WFI_WFE);
+  default:
+panic("Unrecognized Exception Level: %d\n", targetEL);
+}
+}
+
+return NoFault;
+}
+
+Fault
+ArmStaticInst::checkForWFxTrap64(ThreadContext *tc,
+ ExceptionLevel targetEL,
+ bool isWfe) const
+{
+// Check if target exception level is implemented.
+assert(ArmSystem::haveEL(tc, targetEL));
+
+// Check if processor needs to trap at selected exception level
+bool trap = isWFxTrapping(tc, targetEL, isWfe);
+
+if (trap) {
+uint32_t iss = isWfe? 0x1E1 : /* WFE Instruction syndrome */
+  0x1E0;  /* WFI Instruction syndrome */
+switch (targetEL) {
+  case EL1:
+return std::make_shared(machInst, iss,
+EC_TRAPPED_WFI_WFE);
+  case EL2:
+return std::make_shared(machInst, iss,
+EC_TRAPPED_WFI_WFE);
+  case EL3:
+return std::make_shared(machInst, iss,
+   EC_TRAPPED_WFI_WFE);
+  default:
+panic("Unrecognized Exception Level: %d\n", targetEL);
+}
+}
+
+return NoFault;
+}
+
+Fault
+ArmStaticInst::trapWFx(ThreadContext *tc,
+   CPSR cpsr, SCR scr,
+   bool isWfe) const
+{
+Fault fault = NoFault;
+if (cpsr.el == EL0) {
+fault = checkForWFxTrap32(tc, EL1, isWfe);
+}
+
+if ((fault == NoFault) &&
+ArmSystem::haveEL(tc, EL2) && !inSecureState(scr, cpsr) &&
+((cpsr.el == EL0) || (cpsr.el == EL1))) {
+
+fault = checkForWFxTrap32(tc, EL2, isWfe);
+}
+
+if 

[gem5-dev] Change in public/gem5[master]: arch-arm: Change casting type from reinterpret to static

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/6761

to review the following change.


Change subject: arch-arm: Change casting type from reinterpret to static
..

arch-arm: Change casting type from reinterpret to static

Cosmetic fix: prefer static_cast rather than reinterpret_cast in
hierarchy.

Change-Id: Ic0e5a4df9b18072a6df5ee316f674241074c349a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/faults.cc
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 0293ee1..8d019d5 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -482,7 +482,7 @@
 // extra information. This is used to generate the correct fault  
syndrome

 // information
 if (inst) {
-ArmStaticInst *armInst = reinterpret_cast*>(inst.get());

+ArmStaticInst *armInst = static_cast(inst.get());
 armInst->annotateFault(this);
 }

@@ -672,7 +672,7 @@
 // extra information. This is used to generate the correct fault  
syndrome

 // information
 if (inst)
-reinterpret_cast(inst.get())->annotateFault(this);
+static_cast(inst.get())->annotateFault(this);
 // Save exception syndrome
 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
 setSyndrome(tc, getSyndromeReg64());

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[gem5-dev] Change in public/gem5[master]: arch-arm: Instruction size methods in StaticInst class

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/6781

to review the following change.


Change subject: arch-arm: Instruction size methods in StaticInst class
..

arch-arm: Instruction size methods in StaticInst class

This patch is introducing some methods in StaticInst so that is possible
to get the instruction size in byte of the instruction (can be 2 bytes
in Thumb) and the correct opcode (The machInst field contains some
appended metadata)

Change-Id: I3bed4d9fd7c77feaeded40ded192afe445d306ea
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/insts/static_inst.hh
1 file changed, 19 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/insts/static_inst.hh  
b/src/arch/arm/insts/static_inst.hh

index 431e81b..4595646 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -423,6 +423,25 @@
 {
 return intWidth;
 }
+
+/** Returns the byte size of current instruction */
+ssize_t
+instSize() const
+{
+return (!machInst.thumb || machInst.bigThumb) ? 4 : 2;
+}
+
+/**
+ * Returns the real encoding of the instruction:
+ * the machInst field is in fact always 64 bit wide and
+ * contains some instruction metadata, which means it differs
+ * from the real opcode.
+ */
+MachInst
+encoding() const
+{
+return static_cast(mask(instSize() * 8));
+}
 };
 }


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[gem5-dev] Change in public/gem5[master]: arch-arm: Instruction size methods in StaticInst class

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/6781 )


Change subject: arch-arm: Instruction size methods in StaticInst class
..

arch-arm: Instruction size methods in StaticInst class

This patch is introducing some methods in StaticInst so that is possible
to get the instruction size in byte of the instruction (can be 2 bytes
in Thumb) and the correct opcode (The machInst field contains some
appended metadata)

Change-Id: I3bed4d9fd7c77feaeded40ded192afe445d306ea
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/6781
Maintainer: Andreas Sandberg 
---
M src/arch/arm/insts/static_inst.hh
1 file changed, 19 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/insts/static_inst.hh  
b/src/arch/arm/insts/static_inst.hh

index 431e81b..4595646 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -423,6 +423,25 @@
 {
 return intWidth;
 }
+
+/** Returns the byte size of current instruction */
+ssize_t
+instSize() const
+{
+return (!machInst.thumb || machInst.bigThumb) ? 4 : 2;
+}
+
+/**
+ * Returns the real encoding of the instruction:
+ * the machInst field is in fact always 64 bit wide and
+ * contains some instruction metadata, which means it differs
+ * from the real opcode.
+ */
+MachInst
+encoding() const
+{
+return static_cast(mask(instSize() * 8));
+}
 };
 }


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Gerrit-Change-Id: I3bed4d9fd7c77feaeded40ded192afe445d306ea
Gerrit-Change-Number: 6781
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[gem5-dev] Change in public/gem5[master]: arch-arm: Change casting type from reinterpret to static

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/6761 )


Change subject: arch-arm: Change casting type from reinterpret to static
..

arch-arm: Change casting type from reinterpret to static

Cosmetic fix: prefer static_cast rather than reinterpret_cast in
hierarchy.

Change-Id: Ic0e5a4df9b18072a6df5ee316f674241074c349a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/6761
Maintainer: Andreas Sandberg 
---
M src/arch/arm/faults.cc
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 0293ee1..8d019d5 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -482,7 +482,7 @@
 // extra information. This is used to generate the correct fault  
syndrome

 // information
 if (inst) {
-ArmStaticInst *armInst = reinterpret_cast*>(inst.get());

+ArmStaticInst *armInst = static_cast(inst.get());
 armInst->annotateFault(this);
 }

@@ -672,7 +672,7 @@
 // extra information. This is used to generate the correct fault  
syndrome

 // information
 if (inst)
-reinterpret_cast(inst.get())->annotateFault(this);
+static_cast(inst.get())->annotateFault(this);
 // Save exception syndrome
 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
 setSyndrome(tc, getSyndromeReg64());

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Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ic0e5a4df9b18072a6df5ee316f674241074c349a
Gerrit-Change-Number: 6761
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in public/gem5[master]: arch-arm: ISB instruction is not Serializing

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/5701

to look at the new patch set (#2).

Change subject: arch-arm: ISB instruction is not Serializing
..

arch-arm: ISB instruction is not Serializing

ISB instruction is not a Serializing Instruction: it is flushing the
pipeline (following instructions), but there is no guarantee for the
processor to complete all modifications to flags and general-purpose
registers by previous instructions before the next instruction is
executed. The correct behaviour is guaranteed by either a
preceeding sw DSB barrier or by gem5 IsSerializeAfter flag for
MCR instruction.

Change-Id: I05e61b4cf9f01113d95b1502c996d04cbd69b759
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/misc64.isa
2 files changed, 2 insertions(+), 2 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I05e61b4cf9f01113d95b1502c996d04cbd69b759
Gerrit-Change-Number: 5701
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Assignee: Giacomo Gabrielli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-CC: Giacomo Gabrielli 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Interface for the ArmStaticInst intWidth field

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/5661

to review the following change.


Change subject: arch-arm: Interface for the ArmStaticInst intWidth field
..

arch-arm: Interface for the ArmStaticInst intWidth field

ARMv8 Tracers might want to be able to read the intWidth field of the
ArmStaticInst object. The field is specifying the bit width of the
integer registers used by the current instruction.

Change-Id: Iaee3123823a2c7380917001c453377c1c12e54a7
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/insts/static_inst.hh
1 file changed, 7 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/insts/static_inst.hh  
b/src/arch/arm/insts/static_inst.hh

index 5c6a315..431e81b 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, 2016 ARM Limited
+ * Copyright (c) 2010-2013,2016-2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -417,6 +417,12 @@
   public:
 virtual void
 annotateFault(ArmFault *fault) {}
+
+uint8_t
+getIntWidth() const
+{
+return intWidth;
+}
 };
 }


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[gem5-dev] Change in public/gem5[master]: arch-arm: Fix MSR/MRS disassemble

[Giacomo Travaglini (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/5861

to review the following change.


Change subject: arch-arm: Fix MSR/MRS disassemble
..

arch-arm: Fix MSR/MRS disassemble

This patch is fixing the Aarch64 MSR/MRS disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the system register name

Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/isa/templates/misc64.isa
5 files changed, 132 insertions(+), 13 deletions(-)



diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 465bafa..b40de02 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -53,7 +53,7 @@

 std::string
 RegRegRegImmOp64::generateDisassembly(
-Addr pc, const SymbolTable *symtab) const
+Addr pc, const SymbolTable *symtab) const
 {
 std::stringstream ss;
 printMnemonic(ss, "", false);
@@ -71,3 +71,27 @@
 {
 return csprintf("%-10s (inst %#08x)", "unknown", machInst);
 }
+
+std::string
+MiscRegRegImmOp64::generateDisassembly(
+Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss);
+printMiscReg(ss, dest);
+ss << ", ";
+printIntReg(ss, op1);
+return ss.str();
+}
+
+std::string
+RegMiscRegImmOp64::generateDisassembly(
+Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss);
+printIntReg(ss, dest);
+ss << ", ";
+printMiscReg(ss, op1);
+return ss.str();
+}
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 5a0e182..384d946 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -89,4 +89,38 @@
 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

 };

+class MiscRegRegImmOp64 : public ArmStaticInst
+{
+  protected:
+MiscRegIndex dest;
+IntRegIndex op1;
+uint32_t imm;
+
+MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst,
+  OpClass __opClass, MiscRegIndex _dest,
+  IntRegIndex _op1, uint32_t _imm) :
+ArmStaticInst(mnem, _machInst, __opClass),
+dest(_dest), op1(_op1), imm(_imm)
+{}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+class RegMiscRegImmOp64 : public ArmStaticInst
+{
+  protected:
+IntRegIndex dest;
+MiscRegIndex op1;
+uint32_t imm;
+
+RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
+  OpClass __opClass, IntRegIndex _dest,
+  MiscRegIndex _op1, uint32_t _imm) :
+ArmStaticInst(mnem, _machInst, __opClass),
+dest(_dest), op1(_op1), imm(_imm)
+{}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
 #endif
diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 2c33e24..d640caf 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -369,12 +369,13 @@
 return new Dczva(machInst, rt, (IntRegIndex)  
miscReg, iss);


 if (read) {
-StaticInstPtr si = new Mrs64(machInst, rt,  
(IntRegIndex) miscReg, iss);
+StaticInstPtr si = new Mrs64(machInst, rt,  
miscReg, iss);

 if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE])
 si->setFlag(StaticInst::IsUnverifiable);
 return si;
-} else
-return new Msr64(machInst, (IntRegIndex)  
miscReg, rt, iss);

+} else {
+return new Msr64(machInst, miscReg, rt, iss);
+}
 } else if  
(miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {

 std::string full_mnem = csprintf("%s %s",
 read ? "mrs" : "msr", miscRegName[miscReg]);
diff --git a/src/arch/arm/isa/insts/data64.isa  
b/src/arch/arm/isa/insts/data64.isa

index d0ee439..887130f 100644
--- 

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix MCR/MRC disassemble

[Giacomo Travaglini (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/5862

to review the following change.


Change subject: arch-arm: Fix MCR/MRC disassemble
..

arch-arm: Fix MCR/MRC disassemble

This patch is fixing the Aarch32 MCR/MRC disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the coprocessor register name

Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/insts/misc.cc
1 file changed, 2 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 059f86f..ec1b935 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -259,10 +259,9 @@
 {
 std::stringstream ss;
 printMnemonic(ss);
-printIntReg(ss, dest);
+printMiscReg(ss, dest);
 ss << ", ";
 printIntReg(ss, op1);
-ccprintf(ss, ", #%d", imm);
 return ss.str();
 }

@@ -273,8 +272,7 @@
 printMnemonic(ss);
 printIntReg(ss, dest);
 ss << ", ";
-printIntReg(ss, op1);
-ccprintf(ss, ", #%d", imm);
+printMiscReg(ss, op1);
 return ss.str();
 }


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Gerrit-Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Gerrit-Change-Number: 5862
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in public/gem5[master]: arch-arm: HVC instruction undefined in secure EL1

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/5921

to review the following change.


Change subject: arch-arm: HVC instruction undefined in secure EL1
..

arch-arm: HVC instruction undefined in secure EL1

Since EL2 is not available in secure mode, any HVC call from secure mode
should be treated as undefined. This behaviour was implemented in
aarch32 HVC but not in 64 bit version

Change-Id: Ibaa4d8b1e8fe01d2ba3ef07494c09a4d3e7e87b0
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa/insts/misc64.isa
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/isa/insts/misc64.isa  
b/src/arch/arm/isa/insts/misc64.isa

index 58f08f5..00724c0 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -53,7 +53,7 @@
 SCR scr = Scr64;

 if (!ArmSystem::haveVirtualization(xc->tcBase()) ||
-(ArmSystem::haveSecurity(xc->tcBase()) && !scr.hce)) {
+(ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
 fault = disabledFault();
 } else {
 fault = std::make_shared(machInst, bits(machInst,  
20, 5));


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[gem5-dev] Change in public/gem5[master]: arch-arm: Fix MSR/MRS disassemble

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5861 )


Change subject: arch-arm: Fix MSR/MRS disassemble
..

arch-arm: Fix MSR/MRS disassemble

This patch is fixing the Aarch64 MSR/MRS disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the system register name

Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/5861
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/isa/templates/misc64.isa
5 files changed, 132 insertions(+), 13 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 465bafa..b40de02 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -53,7 +53,7 @@

 std::string
 RegRegRegImmOp64::generateDisassembly(
-Addr pc, const SymbolTable *symtab) const
+Addr pc, const SymbolTable *symtab) const
 {
 std::stringstream ss;
 printMnemonic(ss, "", false);
@@ -71,3 +71,27 @@
 {
 return csprintf("%-10s (inst %#08x)", "unknown", machInst);
 }
+
+std::string
+MiscRegRegImmOp64::generateDisassembly(
+Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss);
+printMiscReg(ss, dest);
+ss << ", ";
+printIntReg(ss, op1);
+return ss.str();
+}
+
+std::string
+RegMiscRegImmOp64::generateDisassembly(
+Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss);
+printIntReg(ss, dest);
+ss << ", ";
+printMiscReg(ss, op1);
+return ss.str();
+}
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 5a0e182..384d946 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -89,4 +89,38 @@
 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

 };

+class MiscRegRegImmOp64 : public ArmStaticInst
+{
+  protected:
+MiscRegIndex dest;
+IntRegIndex op1;
+uint32_t imm;
+
+MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst,
+  OpClass __opClass, MiscRegIndex _dest,
+  IntRegIndex _op1, uint32_t _imm) :
+ArmStaticInst(mnem, _machInst, __opClass),
+dest(_dest), op1(_op1), imm(_imm)
+{}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+class RegMiscRegImmOp64 : public ArmStaticInst
+{
+  protected:
+IntRegIndex dest;
+MiscRegIndex op1;
+uint32_t imm;
+
+RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
+  OpClass __opClass, IntRegIndex _dest,
+  MiscRegIndex _op1, uint32_t _imm) :
+ArmStaticInst(mnem, _machInst, __opClass),
+dest(_dest), op1(_op1), imm(_imm)
+{}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
 #endif
diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 2c33e24..d640caf 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -369,12 +369,13 @@
 return new Dczva(machInst, rt, (IntRegIndex)  
miscReg, iss);


 if (read) {
-StaticInstPtr si = new Mrs64(machInst, rt,  
(IntRegIndex) miscReg, iss);
+StaticInstPtr si = new Mrs64(machInst, rt,  
miscReg, iss);

 if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE])
 si->setFlag(StaticInst::IsUnverifiable);
 return si;
-} else
-return new Msr64(machInst, (IntRegIndex)  
miscReg, rt, iss);

+} else {
+return new Msr64(machInst, miscReg, rt, iss);
+}
 } else 

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix MCR/MRC disassemble

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5862 )


Change subject: arch-arm: Fix MCR/MRC disassemble
..

arch-arm: Fix MCR/MRC disassemble

This patch is fixing the Aarch32 MCR/MRC disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the coprocessor register name

Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/5862
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/insts/misc.cc
1 file changed, 2 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 059f86f..ec1b935 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -259,10 +259,9 @@
 {
 std::stringstream ss;
 printMnemonic(ss);
-printIntReg(ss, dest);
+printMiscReg(ss, dest);
 ss << ", ";
 printIntReg(ss, op1);
-ccprintf(ss, ", #%d", imm);
 return ss.str();
 }

@@ -273,8 +272,7 @@
 printMnemonic(ss);
 printIntReg(ss, dest);
 ss << ", ";
-printIntReg(ss, op1);
-ccprintf(ss, ", #%d", imm);
+printMiscReg(ss, op1);
 return ss.str();
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Gerrit-Change-Number: 5862
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: scons: Build error introduced by site_tools/default.py

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/5941



Change subject: scons: Build error introduced by site_tools/default.py
..

scons: Build error introduced by site_tools/default.py

One of the latest commits affecting the build system introduced a change
in the environment setting: rather than using the ENV dictionary,
environment key-val pairs were saved directly into the class. This
patch reverts that behaviour.

Change-Id: If206ba0a34ac8c35695a493cb90654b7ec81971b
Signed-off-by: Giacomo Travaglini 
---
M site_scons/site_tools/default.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/site_scons/site_tools/default.py  
b/site_scons/site_tools/default.py

index 73c4a9e..9d02ab7 100644
--- a/site_scons/site_tools/default.py
+++ b/site_scons/site_tools/default.py
@@ -64,7 +64,7 @@
 for key,val in sorted(os.environ.iteritems()):
 if key in use_vars or \
 any([key.startswith(prefix) for prefix in use_prefixes]):
-env[key] = val
+env['ENV'][key] = val

 # Tell scons to avoid implicit command dependencies to avoid issues
 # with the param wrappes being compiled twice (see

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[gem5-dev] Change in public/gem5[master]: scons: Build error introduced by site_tools/default.py

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5941 )


Change subject: scons: Build error introduced by site_tools/default.py
..

scons: Build error introduced by site_tools/default.py

One of the latest commits affecting the build system introduced a change
in the environment setting: rather than using the ENV dictionary,
environment key-val pairs were saved directly into the class. This
patch reverts that behaviour.

Change-Id: If206ba0a34ac8c35695a493cb90654b7ec81971b
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/5941
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M site_scons/site_tools/default.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/site_scons/site_tools/default.py  
b/site_scons/site_tools/default.py

index 73c4a9e..9d02ab7 100644
--- a/site_scons/site_tools/default.py
+++ b/site_scons/site_tools/default.py
@@ -64,7 +64,7 @@
 for key,val in sorted(os.environ.iteritems()):
 if key in use_vars or \
 any([key.startswith(prefix) for prefix in use_prefixes]):
-env[key] = val
+env['ENV'][key] = val

 # Tell scons to avoid implicit command dependencies to avoid issues
 # with the param wrappes being compiled twice (see

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Gerrit-Change-Id: If206ba0a34ac8c35695a493cb90654b7ec81971b
Gerrit-Change-Number: 5941
Gerrit-PatchSet: 2
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[gem5-dev] Change in public/gem5[master]: arch-arm: ISB instruction is not Serializing

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/5701

to review the following change.


Change subject: arch-arm: ISB instruction is not Serializing
..

arch-arm: ISB instruction is not Serializing

ISB instruction is not a Serializing Instruction: it is flushing the
pipeline (following instructions), but there is no guarantee for the
processor to complete all modifications to flags and general-purpose
registers by previous instructions before the next instruction is
executed.

Change-Id: I05e61b4cf9f01113d95b1502c996d04cbd69b759
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/misc64.isa
2 files changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/isa/insts/misc.isa  
b/src/arch/arm/isa/insts/misc.isa

index 80ad6cd..89c9500 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -1074,7 +1074,7 @@
 isbIop = InstObjParams("isb", "Isb", "ImmOp",
  {"code": isbCode,
"predicate_test": predicateTest},
-['IsSerializeAfter', 'IsSquashAfter'])
+['IsSquashAfter'])
 header_output += ImmOpDeclare.subst(isbIop)
 decoder_output += ImmOpConstructor.subst(isbIop)
 exec_output += PredOpExecute.subst(isbIop)
diff --git a/src/arch/arm/isa/insts/misc64.isa  
b/src/arch/arm/isa/insts/misc64.isa

index 58f08f5..73625dc 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -140,7 +140,7 @@
 exec_output += BasicExecute.subst(unknown64Iop)

 isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst", "",
-   ['IsSerializeAfter', 'IsSquashAfter'])
+   ['IsSquashAfter'])
 header_output += BasicDeclare.subst(isbIop)
 decoder_output += BasicConstructor64.subst(isbIop)
 exec_output += BasicExecute.subst(isbIop)

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[gem5-dev] Change in public/gem5[master]: cpu: MinorCPU handling IsSquashAfter flag

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/5702

to review the following change.


Change subject: cpu: MinorCPU handling IsSquashAfter flag
..

cpu: MinorCPU handling IsSquashAfter flag

MinorCPU was not handling IsSquashAfter flagged instructions. The
behaviour was to force a branch (hence enforcing refetching) for
SerializeAfter instructions only. This has now been extended to
SquashAfter in order to correctly support ISB barrier instruction
behaviour.

Change-Id: Ie525b23350b0de121372d3b98b433e36b097d5c4
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/cpu/minor/execute.cc
1 file changed, 4 insertions(+), 3 deletions(-)



diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index a38a767..7b76ca2 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -219,13 +219,14 @@
 const TheISA::PCState _before = inst->pc;
 TheISA::PCState target = thread->pcState();

-/* Force a branch for SerializeAfter instructions at the end of  
micro-op

- *  sequence when we're not suspended */
+/* Force a branch for SerializeAfter/SquashAfter instructions
+ * at the end of micro-op sequence when we're not suspended */
 bool force_branch = thread->status() != ThreadContext::Suspended &&
 !inst->isFault() &&
 inst->isLastOpInInst() &&
 (inst->staticInst->isSerializeAfter() ||
-inst->staticInst->isIprAccess());
+ inst->staticInst->isSquashAfter() ||
+ inst->staticInst->isIprAccess());

 DPRINTF(Branch, "tryToBranch before: %s after: %s%s\n",
 pc_before, target, (force_branch ? " (forcing)" : ""));

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Gerrit-Change-Id: Ie525b23350b0de121372d3b98b433e36b097d5c4
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[gem5-dev] Change in public/gem5[master]: arch-arm: Corrected encoding for T32 HVC instruction

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/5541



Change subject: arch-arm: Corrected encoding for T32 HVC instruction
..

arch-arm: Corrected encoding for T32 HVC instruction

This patch corrects the encoding of the HVC (Hypervisor Call) for the
T32 instruction set.

Change-Id: I6f77eaf5c586697e9ccd588419c61e6d90c6c7bf
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Chuan Zhu 
---
M src/arch/arm/isa/formats/branch.isa
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/isa/formats/branch.isa  
b/src/arch/arm/isa/formats/branch.isa

index 513506d..df85b08 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010, 2012-2013 ARM Limited
+// Copyright (c) 2010,2012-2013,2017 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -247,7 +247,7 @@
 }
 }
 }
-  case 0xfe:
+  case 0x7e:
 {
 uint32_t imm16 = (bits(machInst, 19, 16) << 12) |
  (bits(machInst, 11,  0) <<  0);

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[gem5-dev] Change in public/gem5[master]: arm: Change access permission in TPIDRURO and TPIDRURW

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/6381 )


Change subject: arm: Change access permission in TPIDRURO and TPIDRURW
..

arm: Change access permission in TPIDRURO and TPIDRURW

This patch corrects the TPIDRURO and TPIDRURW access flags: TPIDRURO is
now readable in secure user mode, an TPIDRURW is readable and writable
in secure user mode.

Change-Id: I6293d9a3bcc7adc0f655bf98d29aca51eca5a002
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-by: Chuan Zhu 
Reviewed-on: https://gem5-review.googlesource.com/6381
Maintainer: Andreas Sandberg 
---
M src/arch/arm/miscregs.cc
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 826e567..ece5524 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -686,13 +686,13 @@
 // MISCREG_TPIDRURW_NS
 bitset(string("11001111")),
 // MISCREG_TPIDRURW_S
-bitset(string("001100110011")),
+bitset(string("0011001100110011")),
 // MISCREG_TPIDRURO
 bitset(string("00010001")),
 // MISCREG_TPIDRURO_NS
 bitset(string("110011010111")),
 // MISCREG_TPIDRURO_S
-bitset(string("001100110011")),
+bitset(string("0011001100010011")),
 // MISCREG_TPIDRPRW
 bitset(string("00010001")),
 // MISCREG_TPIDRPRW_NS

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I6293d9a3bcc7adc0f655bf98d29aca51eca5a002
Gerrit-Change-Number: 6381
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: arm: Enable ns registers access in secure mode

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/6201 )


Change subject: arm: Enable ns registers access in secure mode
..

arm: Enable ns registers access in secure mode

Arm security extension introduced register banking between secure and
non-secure mode. This has been removed in armv8 using AArch64 in EL3,
where the decoded register is by default the non-secure version. Using
non-secure register infos(flags) was preventing secure execution to
access the register with the MRC/MCR at EL1.
The patch updates the following banked registers' flags so that their
non-secure version can be accessed in secure mode:

MISCREG_CSSELR, MISCREG_SCTLR, MISCREG_ACTLR, MISCREG_TTBR0,
MISCREG_TTBR1, MISCREG_TTBCR, MISCREG_DACR, MISCREG_DFSR, MISCREG_IFSR,
MISCREG_ADFSR, MISCREG_AIFSR, MISCREG_DFAR, MISCREG_IFAR, MISCREG_PAR,
MISCREG_PRRR, MISCREG_MAIR0, MISCREG_NMRR, MISCREG_MAIR1,
MISCREG_AMAIR0, MISCREG_AMAIR1, MISCREG_VBAR, MISCREG_CONTEXTIDR,
MISCREG_TPIDRURW, MISCREG_TPIDRURO, MISCREG_TPIDRPRW, MISCREG_CNTP_TVAL,
MISCREG_CNTP_CTL, MISCREG_CNTP_CVAL

For those registers the following permission bits have been set:

MISCREG_PRI_S_RD
MISCREG_PRI_S_WR

Change-Id: Ib881c526e75d69e313f8ef66eb78fc704de6bf59
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Giacomo Gabrielli 
Reviewed-on: https://gem5-review.googlesource.com/6201
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/miscregs.cc
1 file changed, 28 insertions(+), 28 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index d31c84c..d08f751 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -344,7 +344,7 @@
 // MISCREG_CSSELR
 bitset(string("00010001")),
 // MISCREG_CSSELR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_CSSELR_S
 bitset(string("001100110011")),
 // MISCREG_VPIDR
@@ -354,13 +354,13 @@
 // MISCREG_SCTLR
 bitset(string("00010001")),
 // MISCREG_SCTLR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_SCTLR_S
 bitset(string("001100110011")),
 // MISCREG_ACTLR
 bitset(string("00010001")),
 // MISCREG_ACTLR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_ACTLR_S
 bitset(string("001100110011")),
 // MISCREG_CPACR
@@ -388,19 +388,19 @@
 // MISCREG_TTBR0
 bitset(string("00010001")),
 // MISCREG_TTBR0_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_TTBR0_S
 bitset(string("001100110011")),
 // MISCREG_TTBR1
 bitset(string("00010001")),
 // MISCREG_TTBR1_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_TTBR1_S
 bitset(string("001100110011")),
 // MISCREG_TTBCR
 bitset(string("00010001")),
 // MISCREG_TTBCR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_TTBCR_S
 bitset(string("001100110011")),
 // MISCREG_HTCR
@@ -410,31 +410,31 @@
 // MISCREG_DACR
 bitset(string("00010001")),
 // MISCREG_DACR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_DACR_S
 bitset(string("001100110011")),
 // MISCREG_DFSR
 bitset(string("00010001")),
 // MISCREG_DFSR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_DFSR_S
 bitset(string("001100110011")),
 // MISCREG_IFSR
 bitset(string("00010001")),
 // MISCREG_IFSR_NS
-bitset(string("110011001111")),
+bitset(string("11001111")),
 // MISCREG_IFSR_S
 bitset(string("001100110011")),
 // MISCREG_ADFSR
 bitset(string("00010100")),
 // MISCREG_ADFSR_NS
-bitset(string("1100110011100100")),
+bitset(string("110011100100")),
 // MISCREG_ADFSR_S
 bitset(string("0011001100100100")),
 // MISCREG_AIFSR
 bitset(string("00010100")),
 // MISCREG_AIFSR_NS
-bitset(string("1100110011100100")),
+bitset(string("110011100100")),
 // MISCREG_AIFSR_S
 bitset(string("0011001100100100")),
 // MISCREG_HADFSR
@@ -446,13 +446,13 @@
 // MISCREG_DFAR
 bitset(string("00010001")),
 // MISCREG_DFAR_NS
-

[gem5-dev] Change in public/gem5[master]: arch-arm: Removing Serializing flag from ISB

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/5701

to look at the new patch set (#3).

Change subject: arch-arm: Removing Serializing flag from ISB
..

arch-arm: Removing Serializing flag from ISB

ISB Serializing behaviour is guaranteed by IsSquashAfter,
which is inherently serializing; when instruction is commited,
consecutive instructions are flushed and refetched.

Change-Id: I05e61b4cf9f01113d95b1502c996d04cbd69b759
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/misc64.isa
2 files changed, 2 insertions(+), 2 deletions(-)


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Gerrit-Change-Id: I05e61b4cf9f01113d95b1502c996d04cbd69b759
Gerrit-Change-Number: 5701
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Assignee: Giacomo Gabrielli 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: base: Introducing utility for writing raw data in png format

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5181 )


Change subject: base: Introducing utility for writing raw data in png format
..

base: Introducing utility for writing raw data in png format

Originally it was possible to use a Bitmap writer class for dumping a
framebuffer snapshot in a .bmp file. This patch enables you to choose
another format.  In particular it implements the writing of PNG Images
using libpng library.  The latter has to be already installed in your
machine, otherwise gem5 will default to the Bitmap format.  This
configurable writer has been introduced in the VNC frame dumping mechanism,
which is storing changed frame buffers from the VNC server

Change-Id: Id7e5763c82235f1ce90381c8486b85a7cce734ce
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/5181
Reviewed-by: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
---
M SConstruct
A src/base/Graphics.py
M src/base/SConscript
R src/base/bmpwriter.cc
R src/base/bmpwriter.hh
A src/base/imgwriter.cc
A src/base/imgwriter.hh
A src/base/pngwriter.cc
C src/base/pngwriter.hh
M src/base/vnc/Vnc.py
M src/base/vnc/vncinput.cc
M src/base/vnc/vncinput.hh
M src/base/vnc/vncserver.cc
M src/base/vnc/vncserver.hh
M src/dev/arm/hdlcd.hh
M src/dev/arm/pl111.hh
16 files changed, 509 insertions(+), 103 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/SConstruct b/SConstruct
index 95efb83..230232d 100755
--- a/SConstruct
+++ b/SConstruct
@@ -1,6 +1,6 @@
 # -*- mode:python -*-

-# Copyright (c) 2013, 2015, 2016 ARM Limited
+# Copyright (c) 2013, 2015-2017 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -1134,6 +1134,14 @@
 print "Warning: Header file  not found."
 print " This host has no IEEE FP rounding mode control."

+# Check for  (libpng library needed if wanting to dump
+# frame buffer image in png format)
+have_png = conf.CheckHeader('png.h', '<>')
+if not have_png:
+print "Warning: Header file  not found."
+print " This host has no libpng library."
+print " Disabling support for PNG framebuffers."
+
 # Check if we should enable KVM-based hardware virtualization. The API
 # we rely on exists since version 2.6.36 of the kernel, but somehow
 # the KVM_API_VERSION does not reflect the change. We test for one of
@@ -1278,8 +1286,11 @@
  False),
 BoolVariable('USE_POSIX_CLOCK', 'Use POSIX Clocks', have_posix_clock),
 BoolVariable('USE_FENV', 'Use  IEEE mode control', have_fenv),
-BoolVariable('CP_ANNOTATE', 'Enable critical path annotation  
capability', False),
-BoolVariable('USE_KVM', 'Enable hardware virtualized (KVM) CPU  
models', have_kvm),

+BoolVariable('USE_PNG',  'Enable support for PNG images', have_png),
+BoolVariable('CP_ANNOTATE', 'Enable critical path annotation  
capability',

+ False),
+BoolVariable('USE_KVM', 'Enable hardware virtualized (KVM) CPU models',
+ have_kvm),
 BoolVariable('USE_TUNTAP',
  'Enable using a tap device to bridge to the host network',
  have_tuntap),
@@ -1293,7 +1304,8 @@
 # These variables get exported to #defines in config/*.hh (see  
src/SConscript).
 export_vars +=  
['USE_FENV', 'SS_COMPATIBLE_FP', 'TARGET_ISA', 'TARGET_GPU_ISA',

 'CP_ANNOTATE', 'USE_POSIX_CLOCK', 'USE_KVM', 'USE_TUNTAP',
-'PROTOCOL', 'HAVE_PROTOBUF', 'HAVE_PERF_ATTR_EXCLUDE_HOST']
+'PROTOCOL', 'HAVE_PROTOBUF', 'HAVE_PERF_ATTR_EXCLUDE_HOST',
+'USE_PNG']

 ###
 #
@@ -1486,6 +1498,14 @@
 print "Warning: No IEEE FP rounding mode control in", variant_dir  
+ "."
 print " FP results may deviate slightly from other  
platforms."


+if not have_png and env['USE_PNG']:
+print "Warning:  not available; " \
+  "forcing USE_PNG to False in", variant_dir + "."
+env['USE_PNG'] = False
+
+if env['USE_PNG']:
+env.Append(LIBS=['png'])
+
 if env['EFENCE']:
 env.Append(LIBS=['efence'])

diff --git a/src/base/Graphics.py b/src/base/Graphics.py
new file mode 100644
index 000..c42882e
--- /dev/null
+++ b/src/base/Graphics.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2017 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the 

[gem5-dev] Change in public/gem5[master]: vnc: Default image writer type set to Auto

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5182 )


Change subject: vnc: Default image writer type set to Auto
..

vnc: Default image writer type set to Auto

This commit modifies the default behaviour of the vnc frame dumping
process: rather than using 'Bitmap' as a default parameter value, it is
using 'Auto'.  Auto parameter is letting gem5 to choose the most
efficient image format among the available ones.

Change-Id: I3c8e2b5a34a5925d24892880ac362dfe38de36e3
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/5182
Reviewed-by: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
---
M src/base/vnc/Vnc.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/base/vnc/Vnc.py b/src/base/vnc/Vnc.py
index 0aed0dc..e440d10 100644
--- a/src/base/vnc/Vnc.py
+++ b/src/base/vnc/Vnc.py
@@ -45,7 +45,7 @@
 cxx_header = "base/vnc/vncinput.hh"
 frame_capture = Param.Bool(False, "capture changed frames to files")
 img_format = Param.ImageFormat(
-"Bitmap", "Format of the dumped Framebuffer"
+"Auto", "Format of the dumped Framebuffer"
 )

 class VncServer(VncInput):

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I3c8e2b5a34a5925d24892880ac362dfe38de36e3
Gerrit-Change-Number: 5182
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: dev: Using Configurable image writer in HDLcd

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5183 )


Change subject: dev: Using Configurable image writer in HDLcd
..

dev: Using Configurable image writer in HDLcd

The fixed image writer (which was dumping .bmp images only) has been
replaced by the configurable one in HDLcd device.  Default format is
Auto, which gives gem5 the freedom to choose the format it prefers.

Change-Id: I0643266556bb10b43cdebd628f6daa2cd5e105dd
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/5183
Reviewed-by: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
---
M src/dev/arm/RealView.py
M src/dev/arm/hdlcd.cc
M src/dev/arm/hdlcd.hh
3 files changed, 17 insertions(+), 6 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 51aa1cf..08145bf 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -56,6 +56,7 @@
 from EnergyCtrl import EnergyCtrl
 from ClockDomain import SrcClockDomain
 from SubSystem import SubSystem
+from Graphics import ImageFormat

 # Platforms with KVM support should generally use in-kernel GIC
 # emulation. Use a GIC model that automatically switches between
@@ -298,7 +299,10 @@
 "selector order in some kernels")
 workaround_dma_line_count = Param.Bool(True, "Workaround incorrect "
"DMA line count (off by 1)")
-enable_capture = Param.Bool(True, "capture frame to  
system.framebuffer.bmp")

+enable_capture = Param.Bool(True, "capture frame to "
+  "system.framebuffer.{extension}")
+frame_format = Param.ImageFormat("Auto",
+ "image format of the captured frame")

 pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range")

diff --git a/src/dev/arm/hdlcd.cc b/src/dev/arm/hdlcd.cc
index 98f2a3d..20dc7d4 100644
--- a/src/dev/arm/hdlcd.cc
+++ b/src/dev/arm/hdlcd.cc
@@ -47,6 +47,7 @@
 #include "debug/HDLcd.hh"
 #include "dev/arm/amba_device.hh"
 #include "dev/arm/base_gic.hh"
+#include "enums/ImageFormat.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/HDLcd.hh"
@@ -85,11 +86,13 @@

   virtRefreshEvent([this]{ virtRefresh(); }, name()),
   // Other
-  bmp(), pic(NULL), conv(PixelConverter::rgba_le),
+  imgFormat(p->frame_format), pic(NULL),  
conv(PixelConverter::rgba_le),

   pixelPump(*this, *p->pxl_clk, p->pixel_chunk)
 {
 if (vnc)
 vnc->setFrameBuffer();
+
+imgWriter = createImgWriter(imgFormat, );
 }

 HDLcd::~HDLcd()
@@ -572,13 +575,14 @@
 if (enableCapture) {
 if (!pic) {
 pic = simout.create(
-csprintf("%s.framebuffer.bmp", sys->name()),
+csprintf("%s.framebuffer.%s",
+ sys->name(), imgWriter->getImgExtension()),
 true);
 }

 assert(pic);
 pic->stream()->seekp(0);
-bmp.write(*pic->stream());
+imgWriter->write(*pic->stream());
 }
 }

diff --git a/src/dev/arm/hdlcd.hh b/src/dev/arm/hdlcd.hh
index dd52e20..f737710 100644
--- a/src/dev/arm/hdlcd.hh
+++ b/src/dev/arm/hdlcd.hh
@@ -79,8 +79,8 @@
 #include 
 #include 

-#include "base/bmpwriter.hh"
 #include "base/framebuffer.hh"
+#include "base/imgwriter.hh"
 #include "base/output.hh"
 #include "dev/arm/amba_device.hh"
 #include "dev/pixelpump.hh"
@@ -350,7 +350,10 @@
 EventFunctionWrapper virtRefreshEvent;

 /** Helper to write out bitmaps */
-BmpWriter bmp;
+std::unique_ptr imgWriter;
+
+/** Image Format */
+Enums::ImageFormat imgFormat;

 /** Picture of what the current frame buffer looks like */
 OutputStream *pic;

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I0643266556bb10b43cdebd628f6daa2cd5e105dd
Gerrit-Change-Number: 5183
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Fix StaticInst encoding() method

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/6881

to review the following change.


Change subject: arch-arm: Fix StaticInst encoding() method
..

arch-arm: Fix StaticInst encoding() method

The previously introduced method was missing the machInst value
to be masked.

Change-Id: Ic722f7cc2abc680da1a1f19c08299338b5c859a6
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Chuan Zhu 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/insts/static_inst.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/insts/static_inst.hh  
b/src/arch/arm/insts/static_inst.hh

index 4595646..7ca1a84 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -440,7 +440,7 @@
 MachInst
 encoding() const
 {
-return static_cast(mask(instSize() * 8));
+return static_cast(machInst & (mask(instSize() * 8)));
 }
 };
 }

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Gerrit-Change-Id: Ic722f7cc2abc680da1a1f19c08299338b5c859a6
Gerrit-Change-Number: 6881
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[gem5-dev] Change in gem5/gem5[master]: scons: Fix --with-ubsan/asan compilation flags

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10181 )


Change subject: scons: Fix --with-ubsan/asan compilation flags
..

scons: Fix --with-ubsan/asan compilation flags

SConstruct was using an undefined env variable; this patch uses the main
Environment variable.

Change-Id: I30ab6b4bbfa6d9a71a30fb33406a799bfb476821
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/10181
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M SConstruct
1 file changed, 8 insertions(+), 8 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/SConstruct b/SConstruct
index 8fde133..b382d33 100755
--- a/SConstruct
+++ b/SConstruct
@@ -481,21 +481,21 @@
 # The address sanitizer is available for gcc >= 4.8
 if GetOption('with_asan'):
 if GetOption('with_ubsan') and \
-compareVersions(env['GCC_VERSION'], '4.9') >= 0:
-env.Append(CCFLAGS=['-fsanitize=address,undefined',
-'-fno-omit-frame-pointer'],
+compareVersions(main['GCC_VERSION'], '4.9') >= 0:
+main.Append(CCFLAGS=['-fsanitize=address,undefined',
+ '-fno-omit-frame-pointer'],
LINKFLAGS='-fsanitize=address,undefined')
 else:
-env.Append(CCFLAGS=['-fsanitize=address',
-'-fno-omit-frame-pointer'],
+main.Append(CCFLAGS=['-fsanitize=address',
+ '-fno-omit-frame-pointer'],
LINKFLAGS='-fsanitize=address')
 # Only gcc >= 4.9 supports UBSan, so check both the version
 # and the command-line option before adding the compiler and
 # linker flags.
 elif GetOption('with_ubsan') and \
-compareVersions(env['GCC_VERSION'], '4.9') >= 0:
-env.Append(CCFLAGS='-fsanitize=undefined')
-env.Append(LINKFLAGS='-fsanitize=undefined')
+compareVersions(main['GCC_VERSION'], '4.9') >= 0:
+main.Append(CCFLAGS='-fsanitize=undefined')
+main.Append(LINKFLAGS='-fsanitize=undefined')

 elif main['CLANG']:
 # Check for a supported version of clang, >= 3.1 is needed to

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I30ab6b4bbfa6d9a71a30fb33406a799bfb476821
Gerrit-Change-Number: 10181
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: sim: Remove trailing dot when assigning a master's name

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10301

to review the following change.


Change subject: sim: Remove trailing dot when assigning a master's name
..

sim: Remove trailing dot when assigning a master's name

This patch fixes the master's name allocation in the system. The error
was occurring when a submaster was not specified in getMasterId: a
trailing separation dot was still added to the master's name.

Change-Id: I0e67900f6fdd36a61900453b55219fc7007d1b05
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/sim/system.cc
1 file changed, 7 insertions(+), 4 deletions(-)



diff --git a/src/sim/system.cc b/src/sim/system.cc
index 911ee5d..74bc94e 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -538,10 +538,13 @@
 std::string
 System::leafMasterName(const SimObject* master, const std::string&  
submaster)

 {
-// Get the full master name by appending the submaster name to
-// the root SimObject master name
-auto master_name = master->name() + "." + submaster;
-return master_name;
+if (submaster.empty()) {
+return master->name();
+} else {
+// Get the full master name by appending the submaster name to
+// the root SimObject master name
+return master->name() + "." + submaster;
+}
 }

 std::string

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Gerrit-Change-Id: I0e67900f6fdd36a61900453b55219fc7007d1b05
Gerrit-Change-Number: 10301
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: sim: Remove trailing dot when assigning a master's name

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10301 )


Change subject: sim: Remove trailing dot when assigning a master's name
..

sim: Remove trailing dot when assigning a master's name

This patch fixes the master's name allocation in the system. The error
was occurring when a submaster was not specified in getMasterId: a
trailing separation dot was still added to the master's name.

Change-Id: I0e67900f6fdd36a61900453b55219fc7007d1b05
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/10301
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/sim/system.cc
1 file changed, 7 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved



diff --git a/src/sim/system.cc b/src/sim/system.cc
index 911ee5d..74bc94e 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -538,10 +538,13 @@
 std::string
 System::leafMasterName(const SimObject* master, const std::string&  
submaster)

 {
-// Get the full master name by appending the submaster name to
-// the root SimObject master name
-auto master_name = master->name() + "." + submaster;
-return master_name;
+if (submaster.empty()) {
+return master->name();
+} else {
+// Get the full master name by appending the submaster name to
+// the root SimObject master name
+return master->name() + "." + submaster;
+}
 }

 std::string

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0e67900f6fdd36a61900453b55219fc7007d1b05
Gerrit-Change-Number: 10301
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: sim, cpu, mem, arch: Introduced MasterInfo data structure

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9781 )


Change subject: sim,cpu,mem,arch: Introduced MasterInfo data structure
..

sim,cpu,mem,arch: Introduced MasterInfo data structure

With this patch a gem5 System will store more info about its Masters.
While it was previously keeping track of the Master name and Master ID
only, it is now adding a per-Master pointer to the SimObject related to
the Master.
This will make it possible for a client to query a System for a Master
using either the master's name or the master's pointer.

Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/9781
Reviewed-by: Jason Lowe-Power 
Maintainer: Nikos Nikoleris 
---
M src/arch/arm/stage2_mmu.cc
M src/arch/x86/pagetable_walker.hh
M src/cpu/base.cc
M src/cpu/checker/cpu.cc
M src/cpu/testers/directedtest/DirectedGenerator.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/traffic_gen/traffic_gen.cc
M src/cpu/trace/trace_cpu.cc
M src/dev/dma_device.cc
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/dispatcher.cc
M src/mem/cache/prefetch/base.cc
M src/mem/external_master.cc
A src/mem/mem_master.hh
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/sim/system.cc
M src/sim/system.hh
19 files changed, 185 insertions(+), 40 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved



diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index 5c28d07..ba820e3 100644
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -51,7 +51,7 @@
 Stage2MMU::Stage2MMU(const Params *p)
 : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
   port(_stage1Tlb->getTableWalker(), p->sys),
-  masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()->name()))
+  masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()))
 {
 // we use the stage-one table walker as the parent of the port,
 // and to get our master id, this is done to keep things
diff --git a/src/arch/x86/pagetable_walker.hh  
b/src/arch/x86/pagetable_walker.hh

index d71db7e..d5aa631 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -203,7 +203,7 @@
 Walker(const Params *params) :
 MemObject(params), port(name() + ".port", this),
 funcState(this, NULL, NULL, true), tlb(NULL),  
sys(params->system),

-masterId(sys->getMasterId(name())),
+masterId(sys->getMasterId(this)),
 numSquashable(params->num_squash_per_cycle),
 startWalkWrapperEvent([this]{ startWalkWrapper(); }, name())
 {
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 4fd804b..c576f1d 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -127,8 +127,8 @@

 BaseCPU::BaseCPU(Params *p, bool is_checker)
 : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id),
-  _instMasterId(p->system->getMasterId(name() + ".inst")),
-  _dataMasterId(p->system->getMasterId(name() + ".data")),
+  _instMasterId(p->system->getMasterId(this, "inst")),
+  _dataMasterId(p->system->getMasterId(this, "data")),
   _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid),
   _switchedOut(p->switched_out),  
_cacheLineSize(p->system->cacheLineSize()),

   interrupts(p->interrupts), profileEvent(NULL),
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 48fcb20..07b6553 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -62,7 +62,7 @@
 void
 CheckerCPU::init()
 {
-masterId = systemPtr->getMasterId(name());
+masterId = systemPtr->getMasterId(this);
 }

 CheckerCPU::CheckerCPU(Params *p)
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.cc  
b/src/cpu/testers/directedtest/DirectedGenerator.cc

index e37868b..2d76b86 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.cc
+++ b/src/cpu/testers/directedtest/DirectedGenerator.cc
@@ -33,7 +33,7 @@

 DirectedGenerator::DirectedGenerator(const Params *p)
 : SimObject(p),
-  masterId(p->system->getMasterId(name()))
+  masterId(p->system->getMasterId(this))
 {
 m_num_cpus = p->num_cpus;
 m_directed_tester = NULL;
diff --git  
a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc  
b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc

index f7513d3..56edd84 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
@@ -93,7 +93,7 @@
   

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Map ID_x_EL1 registers to AArch32 version

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10361 )


Change subject: arch-arm: Map ID_x_EL1 registers to AArch32 version
..

arch-arm: Map ID_x_EL1 registers to AArch32 version

AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts.  Those
registers must be initialized even when the highest Exception Level is
using AArch64.

Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/10361
Maintainer: Andreas Sandberg 
---
M src/arch/arm/isa.cc
M src/arch/arm/miscregs.cc
2 files changed, 38 insertions(+), 25 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 42d1b92..296f8eb 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -118,6 +118,18 @@
 miscRegs[MISCREG_MIDR_EL1] = p->midr;
 miscRegs[MISCREG_VPIDR] = p->midr;

+miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
+miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
+miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
+miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
+miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
+miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
+
+miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
+miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
+miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
+miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+
 if (FullSystem && system->highestELIs64()) {
 // Initialize AArch64 state
 clear64(p);
@@ -208,18 +220,6 @@

 miscRegs[MISCREG_CPACR] = 0;

-miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
-miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
-miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
-miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
-
-miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
-miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
-miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
-miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
-miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
-miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
-
 miscRegs[MISCREG_FPSID] = p->fpsid;

 if (haveLPAE) {
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 6615913..08eb255 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3392,34 +3392,47 @@
 InitReg(MISCREG_REVIDR_EL1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_PFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_PFR0);
 InitReg(MISCREG_ID_PFR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_PFR1);
 InitReg(MISCREG_ID_DFR0_EL1)
   .allPrivileges().exceptUserMode().writes(0)
   .mapsTo(MISCREG_ID_DFR0);
 InitReg(MISCREG_ID_AFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_AFR0);
 InitReg(MISCREG_ID_MMFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR0);
 InitReg(MISCREG_ID_MMFR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR1);
 InitReg(MISCREG_ID_MMFR2_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR2);
 InitReg(MISCREG_ID_MMFR3_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR3);
 InitReg(MISCREG_ID_ISAR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR0);
 InitReg(MISCREG_ID_ISAR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR1);
 InitReg(MISCREG_ID_ISAR2_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR2);
 InitReg(MISCREG_ID_ISAR3_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR3);
 InitReg(MISCREG_ID_ISAR4_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR4);
 InitReg(MISCREG_ID_ISAR5_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR5);
 

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Map ID_x_EL1 registers to AArch32 version

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10361

to review the following change.


Change subject: arch-arm: Map ID_x_EL1 registers to AArch32 version
..

arch-arm: Map ID_x_EL1 registers to AArch32 version

AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts.  Those
registers must be initialized even when the highest Exception Level is
using AArch64.

Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa.cc
M src/arch/arm/miscregs.cc
2 files changed, 38 insertions(+), 25 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 42d1b92..296f8eb 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -118,6 +118,18 @@
 miscRegs[MISCREG_MIDR_EL1] = p->midr;
 miscRegs[MISCREG_VPIDR] = p->midr;

+miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
+miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
+miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
+miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
+miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
+miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
+
+miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
+miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
+miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
+miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+
 if (FullSystem && system->highestELIs64()) {
 // Initialize AArch64 state
 clear64(p);
@@ -208,18 +220,6 @@

 miscRegs[MISCREG_CPACR] = 0;

-miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
-miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
-miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
-miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
-
-miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
-miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
-miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
-miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
-miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
-miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
-
 miscRegs[MISCREG_FPSID] = p->fpsid;

 if (haveLPAE) {
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 6615913..08eb255 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3392,34 +3392,47 @@
 InitReg(MISCREG_REVIDR_EL1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_PFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_PFR0);
 InitReg(MISCREG_ID_PFR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_PFR1);
 InitReg(MISCREG_ID_DFR0_EL1)
   .allPrivileges().exceptUserMode().writes(0)
   .mapsTo(MISCREG_ID_DFR0);
 InitReg(MISCREG_ID_AFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_AFR0);
 InitReg(MISCREG_ID_MMFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR0);
 InitReg(MISCREG_ID_MMFR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR1);
 InitReg(MISCREG_ID_MMFR2_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR2);
 InitReg(MISCREG_ID_MMFR3_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR3);
 InitReg(MISCREG_ID_ISAR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR0);
 InitReg(MISCREG_ID_ISAR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR1);
 InitReg(MISCREG_ID_ISAR2_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR2);
 InitReg(MISCREG_ID_ISAR3_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR3);
 InitReg(MISCREG_ID_ISAR4_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR4);
 InitReg(MISCREG_ID_ISAR5_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR5);
 InitReg(MISCREG_MVFR0_EL1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_MVFR1_EL1)

--
To view, visit https://gem5-review.googlesource.com/10361
To 

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Implement ARMv8.1 TTBR1_EL2 register

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10382

to review the following change.


Change subject: arch-arm: Implement ARMv8.1 TTBR1_EL2 register
..

arch-arm: Implement ARMv8.1 TTBR1_EL2 register

This patch implements the ARMv8.1 TTBR1_EL2 register, which is used for
getting the translation table base address when a Host Operating System
is running at EL2. (HCR_EL2.E2H = 1)

Change-Id: Ic0ab351cae3fd64855eda7c18c8757da0d7b8663
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/miscregs.cc
M src/arch/arm/table_walker.cc
2 files changed, 33 insertions(+), 12 deletions(-)



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 6615913..f3f7476 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3522,7 +3522,7 @@
   .hyp().mon()
   .mapsTo(MISCREG_HTTBR);
 InitReg(MISCREG_TTBR1_EL2)
-  .unimplemented();
+  .hyp().mon();
 InitReg(MISCREG_TCR_EL2)
   .hyp().mon()
   .mapsTo(MISCREG_HTCR);
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 3c79e43..26a07d7 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2017 ARM Limited
+ * Copyright (c) 2010, 2012-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -739,9 +739,9 @@
 DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n",
 currState->vaddr_tainted, currState->tcr);

-static const GrainSize GrainMapDefault[] =
+static const GrainSize GrainMap_tg0[] =
   { Grain4KB, Grain64KB, Grain16KB, ReservedGrain };
-static const GrainSize GrainMap_EL1_tg1[] =
+static const GrainSize GrainMap_tg1[] =
   { ReservedGrain, Grain16KB, Grain4KB, Grain64KB };

 statWalkWaitTime.sample(curTick() - currState->startTime);
@@ -761,7 +761,7 @@
 DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n");
 ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2);
 tsz = 64 - currState->vtcr.t0sz64;
-tg = GrainMapDefault[currState->vtcr.tg0];
+tg = GrainMap_tg0[currState->vtcr.tg0];
 // ARM DDI 0487A.f D7-2148
 // The starting level of stage 2 translation depends on
 // VTCR_EL2.SL0 and VTCR_EL2.TG0
@@ -781,7 +781,7 @@
 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
-tg = GrainMapDefault[currState->tcr.tg0];
+tg = GrainMap_tg0[currState->tcr.tg0];
 if (bits(currState->vaddr, 63, tsz) != 0x0 ||
 currState->tcr.epd0)
   fault = true;
@@ -790,7 +790,7 @@
 DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1);
 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
-tg = GrainMap_EL1_tg1[currState->tcr.tg1];
+tg = GrainMap_tg1[currState->tcr.tg1];
 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
 currState->tcr.epd1)
   fault = true;
@@ -802,16 +802,37 @@
 ps = currState->tcr.ips;
 break;
   case EL2:
+switch(bits(currState->vaddr, 63,48)) {
+  case 0:
+DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
+ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2);
+tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
+tg = GrainMap_tg0[currState->tcr.tg0];
+break;
+
+  case 0x:
+DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
+ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL2);
+tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
+tg = GrainMap_tg1[currState->tcr.tg1];
+if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
+currState->tcr.epd1 || !currState->hcr.e2h)
+  fault = true;
+break;
+
+   default:
+  // invalid addr if top two bytes are not all 0s
+  fault = true;
+}
+ps = currState->tcr.ips;
+break;
   case EL3:
 switch(bits(currState->vaddr, 63,48)) {
 case 0:
 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
-if (currState->el == EL2)
-ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2);
-else
-ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3);
+ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3);
 tsz = 

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add E2H bit to HCR_EL2 System register

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10381

to review the following change.


Change subject: arch-arm: Add E2H bit to HCR_EL2 System register
..

arch-arm: Add E2H bit to HCR_EL2 System register

This patch adds the EL2 Host bit to the HCR_EL2 register.  Enables a
configuration where a Host Operating System is running in EL2, and the
Host Operating System's applications are running in EL0.

Change-Id: I92d21ed9f8958c58f135dca1b6a97460ba4c02f9
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/miscregs.hh
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 06d1a0d..b43b04f 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1478,6 +1478,7 @@
 EndBitUnion(HSTR)

 BitUnion64(HCR)
+Bitfield<34> e2h;   // AArch64
 Bitfield<33> id;// AArch64
 Bitfield<32> cd;// AArch64
 Bitfield<31> rw;// AArch64

--
To view, visit https://gem5-review.googlesource.com/10381
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I92d21ed9f8958c58f135dca1b6a97460ba4c02f9
Gerrit-Change-Number: 10381
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: mem: Optimize self-refresh entry

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10102 )


Change subject: mem: Optimize self-refresh entry
..

mem: Optimize self-refresh entry

Self-refresh is entered during a refresh event, when the
rank was previously in a precharge power-down state.
The original code would enter self-refresh after a refresh
was issued.  The device subsequently will issue a refresh
on self-refresh entry.  On self-refresh exit, the controller
will issue another refresh command.

Devices require at least one additional refresh to be issued
between self-refresh exit and re-entry.  This ensures that enough
refreshes occur in the case when the device narrowly missed a
refresh on self-refresh exit.

To minimize the number of refresh operations and still maintain
the device requirement, the current logic does the following:
1) The controller will still enter self-refresh from a refresh
   event, when the previous state was precharge power-down.
   However, the refresh itself will be bypassed and the controller
   will immediately issue a self-refresh entry.
2) On a self-refresh exit, the controller will immediately
   issue a refresh command (per the original logic).  This ensures
   the devices requirements are met and is a convenient way to
   kick off the command state machine.

Change-Id: I1c4b0dcbfa3bdafd755f3ccd65e267fcd700c491
Reviewed-by: Curtis Dunham 
Reviewed-on: https://gem5-review.googlesource.com/10102
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Jason Lowe-Power 
Maintainer: Nikos Nikoleris 
---
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
2 files changed, 108 insertions(+), 96 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index fed519d..27e5a23 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -664,10 +664,8 @@

 // track if this is the last packet before idling
 // and that there are no outstanding commands to this rank
-// if REF in progress, transition to LP state should not occur
-// until REF completes
-if ((dram_pkt->rankRef.refreshState == REF_IDLE) &&
-(dram_pkt->rankRef.lowPowerEntryReady())) {
+if (dram_pkt->rankRef.isQueueEmpty() &&
+dram_pkt->rankRef.outstandingEvents == 0) {
 // verify that there are no events scheduled
 assert(!dram_pkt->rankRef.activateEvent.scheduled());
 assert(!dram_pkt->rankRef.prechargeEvent.scheduled());
@@ -1668,21 +1666,13 @@
 }

 bool
-DRAMCtrl::Rank::lowPowerEntryReady() const
+DRAMCtrl::Rank::isQueueEmpty() const
 {
+// check commmands in Q based on current bus direction
 bool no_queued_cmds = ((memory.busStateNext == READ) && (readEntries  
== 0))

   || ((memory.busStateNext == WRITE) &&
   (writeEntries == 0));
-
-if (refreshState == REF_RUN) {
-   // have not decremented outstandingEvents for refresh command
-   // still check if there are no commands queued to force PD
-   // entry after refresh completes
-   return no_queued_cmds;
-} else {
-   // ensure no commands in Q and no commands scheduled
-   return (no_queued_cmds && (outstandingEvents == 0));
-}
+return no_queued_cmds;
 }

 void
@@ -1752,7 +1742,7 @@
 if (numBanksActive == 0) {
 // no reads to this rank in the Q and no pending
 // RD/WR or refresh commands
-if (lowPowerEntryReady()) {
+if (isQueueEmpty() && outstandingEvents == 0) {
 // should still be in ACT state since bank still open
 assert(pwrState == PWR_ACT);

@@ -1953,7 +1943,10 @@

 // Force PRE power-down if there are no outstanding commands
 // in Q after refresh.
-} else if (lowPowerEntryReady()) {
+} else if (isQueueEmpty()) {
+// still have refresh event outstanding but there should
+// be no other events outstanding
+assert(outstandingEvents == 1);
 DPRINTF(DRAMState, "Rank %d sleeping after refresh but was  
NOT"

 " in a low power state before refreshing\n", rank);
 powerDownSleep(PWR_PRE_PDN, curTick());
@@ -1966,16 +1959,15 @@
 }
 }

-// if transitioning to self refresh do not schedule a new refresh;
-// when waking from self refresh, a refresh is scheduled again.
-if (pwrStateTrans != PWR_SREF) {
-// compensate for the delay in actually performing the refresh
-// when scheduling the next one
-schedule(refreshEvent, refreshDueAt - memory.tRP);
+// At this point, we have 

[gem5-dev] Change in gem5/gem5[master]: mem: Add support for more flexible DRAM timing and topologies

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10103 )


Change subject: mem: Add support for more flexible DRAM timing and  
topologies

..

mem: Add support for more flexible DRAM timing and topologies

This patch has 2 main aspects:
1) Add new parameter to adjust write-to-write delay
2) Enable support of more than 64 banks per controller

Changes for new parameter:
Incorporated a new parameter, tCCD_L_WR, which defaults to tCCD_L.
This parameter can be used to set a unique delay between writes and
between reads.

To incorporate this parameter in the controller, modified the DRAMCtrl
class to have separate variables for read and write column delays.
Used these variables to account for tRTW, tWTR, tBURST, tCCD_L, and tCS
as well as the new tCCD_L_WR parameter.

Changes to support more than 64 banks:
Modified the logic selecting the next command (reorderQueue
and minBankPrep functions).  Replaced the unint64_t variables with
a vector of uint32_t elements.  There is a uint32_t element defined
per ranks to allow up to 32 banks per rank.  This will automatically
scale with ranks without issue.
Change will allow analysis of memory sub-systems beyond the current
landscape.

Change-Id: I0ce466efed58276f843ad90e9ecc0ece6c37d646
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/10103
Reviewed-by: Jason Lowe-Power 
Maintainer: Nikos Nikoleris 
---
M src/mem/DRAMCtrl.py
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
3 files changed, 99 insertions(+), 85 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved



diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index 3145751..f78a737 100644
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2016 ARM Limited
+# Copyright (c) 2012-2018 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -45,6 +45,7 @@
 #  Erfan Azarkhish

 from m5.params import *
+from m5.proxy import *
 from AbstractMemory import *

 # Enum for memory scheduling algorithms, currently First-Come
@@ -183,6 +184,13 @@
 # for CAS-to-CAS delay for bursts to different bank groups
 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")

+# Write-to-Write delay for bursts to the same bank group
+# only utilized with bank group architectures; set to 0 for default  
case

+# This will be used to enable different same bank group delays
+# for writes versus reads
+tCCD_L_WR = Param.Latency(Self.tCCD_L,
+"Same bank group Write to Write delay")
+
 # time taken to complete one refresh cycle (N rows in all banks)
 tRFC = Param.Latency("Refresh cycle time")

diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 27e5a23..1a3eec4 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2017 ARM Limited
+ * Copyright (c) 2010-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -84,17 +84,19 @@
 writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),
 minWritesPerSwitch(p->min_writes_per_switch),
 writesThisTime(0), readsThisTime(0),
-tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS),  
tBURST(p->tBURST),

+tCK(p->tCK), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST),
+tCCD_L_WR(p->tCCD_L_WR),
 tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP),  
tRAS(p->tRAS),
 tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI),  
tRRD(p->tRRD),

 tRRD_L(p->tRRD_L), tXAW(p->tXAW), tXP(p->tXP), tXS(p->tXS),
-activationLimit(p->activation_limit),
+activationLimit(p->activation_limit), rankToRankDly(tCS + tBURST),
+wrToRdDly(tCL + tBURST + p->tWTR), rdToWrDly(tRTW + tBURST),
 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
 pageMgmt(p->page_policy),
 maxAccessesPerRow(p->max_accesses_per_row),
 frontendLatency(p->static_frontend_latency),
 backendLatency(p->static_backend_latency),
-busBusyUntil(0), prevArrival(0),
+nextBurstAt(0), prevArrival(0),
 nextReqTime(0), activeRank(0), timeStampOffset(0),
 lastStatsResetTick(0)
 {
@@ -164,6 +166,12 @@
   "bank groups per rank (%d) is greater than 1\n",
   tCCD_L, tBURST, bankGroupsPerRank);
 }
+// tCCD_L_WR should be greater than minimal, back-to-back burst  
delay

+if (tCCD_L_WR <= tBURST) {
+fatal("tCCD_L_WR (%d) should be larger than tBURST (%d) when "
+  "bank groups per rank (%d) is greater than 1\n",
+  tCCD_L_WR, tBURST, bankGroupsPerRank);
+}
 // tRRD_L is greater 

[gem5-dev] Change in gem5/gem5[master]: mem: Add support for more flexible DRAM timing and topologies

[Giacomo Travaglini (Gerrit)]

Hello Jason Lowe-Power, Nikos Nikoleris, Matthew Poremba, Wendy Elsasser,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/10103

to look at the new patch set (#2).

Change subject: mem: Add support for more flexible DRAM timing and  
topologies

..

mem: Add support for more flexible DRAM timing and topologies

This patch has 2 main aspects:
1) Add new parameter to adjust write-to-write delay
2) Enable support of more than 64 banks per controller

Changes for new parameter:
Incorporated a new parameter, tCCD_L_WR, which defaults to tCCD_L.
This parameter can be used to set a unique delay between writes and
between reads.

To incorporate this parameter in the controller, modified the DRAMCtrl
class to have separate variables for read and write column delays.
Used these variables to account for tRTW, tWTR, tBURST, tCCD_L, and tCS
as well as the new tCCD_L_WR parameter.

Changes to support more than 64 banks:
Modified the logic selecting the next command (reorderQueue
and minBankPrep functions).  Replaced the unint64_t variables with
a vector of uint32_t elements.  There is a uint32_t element defined
per ranks to allow up to 32 banks per rank.  This will automatically
scale with ranks without issue.
Change will allow analysis of memory sub-systems beyond the current
landscape.

Change-Id: I0ce466efed58276f843ad90e9ecc0ece6c37d646
Reviewed-by: Nikos Nikoleris 
---
M src/mem/DRAMCtrl.py
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
3 files changed, 99 insertions(+), 85 deletions(-)


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Gerrit-Change-Number: 10103
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Wendy Elsasser 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: S3____ are Implementation defined

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10501

to review the following change.


Change subject: arch-arm: S3 are Implementation  
defined

..

arch-arm: S3 are Implementation defined

In the AArch64 ISA, S3 refers to a pool
of implementation defined registers, provided that reg numbers
are in the following range:

 is in the range 0 - 7
 can take the values 11, 15
 is in the range 0 - 15
 is in the range 0 - 7

Change-Id: I7edd013e5cea4887f5e4c5a81f4835b7de93bd50
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/miscregs.cc
1 file changed, 7 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 08eb255..9861211 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -2082,9 +2082,12 @@
 }
 break;
 }
-break;
+M5_FALLTHROUGH;
+  default:
+// S3__11__
+return MISCREG_IMPDEF_UNIMPL;
 }
-break;
+M5_UNREACHABLE;
   case 12:
 switch (op1) {
   case 0:
@@ -2370,7 +2373,8 @@
 }
 break;
 }
-break;
+// S3__15__
+return MISCREG_IMPDEF_UNIMPL;
 }
 break;
 }

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10504

to review the following change.


Change subject: arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as  
NOP

..

arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP

In the Arm ISA there are some sys reg numbers which are reserved for
implementation defined registers. The default behaviour is to to treat
them as unimplemented registers. It is now possible to change this
behaviour at runtime and treat them as NOP. In this way an access to
those register won't make simulation fail.

Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/ArmISA.py
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/misc.isa
M src/arch/arm/miscregs.cc
6 files changed, 48 insertions(+), 6 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 7956570..78dd043 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013, 2015-2016 ARM Limited
+# Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -111,3 +111,9 @@
 # Reserved for future expansion
 id_aa64mmfr1_el1 = Param.UInt64(0x,
 "AArch64 Memory Model Feature Register 1")
+
+# Any access (read/write) to an unimplemented
+# Implementation Defined registers is not causing an Undefined  
Instruction.

+# It is rather executed as a NOP.
+impdef_nop = Param.Bool(False,
+"Any access to a MISCREG_IMPDEF_UNIMPL register is executed as  
NOP")

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 296f8eb..a4e9c79 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -61,7 +61,8 @@
   system(NULL),
   _decoderFlavour(p->decoderFlavour),
   _vecRegRenameMode(p->vecRegRenameMode),
-  pmu(p->pmu)
+  pmu(p->pmu),
+  impdefAsNop(p->impdef_nop)
 {
 miscRegs[MISCREG_SCTLR_RST] = 0;

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index c8ae5c2..9158b62 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -90,6 +90,12 @@
 bool haveLargeAsid64;
 uint8_t physAddrRange64;

+/**
+ * If true, accesses to IMPLEMENTATION DEFINED registers are  
treated

+ * as NOP hence not causing UNDEFINED INSTRUCTION.
+ */
+bool impdefAsNop;
+
 /** MiscReg metadata **/
 struct MiscRegLUTEntry {
 uint32_t lower;  // Lower half mapped to this register
diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 00bd077..722cd74 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -377,6 +377,20 @@
 return new FailUnimplemented(read ? "mrs" : "msr",
 machInst, full_mnemonic);

+} else if (miscReg == MISCREG_IMPDEF_UNIMPL) {
+auto full_mnemonic =
+csprintf("%s op0:%d op1:%d crn:%d crm:%d  
op2:%d",

+ read ? "mrs" : "msr",
+ op0, op1, crn, crm, op2);
+
+if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
+return new  
WarnUnimplemented(read ? "mrs" : "msr",
+machInst, full_mnemonic + " treated as  
NOP");

+} else {
+return new  
FailUnimplemented(read ? "mrs" : "msr",

+machInst, full_mnemonic);
+}
+
 } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
 if (miscReg == MISCREG_NZCV) {
 if (read)
diff --git a/src/arch/arm/isa/formats/misc.isa  
b/src/arch/arm/isa/formats/misc.isa

index 4f1960b..7397417 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -220,10 +220,22 @@
 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s  
unknown",

 crn, opc1, crm, opc2, isRead ? "read" : "write"));
   case MISCREG_IMPDEF_UNIMPL:
-return new McrMrcImplDefined(
-isRead ? "mrc implementation defined" :
- "mcr implementation defined",
-machInst, iss, MISCREG_IMPDEF_UNIMPL);
+
+if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
+auto mnemonic =
+csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s",
+ crn, opc1, 

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Remove unusued MISCREG_A64_UNIMPL

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10503

to review the following change.


Change subject: arch-arm: Remove unusued MISCREG_A64_UNIMPL
..

arch-arm: Remove unusued MISCREG_A64_UNIMPL

In case the decoder fails to find a suitable MiscReg during a MSR/MRS
in AArch64, MISCREG_UNKNOWN is used, so there is no need for an extra
MISCREG_A64_UNIMPL register.

Change-Id: I7c709fc554e554b39d765dffb7ceb90e33b7c15f
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
2 files changed, 0 insertions(+), 5 deletions(-)



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 9861211..73b991a 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4007,9 +4007,6 @@
 InitReg(MISCREG_CP15_UNIMPL)
   .unimplemented()
   .warnNotFail();
-InitReg(MISCREG_A64_UNIMPL)
-  .unimplemented()
-  .warnNotFail();
 InitReg(MISCREG_UNKNOWN);

 // Register mappings for some unimplemented registers:
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 06d1a0d..8815afc 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -689,7 +689,6 @@
 MISCREG_RAZ,
 MISCREG_CP14_UNIMPL,
 MISCREG_CP15_UNIMPL,
-MISCREG_A64_UNIMPL,
 MISCREG_UNKNOWN,

 // Implementation defined register: this represent
@@ -1386,7 +1385,6 @@
 "raz",
 "cp14_unimpl",
 "cp15_unimpl",
-"a64_unimpl",
 "unknown",
 "impl_defined"
 };

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: MPIDR.MT = 1 in a multithreaded system

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10502

to review the following change.


Change subject: arch-arm: MPIDR.MT = 1 in a multithreaded system
..

arch-arm: MPIDR.MT = 1 in a multithreaded system

MPIDR.MT Indicates whether the lowest level of affinity consists of
logical PEs that are implemented using a multithreading type approach

Change-Id: Ia5e6e65577729c7826227c4574ce690f76454edc
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/utility.cc
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index c272ef6..7659e1e 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -223,6 +223,7 @@
 assert(tc->socketId() < 65536);
 if (arm_sys->multiThread) {
return 0x8000 | // multiprocessor extensions available
+  0x0100 | // multi-threaded cores
   tc->contextId();
 } else if (arm_sys->multiProc) {
return 0x8000 | // multiprocessor extensions available

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add Illegal Execution flag to PCState

[Giacomo Travaglini (Gerrit)]

code AARCH64 {
-0:
-##include "arm.isa"
+decode ILLEGALEXEC default IllegalExec::illegalExec() {
+0: decode DECODERFAULT default DecoderFault::decoderFault() {
+0: decode THUMB default Unknown::unknown() {
+0: decode AARCH64 {
+0:
+##include "arm.isa"
+1:
+##include "aarch64.isa"
+}
 1:
-##include "aarch64.isa"
+##include "thumb.isa"
 }
-1:
-##include "thumb.isa"
 }
 }
diff --git a/src/arch/arm/isa/formats/pseudo.isa  
b/src/arch/arm/isa/formats/pseudo.isa

index 30c2320..407b1c8 100644
--- a/src/arch/arm/isa/formats/pseudo.isa
+++ b/src/arch/arm/isa/formats/pseudo.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2014 ARM Limited
+// Copyright (c) 2014, 2018 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -55,6 +55,15 @@

 
 //
+// Illegal execution handling
+//
+
+def format IllegalExec() {{
+decode_block = 'return new IllegalExecInst(machInst);\n'
+}};
+
+
+//
 // Unknown instruction handling
 //

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 192f01b..9168bdd 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1144,11 +1144,6 @@
 }

 if (fault == NoFault) {
-// Generate Illegal Inst Set State fault if IL bit is set in CPSR
-if (aarch64 && is_fetch && cpsr.il == 1) {
-return std::make_shared();
-}
-
 // Don't try to finalize a physical address unless the
 // translation has completed (i.e., there is a table entry).
 return te ? finalizePhysical(req, tc, mode) : NoFault;
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 84887a1..07cdfad 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2017 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -70,6 +70,7 @@
 BitUnion64(ExtMachInst)
 // Decoder state
 Bitfield<63, 62> decoderFault; // See DecoderFault
+Bitfield<61> illegalExecution;

 // ITSTATE bits
 Bitfield<55, 48> itstate;
@@ -218,14 +219,16 @@
 JazelleBit = (1 << 1),
 AArch64Bit = (1 << 2)
 };
+
 uint8_t flags;
 uint8_t nextFlags;
 uint8_t _itstate;
 uint8_t _nextItstate;
 uint8_t _size;
+bool _illegalExec;
   public:
 PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0),
-_size(0)
+_size(0), _illegalExec(false)
 {}

 void
@@ -236,10 +239,22 @@
 }

 PCState(Addr val) : flags(0), nextFlags(0), _itstate(0),
-_nextItstate(0), _size(0)
+_nextItstate(0), _size(0), _illegalExec(false)
 { set(val); }

 bool
+illegalExec() const
+{
+return _illegalExec;
+}
+
+void
+illegalExec(bool val)
+{
+_illegalExec = val;
+}
+
+bool
 thumb() const
 {
 return flags & ThumbBit;
@@ -472,7 +487,9 @@
 {
 return Base::operator == (opc) &&
 flags == opc.flags && nextFlags == opc.nextFlags &&
-_itstate == opc._itstate && _nextItstate ==  
opc._nextItstate;

+_itstate == opc._itstate &&
+_nextItstate == opc._nextItstate &&
+_illegalExec == opc._illegalExec;
 }

 bool
@@ -490,6 +507,7 @@
 SERIALIZE_SCALAR(nextFlags);
 SERIALIZE_SCALAR(_itstate);
 SERIALIZE_SCALAR(_nextItstate);
+SERIALIZE_SCALAR(_illegalExec);
 }

 void
@@ -501,6 +519,7 @@
 UNSERIALIZE_SCALAR(nextFlags);
 UNSERIALIZE_SCALAR(_itstate);
 UNSERIALIZE_SCALAR(_nextItstate);
+UNSERIALIZE_SCALAR(_illegalExec);
 }
 };


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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adapting IllegalExecution fault for AArch32

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10814

to review the following change.


Change subject: arch-arm: Adapting IllegalExecution fault for AArch32
..

arch-arm: Adapting IllegalExecution fault for AArch32

The Illegal Execution fault triggered by the setting of processor state
PSTATE.IL happens in AArch32 as well and takes the form of UNDEFINED
exception fault.  We are hence copying the UndefinedInstruction AArch32
fields into the IllegalInstSetStateFault.

Change-Id: Ibb7424397c2030ea5d010577c530277a27036aea
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/faults.cc
1 file changed, 4 insertions(+), 5 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index dd4f958..cf58960 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -257,6 +257,10 @@
 "Virtual FIQ",   0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
 4, 4, 0, 0, false, true,  true,  EC_INVALID
 );
+template<> ArmFault::FaultVals  
ArmFaultVals::vals(
+"Illegal Inst Set State Fault",   0x004, 0x000, 0x200, 0x400, 0x600,  
MODE_UNDEFINED,

+4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST
+);
 template<> ArmFault::FaultVals ArmFaultVals::vals(
 // Some dummy values (SupervisorTrap is AArch64-only)
 "Supervisor Trap",   0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
@@ -287,11 +291,6 @@
 "ArmSev Flush",  0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
 0, 0, 0, 0, false, true,  true,  EC_UNKNOWN
 );
-template<> ArmFault::FaultVals  
ArmFaultVals::vals(

-// Some dummy values (SPAlignmentFault is AArch64-only)
-"Illegal Inst Set State Fault",   0x000, 0x000, 0x200, 0x400, 0x600,  
MODE_SVC,

-0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST
-);

 Addr
 ArmFault::getVector(ThreadContext *tc)

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Gerrit-Branch: master
Gerrit-Change-Id: Ibb7424397c2030ea5d010577c530277a27036aea
Gerrit-Change-Number: 10814
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[master]: misc: Using smart pointers for memory Requests

[Giacomo Travaglini (Gerrit)]

Hello Anthony Gutierrez, Daniel Carvalho, Jason Lowe-Power, Andreas  
Sandberg,


I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/10996

to look at the new patch set (#2).

Change subject: misc: Using smart pointers for memory Requests
..

misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M ext/sst/ExtMaster.cc
M ext/sst/ExtSlave.cc
M src/arch/alpha/locked_mem.hh
M src/arch/alpha/tlb.cc
M src/arch/alpha/tlb.hh
M src/arch/arm/isa.cc
M src/arch/arm/locked_mem.hh
M src/arch/arm/stage2_lookup.cc
M src/arch/arm/stage2_lookup.hh
M src/arch/arm/stage2_mmu.cc
M src/arch/arm/stage2_mmu.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/tracers/tarmac_parser.hh
M src/arch/arm/vtophys.cc
M src/arch/generic/locked_mem.hh
M src/arch/generic/tlb.cc
M src/arch/generic/tlb.hh
M src/arch/hsail/insts/mem.hh
M src/arch/mips/locked_mem.hh
M src/arch/mips/tlb.cc
M src/arch/mips/tlb.hh
M src/arch/power/tlb.cc
M src/arch/power/tlb.hh
M src/arch/riscv/locked_mem.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
M src/arch/sparc/tlb.cc
M src/arch/sparc/tlb.hh
M src/arch/x86/intmessage.hh
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/pagetable_walker.hh
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
M src/cpu/base.cc
M src/cpu/base_dyn_inst.hh
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/checker/cpu_impl.hh
M src/cpu/kvm/base.cc
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/fetch1.cc
M src/cpu/minor/fetch1.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.cc
M src/cpu/simple/base.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
M src/cpu/testers/directedtest/InvalidateGenerator.cc
M src/cpu/testers/directedtest/RubyDirectedTester.cc
M src/cpu/testers/directedtest/SeriesRequestGenerator.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/rubytest/Check.cc
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/traffic_gen/base_gen.cc
M src/cpu/testers/traffic_gen/traffic_gen.cc
M src/cpu/trace/trace_cpu.cc
M src/cpu/translation.hh
M src/dev/dma_device.cc
M src/dev/x86/i82094aa.cc
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/fetch_unit.cc
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/shader.cc
M src/gpu-compute/shader.hh
M src/learning_gem5/part2/simple_cache.cc
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
M src/mem/cache/base.cc
M src/mem/cache/blk.hh
M src/mem/cache/cache.cc
M src/mem/cache/mshr.cc
M src/mem/cache/noncoherent_cache.cc
M src/mem/cache/prefetch/queued.cc
M src/mem/packet.hh
M src/mem/page_table.cc
M src/mem/page_table.hh
M src/mem/port.cc
M src/mem/port_proxy.cc
M src/mem/request.hh
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/system/CacheRecorder.cc
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/Sequencer.cc
M util/tlm/src/sc_master_port.cc
102 files changed, 555 insertions(+), 636 deletions(-)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Gerrit-Change-Number: 10996
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[master]: misc: Using smart pointers for memory Requests

[Giacomo Travaglini (Gerrit)]

Hello Anthony Gutierrez, Daniel Carvalho, Jason Lowe-Power, Andreas  
Sandberg,


I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/10996

to look at the new patch set (#3).

Change subject: misc: Using smart pointers for memory Requests
..

misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M ext/sst/ExtMaster.cc
M ext/sst/ExtSlave.cc
M src/arch/alpha/locked_mem.hh
M src/arch/alpha/tlb.cc
M src/arch/alpha/tlb.hh
M src/arch/arm/isa.cc
M src/arch/arm/locked_mem.hh
M src/arch/arm/stage2_lookup.cc
M src/arch/arm/stage2_lookup.hh
M src/arch/arm/stage2_mmu.cc
M src/arch/arm/stage2_mmu.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/tracers/tarmac_parser.hh
M src/arch/arm/vtophys.cc
M src/arch/generic/locked_mem.hh
M src/arch/generic/tlb.cc
M src/arch/generic/tlb.hh
M src/arch/hsail/insts/mem.hh
M src/arch/mips/locked_mem.hh
M src/arch/mips/tlb.cc
M src/arch/mips/tlb.hh
M src/arch/power/tlb.cc
M src/arch/power/tlb.hh
M src/arch/riscv/locked_mem.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
M src/arch/sparc/tlb.cc
M src/arch/sparc/tlb.hh
M src/arch/x86/intmessage.hh
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/pagetable_walker.hh
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
M src/cpu/base.cc
M src/cpu/base_dyn_inst.hh
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/checker/cpu_impl.hh
M src/cpu/kvm/base.cc
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/fetch1.cc
M src/cpu/minor/fetch1.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.cc
M src/cpu/simple/base.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
M src/cpu/testers/directedtest/InvalidateGenerator.cc
M src/cpu/testers/directedtest/RubyDirectedTester.cc
M src/cpu/testers/directedtest/SeriesRequestGenerator.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/rubytest/Check.cc
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/traffic_gen/base_gen.cc
M src/cpu/testers/traffic_gen/traffic_gen.cc
M src/cpu/trace/trace_cpu.cc
M src/cpu/translation.hh
M src/dev/dma_device.cc
M src/dev/x86/i82094aa.cc
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/fetch_unit.cc
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/shader.cc
M src/gpu-compute/shader.hh
M src/learning_gem5/part2/simple_cache.cc
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
M src/mem/cache/base.cc
M src/mem/cache/blk.hh
M src/mem/cache/cache.cc
M src/mem/cache/mshr.cc
M src/mem/cache/noncoherent_cache.cc
M src/mem/cache/prefetch/queued.cc
M src/mem/packet.hh
M src/mem/page_table.cc
M src/mem/page_table.hh
M src/mem/port.cc
M src/mem/port_proxy.cc
M src/mem/request.hh
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/system/CacheRecorder.cc
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/Sequencer.cc
M util/tlm/src/sc_master_port.cc
103 files changed, 609 insertions(+), 651 deletions(-)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Gerrit-Change-Number: 10996
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix missing Request allocation

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/11095 )


Change subject: arch-arm: Fix missing Request allocation
..

arch-arm: Fix missing Request allocation

This patch is fixing a missing allocation for a Request buffer
in the Stage2Translation class.

Change-Id: I9ce7b85d3527c5b3cc895eb83e9a39641793b0bd
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/11095
Maintainer: Andreas Sandberg 
---
M src/arch/arm/stage2_mmu.cc
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index c6f3ba7..f043db2 100644
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -113,6 +113,7 @@
 : data(_data), numBytes(0), event(_event), parent(_parent),  
oVAddr(_oVAddr),

 fault(NoFault)
 {
+req = std::make_shared();
 }

 void

--
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Gerrit-Branch: master
Gerrit-Change-Id: I9ce7b85d3527c5b3cc895eb83e9a39641793b0bd
Gerrit-Change-Number: 11095
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: BadMode checking if corresponding EL is implemented

[Giacomo Travaglini (Gerrit)]

c/arch/arm/isa/insts/str.isa
@@ -112,6 +112,12 @@
 if self.add:
 wbDiff = 8
 accCode = '''
+
+auto tc = xc->tcBase();
+if (badMode32(tc, static_cast(regMode))) {
+return undefinedFault32(tc, opModeToEL(currOpMode(tc)));
+}
+
 CPSR cpsr = Cpsr;
 Mem_ud = (uint64_t)cSwap(LR_uw, cpsr.e) |
  ((uint64_t)cSwap(Spsr_uw, cpsr.e) << 32);
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 07cdfad..9ce0252 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -710,7 +710,7 @@
 }

 static inline bool
-badMode(OperatingMode mode)
+unknownMode(OperatingMode mode)
 {
 switch (mode) {
   case MODE_EL0T:
@@ -735,9 +735,8 @@
 }
 }

-
 static inline bool
-badMode32(OperatingMode mode)
+unknownMode32(OperatingMode mode)
 {
 switch (mode) {
   case MODE_USER:
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 7659e1e..dec85ef 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -313,6 +313,18 @@
 }
 }

+bool
+badMode32(ThreadContext *tc, OperatingMode mode)
+{
+return unknownMode32(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
+}
+
+bool
+badMode(ThreadContext *tc, OperatingMode mode)
+{
+return unknownMode(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
+}
+
 Addr
 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
  TTBCR tcr)
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 796ded7..9d0131b 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -181,6 +181,26 @@

 bool isBigEndian64(ThreadContext *tc);

+/**
+ * badMode is checking if the execution mode provided as an argument is
+ * valid and implemented for AArch32
+ *
+ * @param tc ThreadContext
+ * @param mode OperatingMode to check
+ * @return false if mode is valid and implemented, true otherwise
+ */
+bool badMode32(ThreadContext *tc, OperatingMode mode);
+
+/**
+ * badMode is checking if the execution mode provided as an argument is
+ * valid and implemented.
+ *
+ * @param tc ThreadContext
+ * @param mode OperatingMode to check
+ * @return false if mode is valid and implemented, true otherwise
+ */
+bool badMode(ThreadContext *tc, OperatingMode mode);
+
 static inline uint8_t
 itState(CPSR psr)
 {

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ibfe385c5465b904acc0d2eb9647710891d72c9df
Gerrit-Change-Number: 11196
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: AArch32 execution triggering AArch64 SW Break

[Giacomo Travaglini (Gerrit)]

 return softwareBreakpoint32(xc, imm16);
+'''
 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
 header_output += BasicDeclare.subst(bkptIop)
 decoder_output += BasicConstructor.subst(bkptIop)

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Gerrit-Change-Id: I485852ed19429f9cd928a6447a95eb6f471f189c
Gerrit-Change-Number: 11197
Gerrit-PatchSet: 1
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Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Read APSR in User Mode

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10602 )


Change subject: arch-arm: Read APSR in User Mode
..

arch-arm: Read APSR in User Mode

This patch substitutes reads to the CPSR in user mode (MRS CPSR) to
reads to APSR (Application Program Status Register).
This is the user level alias for the CPSR. The APSR is a subset of the
CPSR.

Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/10602
Maintainer: Andreas Sandberg 
---
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/miscregs.hh
2 files changed, 12 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/isa/insts/misc.isa  
b/src/arch/arm/isa/insts/misc.isa

index f1c6acf..ef579bf 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -226,7 +226,7 @@
 cpsr.c = CondCodesC;
 cpsr.v = CondCodesV;
 cpsr.ge = CondCodesGE;
-Dest = cpsr & 0xF8FF03DF
+Dest = cpsr & (cpsr.mode == MODE_USER ? ApsrMask : CpsrMask);
 '''

 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index b00e5ff..f9386b4 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1423,6 +1423,17 @@
 static const uint32_t CondCodesMask   = 0xF00F;
 static const uint32_t CpsrMaskQ   = 0x0800;

+// APSR (Application Program Status Register Mask). It is the user  
level

+// alias for the CPSR. The APSR is a subset of the CPSR. Although
+// bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
+// APSR:
+// Bit[9] returns the value of CPSR.E.
+// Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
+static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask |  
0x01D0;

+
+// CPSR (Current Program Status Register Mask).
+static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
+
 BitUnion32(HDCR)
 Bitfield<11>   tdra;
 Bitfield<10>   tdosa;

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Gerrit-Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d
Gerrit-Change-Number: 10602
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
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Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adapting IllegalExecution fault for AArch32

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10814 )


Change subject: arch-arm: Adapting IllegalExecution fault for AArch32
..

arch-arm: Adapting IllegalExecution fault for AArch32

The Illegal Execution fault triggered by the setting of processor state
PSTATE.IL happens in AArch32 as well and takes the form of UNDEFINED
exception fault.  We are hence copying the UndefinedInstruction AArch32
fields into the IllegalInstSetStateFault.

Change-Id: Ibb7424397c2030ea5d010577c530277a27036aea
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/10814
Maintainer: Andreas Sandberg 
---
M src/arch/arm/faults.cc
1 file changed, 4 insertions(+), 5 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index dd4f958..cf58960 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -257,6 +257,10 @@
 "Virtual FIQ",   0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
 4, 4, 0, 0, false, true,  true,  EC_INVALID
 );
+template<> ArmFault::FaultVals  
ArmFaultVals::vals(
+"Illegal Inst Set State Fault",   0x004, 0x000, 0x200, 0x400, 0x600,  
MODE_UNDEFINED,

+4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST
+);
 template<> ArmFault::FaultVals ArmFaultVals::vals(
 // Some dummy values (SupervisorTrap is AArch64-only)
 "Supervisor Trap",   0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
@@ -287,11 +291,6 @@
 "ArmSev Flush",  0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
 0, 0, 0, 0, false, true,  true,  EC_UNKNOWN
 );
-template<> ArmFault::FaultVals  
ArmFaultVals::vals(

-// Some dummy values (SPAlignmentFault is AArch64-only)
-"Illegal Inst Set State Fault",   0x000, 0x000, 0x200, 0x400, 0x600,  
MODE_SVC,

-0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST
-);

 Addr
 ArmFault::getVector(ThreadContext *tc)

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ibb7424397c2030ea5d010577c530277a27036aea
Gerrit-Change-Number: 10814
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add Illegal Execution flag to PCState

[Giacomo Travaglini (Gerrit)]

-decode DECODERFAULT default DecoderFault::decoderFault() {
-0: decode THUMB default Unknown::unknown() {
-0: decode AARCH64 {
-0:
-##include "arm.isa"
+decode ILLEGALEXEC default IllegalExec::illegalExec() {
+0: decode DECODERFAULT default DecoderFault::decoderFault() {
+0: decode THUMB default Unknown::unknown() {
+0: decode AARCH64 {
+0:
+##include "arm.isa"
+1:
+##include "aarch64.isa"
+}
 1:
-##include "aarch64.isa"
+##include "thumb.isa"
 }
-1:
-##include "thumb.isa"
 }
 }
diff --git a/src/arch/arm/isa/formats/pseudo.isa  
b/src/arch/arm/isa/formats/pseudo.isa

index 30c2320..407b1c8 100644
--- a/src/arch/arm/isa/formats/pseudo.isa
+++ b/src/arch/arm/isa/formats/pseudo.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2014 ARM Limited
+// Copyright (c) 2014, 2018 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -55,6 +55,15 @@

 
 //
+// Illegal execution handling
+//
+
+def format IllegalExec() {{
+decode_block = 'return new IllegalExecInst(machInst);\n'
+}};
+
+
+//
 // Unknown instruction handling
 //

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index d2153e7..79eef1b 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1145,11 +1145,6 @@
 }

 if (fault == NoFault) {
-// Generate Illegal Inst Set State fault if IL bit is set in CPSR
-if (aarch64 && is_fetch && cpsr.il == 1) {
-return std::make_shared();
-}
-
 // Don't try to finalize a physical address unless the
 // translation has completed (i.e., there is a table entry).
 return te ? finalizePhysical(req, tc, mode) : NoFault;
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 84887a1..07cdfad 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2017 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -70,6 +70,7 @@
 BitUnion64(ExtMachInst)
 // Decoder state
 Bitfield<63, 62> decoderFault; // See DecoderFault
+Bitfield<61> illegalExecution;

 // ITSTATE bits
 Bitfield<55, 48> itstate;
@@ -218,14 +219,16 @@
 JazelleBit = (1 << 1),
 AArch64Bit = (1 << 2)
 };
+
 uint8_t flags;
 uint8_t nextFlags;
 uint8_t _itstate;
 uint8_t _nextItstate;
 uint8_t _size;
+bool _illegalExec;
   public:
 PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0),
-_size(0)
+_size(0), _illegalExec(false)
 {}

 void
@@ -236,10 +239,22 @@
 }

 PCState(Addr val) : flags(0), nextFlags(0), _itstate(0),
-_nextItstate(0), _size(0)
+_nextItstate(0), _size(0), _illegalExec(false)
 { set(val); }

 bool
+illegalExec() const
+{
+return _illegalExec;
+}
+
+void
+illegalExec(bool val)
+{
+_illegalExec = val;
+}
+
+bool
 thumb() const
 {
 return flags & ThumbBit;
@@ -472,7 +487,9 @@
 {
 return Base::operator == (opc) &&
 flags == opc.flags && nextFlags == opc.nextFlags &&
-_itstate == opc._itstate && _nextItstate ==  
opc._nextItstate;

+_itstate == opc._itstate &&
+_nextItstate == opc._nextItstate &&
+_illegalExec == opc._illegalExec;
 }

 bool
@@ -490,6 +507,7 @@
 SERIALIZE_SCALAR(nextFlags);
 SERIALIZE_SCALAR(_itstate);
 SERIALIZE_SCALAR(_nextItstate);
+SERIALIZE_SCALAR(_illegalExec);
 }

 void
@@ -501,6 +519,7 @@
 UNSERIALIZE_SCALAR(nextFlags);
 UNSERIALIZE_SCALAR(_itstate);
 UNSERIALIZE_SCALAR(_nextItstate);
+UNSERIALIZE_SCALAR(_illegalExec);
 }
 };


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Gerr

[gem5-dev] Change in gem5/gem5[master]: arch-arm: AArch32 execution triggering AArch64 SW Break

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/11197

to look at the new patch set (#2).

Change subject: arch-arm: AArch32 execution triggering AArch64 SW Break
..

arch-arm: AArch32 execution triggering AArch64 SW Break

AArch32 Software Breakpoint (BKPT) can trigger an AArch64 fault when
interprocessing if the trapping conditions are met.

Change-Id: I485852ed19429f9cd928a6447a95eb6f471f189c
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/faults.cc
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/isa/formats/breakpoint.isa
M src/arch/arm/isa/insts/misc.isa
5 files changed, 35 insertions(+), 46 deletions(-)


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[gem5-dev] Change in gem5/gem5[master]: misc: Substitute pointer to Request with aliased RequestPtr

[Giacomo Travaglini (Gerrit)]

fails
 bool isLLSC = pkt->isLLSC();
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index a8f29e3..f753cc3 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1278,7 +1278,7 @@

 writebacks[Request::wbMasterId]++;

-Request *req = new Request(regenerateBlkAddr(blk), blkSize, 0,
+RequestPtr req = new Request(regenerateBlkAddr(blk), blkSize, 0,
Request::wbMasterId);
 if (blk->isSecure())
 req->setFlags(Request::SECURE);
@@ -1313,7 +1313,7 @@
 PacketPtr
 BaseCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id)
 {
-Request *req = new Request(regenerateBlkAddr(blk), blkSize, 0,
+RequestPtr req = new Request(regenerateBlkAddr(blk), blkSize, 0,
Request::wbMasterId);
 if (blk->isSecure()) {
 req->setFlags(Request::SECURE);
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 34f3dc5..86c1640 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -872,7 +872,8 @@
 assert(!writebackClean);
 assert(blk && blk->isValid() && !blk->isDirty());
 // Creating a zero sized write, a message to the snoop filter
-Request *req =
+
+RequestPtr req =
 new Request(regenerateBlkAddr(blk), blkSize, 0,
 Request::wbMasterId);
 if (blk->isSecure())
diff --git a/src/mem/cache/prefetch/queued.cc  
b/src/mem/cache/prefetch/queued.cc

index bf3a384..00d62f1 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -223,7 +223,7 @@
 }

 /* Create a prefetch memory request */
-Request *pf_req =
+RequestPtr pf_req =
     new Request(pf_info.first, blkSize, 0, masterId);

 if (is_secure) {

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Gerrit-Change-Number: 10995
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Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Daniel Carvalho 
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[gem5-dev] Change in gem5/gem5[master]: base: Add an asymmetrical Coroutine class

[Giacomo Travaglini (Gerrit)]

g the strings together one
+ * character per time.
+ * The result string is hence passed back and forth between the
+ * coroutine and the caller.
+ */
+TEST(Coroutine, Cooperative)
+{
+const std::string caller_str("HloWrd");
+const std::string coro_str("el ol!");
+const std::string expected("Hello World!");
+
+auto cooperative_task =
+[_str] (Coroutine::CallerType& yield)
+{
+for (auto& appended_c : coro_str) {
+auto old_str = yield.get();
+yield(old_str + appended_c);
+}
+};
+
+Coroutine coro(cooperative_task);
+
+std::string result;
+for (auto& c : caller_str) {
+ASSERT_TRUE(coro);
+result += c;
+result = coro(result).get();
+}
+
+ASSERT_STREQ(result.c_str(), expected.c_str());
+}

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[gem5-dev] Change in gem5/gem5[master]: base: Add a class which encapsulates Fibers.

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has uploaded a new patch set (#4) to the change  
originally created by Gabe Black. (  
https://gem5-review.googlesource.com/10935 )


Change subject: base: Add a class which encapsulates Fibers.
..

base: Add a class which encapsulates Fibers.

This class encapsulates the idea of a Fiber in such a way that other
implementations can be substituted in in the future. This
implementation uses the ucontext family of functions.

This change also adds a new unit test which exercises the new class. It
creates three new fibers which accept a sequence of other fibers to
switch to, one after the other. The main test function switches to
the these fibers which switch with each other and occasionally back to
the main fiber. Each time a test fiber is activated, it checks against
a list which shows the correct order for the fibers to run in. When the
main fiber gets control, it makes sure that list has been progressed
through by the correct amount.

Change-Id: I1fc2afa414b51baaa91e350a4ebc791d989f0b8a
---
M src/base/SConscript
A src/base/fiber.cc
A src/base/fiber.hh
A src/base/fibertest.cc
4 files changed, 395 insertions(+), 0 deletions(-)


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Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Implement ARMv8.1 TTBR1_EL2 register

[Giacomo Travaglini (Gerrit)]

>el == EL2)
-ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2);
-else
-ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3);
+ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3);
 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
-tg = GrainMapDefault[currState->tcr.tg0];
+tg = GrainMap_tg0[currState->tcr.tg0];
 break;
 default:
 // invalid addr if top two bytes are not all 0s

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add E2H bit to HCR_EL2 System register

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10381 )


Change subject: arch-arm: Add E2H bit to HCR_EL2 System register
..

arch-arm: Add E2H bit to HCR_EL2 System register

This patch adds the EL2 Host bit to the HCR_EL2 register.  Enables a
configuration where a Host Operating System is running in EL2, and the
Host Operating System's applications are running in EL0.

Change-Id: I92d21ed9f8958c58f135dca1b6a97460ba4c02f9
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/10381
Maintainer: Andreas Sandberg 
---
M src/arch/arm/miscregs.hh
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 06d1a0d..b43b04f 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1478,6 +1478,7 @@
 EndBitUnion(HSTR)

 BitUnion64(HCR)
+Bitfield<34> e2h;   // AArch64
 Bitfield<33> id;// AArch64
 Bitfield<32> cd;// AArch64
 Bitfield<31> rw;// AArch64

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[gem5-dev] Change in gem5/gem5[master]: cpu: Avoid unnecessary dynamic_pointer_cast in atomic model

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10101 )


Change subject: cpu: Avoid unnecessary dynamic_pointer_cast in atomic model
..

cpu: Avoid unnecessary dynamic_pointer_cast in atomic model

In the atomic model a dynamic_pointer_cast is performed at every tick to
check if the fault is a SyscallRetryFault. This was happening even when
there was no generated fault.

Change-Id: I7f4afedf4f988230e05286602d8d9a919c6c
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/10101
Reviewed-by: Brandon Potter 
Reviewed-by: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
---
M src/cpu/simple/atomic.cc
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Brandon Potter: Looks good to me, but someone else must approve
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index bc7670b..7a368ab 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -628,7 +628,8 @@
 traceData = NULL;
 }

-if (dynamic_pointer_cast(fault)) {
+if (fault != NoFault &&
+dynamic_pointer_cast(fault)) {
 // Retry execution of system calls after a delay.
 // Prevents immediate re-execution since conditions  
which

 // caused the retry are unlikely to change every tick.

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Remove unusued MISCREG_A64_UNIMPL

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10503 )


Change subject: arch-arm: Remove unusued MISCREG_A64_UNIMPL
..

arch-arm: Remove unusued MISCREG_A64_UNIMPL

In case the decoder fails to find a suitable MiscReg during a MSR/MRS
in AArch64, MISCREG_UNKNOWN is used, so there is no need for an extra
MISCREG_A64_UNIMPL register.

Change-Id: I7c709fc554e554b39d765dffb7ceb90e33b7c15f
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/10503
Maintainer: Andreas Sandberg 
---
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
2 files changed, 0 insertions(+), 5 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 08e37bb..31b3580 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4007,9 +4007,6 @@
 InitReg(MISCREG_CP15_UNIMPL)
   .unimplemented()
   .warnNotFail();
-InitReg(MISCREG_A64_UNIMPL)
-  .unimplemented()
-  .warnNotFail();
 InitReg(MISCREG_UNKNOWN);

 // Register mappings for some unimplemented registers:
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index b43b04f..b00e5ff 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -689,7 +689,6 @@
 MISCREG_RAZ,
 MISCREG_CP14_UNIMPL,
 MISCREG_CP15_UNIMPL,
-MISCREG_A64_UNIMPL,
 MISCREG_UNKNOWN,

 // Implementation defined register: this represent
@@ -1386,7 +1385,6 @@
 "raz",
 "cp14_unimpl",
 "cp15_unimpl",
-"a64_unimpl",
 "unknown",
 "impl_defined"
 };

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Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini 
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Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: S3____ are Implementation defined

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10501 )


Change subject: arch-arm: S3 are Implementation  
defined

..

arch-arm: S3 are Implementation defined

In the AArch64 ISA, S3 refers to a pool
of implementation defined registers, provided that reg numbers
are in the following range:

 is in the range 0 - 7
 can take the values 11, 15
 is in the range 0 - 15
 is in the range 0 - 7

Change-Id: I7edd013e5cea4887f5e4c5a81f4835b7de93bd50
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/10501
Maintainer: Andreas Sandberg 
---
M src/arch/arm/miscregs.cc
1 file changed, 7 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index e1ddbf9..08e37bb 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -2082,9 +2082,12 @@
 }
 break;
 }
-break;
+M5_FALLTHROUGH;
+  default:
+// S3__11__
+return MISCREG_IMPDEF_UNIMPL;
 }
-break;
+M5_UNREACHABLE;
   case 12:
 switch (op1) {
   case 0:
@@ -2370,7 +2373,8 @@
 }
 break;
 }
-break;
+// S3__15__
+return MISCREG_IMPDEF_UNIMPL;
 }
 break;
 }

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I7edd013e5cea4887f5e4c5a81f4835b7de93bd50
Gerrit-Change-Number: 10501
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP

[Giacomo Travaglini (Gerrit)]

-machInst, iss, MISCREG_IMPDEF_UNIMPL);
+
+if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
+auto mnemonic =
+csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s",
+ crn, opc1, crm, opc2,  
isRead ? "read" : "write");

+
+return new WarnUnimplemented(
+isRead ? "mrc implementation defined" :
+ "mcr implementation defined",
+machInst, mnemonic + " treated as NOP");
+} else {
+return new McrMrcImplDefined(
+isRead ? "mrc implementation defined" :
+ "mcr implementation defined",
+machInst, iss, MISCREG_IMPDEF_UNIMPL);
+}
   case MISCREG_CP15ISB:
 return new Isb(machInst, iss);
   case MISCREG_CP15DSB:
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 31b3580..8dd56c7 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4008,6 +4008,9 @@
   .unimplemented()
   .warnNotFail();
 InitReg(MISCREG_UNKNOWN);
+InitReg(MISCREG_IMPDEF_UNIMPL)
+  .unimplemented()
+  .warnNotFail(impdefAsNop);

 // Register mappings for some unimplemented registers:
 // ESR_EL1 -> DFSR

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Gerrit-Change-Number: 10504
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Read APSR in User Mode

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10602

to review the following change.


Change subject: arch-arm: Read APSR in User Mode
..

arch-arm: Read APSR in User Mode

This patch substitutes reads to the CPSR in user mode (MRS CPSR) to
reads to APSR (Application Program Status Register).
This is the user level alias for the CPSR. The APSR is a subset of the
CPSR.

Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/miscregs.hh
2 files changed, 12 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/isa/insts/misc.isa  
b/src/arch/arm/isa/insts/misc.isa

index f1c6acf..ef579bf 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -226,7 +226,7 @@
 cpsr.c = CondCodesC;
 cpsr.v = CondCodesV;
 cpsr.ge = CondCodesGE;
-Dest = cpsr & 0xF8FF03DF
+Dest = cpsr & (cpsr.mode == MODE_USER ? ApsrMask : CpsrMask);
 '''

 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index b00e5ff..f9386b4 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1423,6 +1423,17 @@
 static const uint32_t CondCodesMask   = 0xF00F;
 static const uint32_t CpsrMaskQ   = 0x0800;

+// APSR (Application Program Status Register Mask). It is the user  
level

+// alias for the CPSR. The APSR is a subset of the CPSR. Although
+// bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
+// APSR:
+// Bit[9] returns the value of CPSR.E.
+// Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
+static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask |  
0x01D0;

+
+// CPSR (Current Program Status Register Mask).
+static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
+
 BitUnion32(HDCR)
 Bitfield<11>   tdra;
 Bitfield<10>   tdosa;

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Gerrit-Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d
Gerrit-Change-Number: 10602
Gerrit-PatchSet: 1
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[gem5-dev] Change in gem5/gem5[master]: python: Include hasattr helper for SimObjects

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10601

to review the following change.


Change subject: python: Include hasattr helper for SimObjects
..

python: Include hasattr helper for SimObjects

With this patch it will be possibile to query a SimObject from
configuration file to check if it has a parameter.

Change-Id: Ie5eb6efe5595f9a8a44df49e6e149428c6c3464d
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/python/m5/SimObject.py
1 file changed, 11 insertions(+), 1 deletion(-)



diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 6e61961..0bcc900 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017 ARM Limited
+# Copyright (c) 2017-2018 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -660,6 +660,16 @@
 raise AttributeError, \
   "object '%s' has no attribute '%s'" % (cls.__name__, attr)

+# Check for attribute (called to see if foo has attribute attr when
+# foo is an instance of class cls)
+def hasattr(cls, attr):
+try:
+__getattr__(cls, attr)
+except AttributeError:
+return False
+else:
+return True
+
 def __str__(cls):
 return cls.__name__


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[gem5-dev] Change in gem5/gem5[master]: base: Add an asymmetrical Coroutine class

[Giacomo Travaglini (Gerrit)]

Hello Gabe Black, Jason Lowe-Power, Nikos Nikoleris, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/11195

to look at the new patch set (#6).

Change subject: base: Add an asymmetrical Coroutine class
..

base: Add an asymmetrical Coroutine class

This patch is providing gem5 a Coroutine class to be used for
instantiating asymmetrical coroutines. Coroutines are built on top of
gem5 fibers, which makes them ucontext based.

Change-Id: I7bb673a954d4a456997afd45b696933534f3e239
Signed-off-by: Giacomo Travaglini 
---
M src/base/SConscript
A src/base/coroutine.hh
A src/base/coroutinetest.cc
3 files changed, 524 insertions(+), 0 deletions(-)


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Gerrit-Change-Id: I7bb673a954d4a456997afd45b696933534f3e239
Gerrit-Change-Number: 11195
Gerrit-PatchSet: 6
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in gem5/gem5[master]: scons: Fix --with-ubsan/asan compilation flags

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10181

to review the following change.


Change subject: scons: Fix --with-ubsan/asan compilation flags
..

scons: Fix --with-ubsan/asan compilation flags

SConstruct was using an undefined env variable; this patch uses the main
Environment variable.

Change-Id: I30ab6b4bbfa6d9a71a30fb33406a799bfb476821
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 8 insertions(+), 8 deletions(-)



diff --git a/SConstruct b/SConstruct
index 8fde133..b382d33 100755
--- a/SConstruct
+++ b/SConstruct
@@ -481,21 +481,21 @@
 # The address sanitizer is available for gcc >= 4.8
 if GetOption('with_asan'):
 if GetOption('with_ubsan') and \
-compareVersions(env['GCC_VERSION'], '4.9') >= 0:
-env.Append(CCFLAGS=['-fsanitize=address,undefined',
-'-fno-omit-frame-pointer'],
+compareVersions(main['GCC_VERSION'], '4.9') >= 0:
+main.Append(CCFLAGS=['-fsanitize=address,undefined',
+ '-fno-omit-frame-pointer'],
LINKFLAGS='-fsanitize=address,undefined')
 else:
-env.Append(CCFLAGS=['-fsanitize=address',
-'-fno-omit-frame-pointer'],
+main.Append(CCFLAGS=['-fsanitize=address',
+ '-fno-omit-frame-pointer'],
LINKFLAGS='-fsanitize=address')
 # Only gcc >= 4.9 supports UBSan, so check both the version
 # and the command-line option before adding the compiler and
 # linker flags.
 elif GetOption('with_ubsan') and \
-compareVersions(env['GCC_VERSION'], '4.9') >= 0:
-env.Append(CCFLAGS='-fsanitize=undefined')
-env.Append(LINKFLAGS='-fsanitize=undefined')
+compareVersions(main['GCC_VERSION'], '4.9') >= 0:
+main.Append(CCFLAGS='-fsanitize=undefined')
+main.Append(LINKFLAGS='-fsanitize=undefined')

 elif main['CLANG']:
 # Check for a supported version of clang, >= 3.1 is needed to

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[gem5-dev] Change in public/gem5[master]: base: Function for mirroring bits in variable length word

[Giacomo Travaglini (Gerrit)]

Hello Nikos Nikoleris, Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/5261

to review the following change.


Change subject: base: Function for mirroring bits in variable length word
..

base: Function for mirroring bits in variable length word

This patch introduces a high-speed template function for mirroring the
bits (MSB=>LSB) in a variable length word. The function is achieving
high performances since it is using a look-up table.

Change-Id: Ib0d0480e68d902f25655f74d243de305103eff75
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Andreas Sandberg 
---
M src/base/SConscript
A src/base/bitfield.cc
M src/base/bitfield.hh
3 files changed, 104 insertions(+), 2 deletions(-)



diff --git a/src/base/SConscript b/src/base/SConscript
index 74a248b..1ca0e35 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -34,6 +34,7 @@
 SimObject('CPA.py')
 Source('cp_annotate.cc')
 Source('atomicio.cc')
+Source('bitfield.cc')
 Source('bigint.cc')
 Source('bitmap.cc')
 Source('callback.cc')
diff --git a/src/base/bitfield.cc b/src/base/bitfield.cc
new file mode 100644
index 000..0650a8c
--- /dev/null
+++ b/src/base/bitfield.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Giacomo Travaglini
+ */
+
+#include "base/bitfield.hh"
+
+/** Lookup table used for High Speed bit reversing */
+const uint8_t reverseLookUpTable[] =
+{
+0x00, 0x80, 0x40, 0xC0, 0x20, 0xA0, 0x60, 0xE0, 0x10, 0x90, 0x50, 0xD0,
+0x30, 0xB0, 0x70, 0xF0, 0x08, 0x88, 0x48, 0xC8, 0x28, 0xA8, 0x68, 0xE8,
+0x18, 0x98, 0x58, 0xD8, 0x38, 0xB8, 0x78, 0xF8, 0x04, 0x84, 0x44, 0xC4,
+0x24, 0xA4, 0x64, 0xE4, 0x14, 0x94, 0x54, 0xD4, 0x34, 0xB4, 0x74, 0xF4,
+0x0C, 0x8C, 0x4C, 0xCC, 0x2C, 0xAC, 0x6C, 0xEC, 0x1C, 0x9C, 0x5C, 0xDC,
+0x3C, 0xBC, 0x7C, 0xFC, 0x02, 0x82, 0x42, 0xC2, 0x22, 0xA2, 0x62, 0xE2,
+0x12, 0x92, 0x52, 0xD2, 0x32, 0xB2, 0x72, 0xF2, 0x0A, 0x8A, 0x4A, 0xCA,
+0x2A, 0xAA, 0x6A, 0xEA, 0x1A, 0x9A, 0x5A, 0xDA, 0x3A, 0xBA, 0x7A, 0xFA,
+0x06, 0x86, 0x46, 0xC6, 0x26, 0xA6, 0x66, 0xE6, 0x16, 0x96, 0x56, 0xD6,
+0x36, 0xB6, 0x76, 0xF6, 0x0E, 0x8E, 0x4E, 0xCE, 0x2E, 0xAE, 0x6E, 0xEE,
+0x1E, 0x9E, 0x5E, 0xDE, 0x3E, 0xBE, 0x7E, 0xFE, 0x01, 0x81, 0x41, 0xC1,
+0x21, 0xA1, 0x61, 0xE1, 0x11, 0x91, 0x51, 0xD1, 0x31, 0xB1, 0x71, 0xF1,
+0x09, 0x89, 0x49, 0xC9, 0x29, 0xA9, 0x69, 0xE9, 0x19, 0x99, 0x59, 0xD9,
+0x39, 0xB9, 0x79, 0xF9, 0x05, 0x85, 0x45, 0xC5, 0x25, 0xA5, 0x65, 0xE5,
+0x15, 0x95, 0x55, 0xD5, 0x35, 0xB5, 0x75, 0xF5, 0x0D, 0x8D, 0x4D, 0xCD,
+0x2D, 0xAD, 0x6D, 0xED, 0x1D, 0x9D, 0x5D, 0xDD, 0x3D, 0xBD, 0x7D, 0xFD,
+0x03, 0x83, 0x43, 0xC3, 0x23, 0xA3, 0x63, 

[gem5-dev] Change in public/gem5[master]: arch-arm: RBIT instruction using mirroring func

[Giacomo Travaglini (Gerrit)]

Hello Nikos Nikoleris, Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/5262

to review the following change.


Change subject: arch-arm: RBIT instruction using mirroring func
..

arch-arm: RBIT instruction using mirroring func

The high speed bit-reversing function is now used
for the Aarch64/32 RBIT instruction implementation.

Change-Id: Id5a8a93d928d00fd33ec4061fbb586b8420a1c1b
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/isa/insts/misc.isa
2 files changed, 2 insertions(+), 23 deletions(-)



diff --git a/src/arch/arm/isa/insts/data64.isa  
b/src/arch/arm/isa/insts/data64.isa

index 48fc87c..3284d5b 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -248,18 +248,7 @@
 Dest64 = (Op164 == 0) ? intWidth : (intWidth - 1 -  
findMsbSet(Op164));

 ''')
 buildDataXRegInst("rbit", 1, '''
-uint64_t result = Op164;
-uint64_t lBit = 1ULL << (intWidth - 1);
-uint64_t rBit = 1ULL;
-while (lBit > rBit) {
-uint64_t maskBits = lBit | rBit;
-uint64_t testBits = result & maskBits;
-// If these bits are different, swap them by toggling them.
-if (testBits && testBits != maskBits)
-result ^= maskBits;
-lBit >>= 1; rBit <<= 1;
-}
-Dest64 = result;
+Dest64 = reverseBits(Op164, intWidth/8);
 ''')
 buildDataXRegInst("rev", 1, '''
 if (intWidth == 32)
diff --git a/src/arch/arm/isa/insts/misc.isa  
b/src/arch/arm/isa/insts/misc.isa

index 5eda615..edeb0f6 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -329,17 +329,7 @@
 exec_output += PredOpExecute.subst(revshIop)

 rbitCode = '''
-uint8_t *opBytes = (uint8_t *)
-uint32_t resTemp;
-uint8_t *destBytes = (uint8_t *)
-// This reverses the bytes and bits of the input, or so says the
-// internet.
-for (int i = 0; i < 4; i++) {
-uint32_t temp = opBytes[i];
-temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
-destBytes[3 - i] = (temp * 0x10101) >> 16;
-}
-Dest = resTemp;
+Dest = reverseBits(Op1);
 '''
 rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
 { "code": rbitCode,

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[gem5-dev] Change in public/gem5[master]: base: Defining make_unique for C++11

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5201 )


Change subject: base: Defining make_unique for C++11
..

base: Defining make_unique for C++11

std::make_unique is not available for C++11 compilers, and it has been
introduced only in C++14.  Since gem5 is not officially supporting the
latter at the moment, this patch allows to use it in gem5 if including
base/compiler.hh. If compiled under C++14, std::make_unique will be
used instead.

Change-Id: Ibf1897fad0a1eb1cb0c683cc25170feaa6841997
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/5201
Reviewed-by: Anthony Gutierrez 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/base/compiler.hh
1 file changed, 27 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved



diff --git a/src/base/compiler.hh b/src/base/compiler.hh
index 9cad07d..2fdd323 100644
--- a/src/base/compiler.hh
+++ b/src/base/compiler.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -43,6 +43,8 @@
 #ifndef __BASE_COMPILER_HH__
 #define __BASE_COMPILER_HH__

+#include 
+
 // http://gcc.gnu.org/onlinedocs/gcc/Function-Attributes.html

 #if defined(__GNUC__) // clang or gcc
@@ -61,4 +63,28 @@
 #  define M5_CLASS_VAR_USED
 #endif

+// std::make_unique redefined for C++11 compilers
+namespace m5
+{
+
+#if __cplusplus == 201402L // C++14
+
+using std::make_unique;
+
+#else // C++11
+
+/** Defining custom version of make_unique: m5::make_unique<>() */
+template
+std::unique_ptr
+make_unique( Args&&... constructor_args )
+{
+return std::unique_ptr(
+   new T( std::forward(constructor_args)... )
+   );
+}
+
+#endif // __cplusplus == 201402L
+
+} //namespace m5
+
 #endif // __BASE_COMPILER_HH__

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Gerrit-MessageType: merged
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Gerrit-Change-Number: 5201
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in public/gem5[master]: base: Function for mirroring bits in variable length word

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5261 )


Change subject: base: Function for mirroring bits in variable length word
..

base: Function for mirroring bits in variable length word

This patch introduces a high-speed template function for mirroring the
bits (MSB=>LSB) in a variable length word. The function is achieving
high performances since it is using a look-up table.

Change-Id: Ib0d0480e68d902f25655f74d243de305103eff75
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/5261
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/base/SConscript
A src/base/bitfield.cc
M src/base/bitfield.hh
3 files changed, 104 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/src/base/SConscript b/src/base/SConscript
index 74a248b..1ca0e35 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -34,6 +34,7 @@
 SimObject('CPA.py')
 Source('cp_annotate.cc')
 Source('atomicio.cc')
+Source('bitfield.cc')
 Source('bigint.cc')
 Source('bitmap.cc')
 Source('callback.cc')
diff --git a/src/base/bitfield.cc b/src/base/bitfield.cc
new file mode 100644
index 000..0650a8c
--- /dev/null
+++ b/src/base/bitfield.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Giacomo Travaglini
+ */
+
+#include "base/bitfield.hh"
+
+/** Lookup table used for High Speed bit reversing */
+const uint8_t reverseLookUpTable[] =
+{
+0x00, 0x80, 0x40, 0xC0, 0x20, 0xA0, 0x60, 0xE0, 0x10, 0x90, 0x50, 0xD0,
+0x30, 0xB0, 0x70, 0xF0, 0x08, 0x88, 0x48, 0xC8, 0x28, 0xA8, 0x68, 0xE8,
+0x18, 0x98, 0x58, 0xD8, 0x38, 0xB8, 0x78, 0xF8, 0x04, 0x84, 0x44, 0xC4,
+0x24, 0xA4, 0x64, 0xE4, 0x14, 0x94, 0x54, 0xD4, 0x34, 0xB4, 0x74, 0xF4,
+0x0C, 0x8C, 0x4C, 0xCC, 0x2C, 0xAC, 0x6C, 0xEC, 0x1C, 0x9C, 0x5C, 0xDC,
+0x3C, 0xBC, 0x7C, 0xFC, 0x02, 0x82, 0x42, 0xC2, 0x22, 0xA2, 0x62, 0xE2,
+0x12, 0x92, 0x52, 0xD2, 0x32, 0xB2, 0x72, 0xF2, 0x0A, 0x8A, 0x4A, 0xCA,
+0x2A, 0xAA, 0x6A, 0xEA, 0x1A, 0x9A, 0x5A, 0xDA, 0x3A, 0xBA, 0x7A, 0xFA,
+0x06, 0x86, 0x46, 0xC6, 0x26, 0xA6, 0x66, 0xE6, 0x16, 0x96, 0x56, 0xD6,
+0x36, 0xB6, 0x76, 0xF6, 0x0E, 0x8E, 0x4E, 0xCE, 0x2E, 0xAE, 0x6E, 0xEE,
+0x1E, 0x9E, 0x5E, 0xDE, 0x3E, 0xBE, 0x7E, 0xFE, 0x01, 0x81, 0x41, 0xC1,
+0x21, 0xA1, 0x61, 0xE1, 0x11, 0x91, 0x51, 0xD1, 0x31, 0xB1, 0x71, 0xF1,
+0x09, 0x89, 0x49, 0xC9, 0x29, 0xA9, 0x69, 0xE9, 0x19, 0x99, 0x59, 0xD9,
+0x39, 0xB9, 0x79, 0xF9, 0x05, 0x85, 0x45, 0xC5, 0x25, 0xA5, 0x65, 0xE5,
+0x15, 0x95, 

[gem5-dev] Change in public/gem5[master]: arch-arm: RBIT instruction using mirroring func

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5262 )


Change subject: arch-arm: RBIT instruction using mirroring func
..

arch-arm: RBIT instruction using mirroring func

The high speed bit-reversing function is now used
for the Aarch64/32 RBIT instruction implementation.

Change-Id: Id5a8a93d928d00fd33ec4061fbb586b8420a1c1b
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/5262
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/isa/insts/misc.isa
2 files changed, 2 insertions(+), 23 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/isa/insts/data64.isa  
b/src/arch/arm/isa/insts/data64.isa

index 48fc87c..3284d5b 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -248,18 +248,7 @@
 Dest64 = (Op164 == 0) ? intWidth : (intWidth - 1 -  
findMsbSet(Op164));

 ''')
 buildDataXRegInst("rbit", 1, '''
-uint64_t result = Op164;
-uint64_t lBit = 1ULL << (intWidth - 1);
-uint64_t rBit = 1ULL;
-while (lBit > rBit) {
-uint64_t maskBits = lBit | rBit;
-uint64_t testBits = result & maskBits;
-// If these bits are different, swap them by toggling them.
-if (testBits && testBits != maskBits)
-result ^= maskBits;
-lBit >>= 1; rBit <<= 1;
-}
-Dest64 = result;
+Dest64 = reverseBits(Op164, intWidth/8);
 ''')
 buildDataXRegInst("rev", 1, '''
 if (intWidth == 32)
diff --git a/src/arch/arm/isa/insts/misc.isa  
b/src/arch/arm/isa/insts/misc.isa

index 5eda615..edeb0f6 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -329,17 +329,7 @@
 exec_output += PredOpExecute.subst(revshIop)

 rbitCode = '''
-uint8_t *opBytes = (uint8_t *)
-uint32_t resTemp;
-uint8_t *destBytes = (uint8_t *)
-// This reverses the bytes and bits of the input, or so says the
-// internet.
-for (int i = 0; i < 4; i++) {
-uint32_t temp = opBytes[i];
-temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
-destBytes[3 - i] = (temp * 0x10101) >> 16;
-}
-Dest = resTemp;
+Dest = reverseBits(Op1);
 '''
 rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
 { "code": rbitCode,

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Gerrit-Change-Id: Id5a8a93d928d00fd33ec4061fbb586b8420a1c1b
Gerrit-Change-Number: 5262
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in public/gem5[master]: arch-arm: isSecureBelow from armarm pseudocode

[Giacomo Travaglini (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/7221

to review the following change.


Change subject: arch-arm: isSecureBelow from armarm pseudocode
..

arch-arm: isSecureBelow from armarm pseudocode

This patch introduces the inSecureBelow pseudocode function
defined in the armarm documentation. It also replaces the
inSecureState function call which was improperly used in
ELIs32: we might be in secure state (EL3), but with non-secure
lower ELs (SCR.NS = 1).

Change-Id: I01febcb54392ad4e51e785b4d5153aeb3437c778
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Chuan Zhu 
---
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
2 files changed, 20 insertions(+), 6 deletions(-)



diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 56503ac..a49f829 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009-2014, 2016-2017 ARM Limited
+ * Copyright (c) 2009-2014, 2016-2018 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -184,6 +184,13 @@
 scr, tc->readMiscReg(MISCREG_CPSR));
 }

+inline bool
+isSecureBelowEL3(ThreadContext *tc)
+{
+SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
+}
+
 bool
 inAArch64(ThreadContext *tc)
 {
@@ -256,8 +263,8 @@

 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 bool aarch32_at_el1 = (aarch32_below_el3
-|| (have_el2
-&& !inSecureState(tc) && hcr.rw == 0));
+   || (have_el2
+   && !isSecureBelowEL3(tc) && hcr.rw == 0));

 // Only know if EL0 using AArch32 from PSTATE
 if (el == EL0 && !aarch32_at_el1) {
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 622fd12..6e4e76b 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2016-2017 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -201,10 +201,17 @@
 }
 }

-bool longDescFormatInUse(ThreadContext *tc);
-
 bool inSecureState(ThreadContext *tc);

+/**
+ * Return TRUE if an Exception level below EL3 is in Secure state.
+ * Differs from inSecureState in that it ignores the current EL
+ * or Mode in considering security state.
+ */
+inline bool isSecureBelowEL3(ThreadContext *tc);
+
+bool longDescFormatInUse(ThreadContext *tc);
+
 uint32_t getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);

 static inline uint32_t

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[gem5-dev] Change in public/gem5[master]: arch-arm: ELUsingAArch32K from armarm pseudocode

[Giacomo Travaglini (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/7222

to review the following change.


Change subject: arch-arm: ELUsingAArch32K from armarm pseudocode
..

arch-arm: ELUsingAArch32K from armarm pseudocode

This patch implements the ELUsingAArch32K pseudocode, which is returning
true if the provided Exception Level is using A32 ISA, but it is not
panicking (quitting simulation) if the information is unknown (see
documentation).
The panicking is the current behaviour of the ELIs32 utility in gem5.

Change-Id: Iad7b56077d7e0f8ee223b5b9593cb8097f26bb29
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
2 files changed, 44 insertions(+), 11 deletions(-)



diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index a49f829..4e99d98 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -243,20 +243,31 @@
 bool
 ELIs32(ThreadContext *tc, ExceptionLevel el)
 {
-// Return true if the specified EL is in aarch32 state.
+bool known, aarch32;
+std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
+panic_if(!known, "EL state is UNKNOWN");
+return aarch32;
+}

+std::pair
+ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
+{
+// Return true if the specified EL is in aarch32 state.
 const bool have_el3 = ArmSystem::haveSecurity(tc);
 const bool have_el2 = ArmSystem::haveVirtualization(tc);

 panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't  
exist");
 panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't  
exist");


-if (ArmSystem::highestELIs64(tc)
-  && ArmSystem::highestEL(tc) == el) {
-return false;
+bool known, aarch32;
+known = aarch32 = false;
+if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) {
+// Target EL is the highest one in a system where
+// the highest is using AArch64.
+known = true; aarch32 = false;
 } else if (!ArmSystem::highestELIs64(tc)) {
-// All levels are using AArch32
-return true;
+// All ELs are using AArch32:
+known = true; aarch32 = true;
 } else {
 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 bool aarch32_below_el3 = (have_el3 && scr.rw == 0);
@@ -268,15 +279,19 @@

 // Only know if EL0 using AArch32 from PSTATE
 if (el == EL0 && !aarch32_at_el1) {
-CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
-panic_if(cpsr.el != EL0, "EL0 state is UNKNOWN");
 // EL0 controlled by PSTATE
-return cpsr.width != 0;
+CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+
+known = (cpsr.el == EL0);
+aarch32 = (cpsr.width == 1);
 } else {
-return (aarch32_below_el3 && el != EL3)
- || (aarch32_at_el1 && (el == EL0 || el == EL1) );
+known = true;
+aarch32 = (aarch32_below_el3 && el != EL3)
+  || (aarch32_at_el1 && (el == EL0 || el == EL1) );
 }
 }
+
+return std::make_pair(known, aarch32);
 }

 bool
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 6e4e76b..8efe4ad 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -157,6 +157,24 @@
 return (ExceptionLevel) (uint8_t) cpsr.el;
 }

+/**
+ * This function checks whether selected EL provided as an argument
+ * is using the AArch32 ISA. This information might be unavailable
+ * at the current EL status: it hence returns a pair of boolean values:
+ * a first boolean, true if information is available (known),
+ * and a second one, true if EL is using AArch32, false for AArch64.
+ *
+ * @param tc The thread context.
+ * @param el The target exception level.
+ * @retval known is FALSE for EL0 if the current Exception level
+ *   is not EL0 and EL1 is using AArch64, since it cannot
+ *   determine the state of EL0; TRUE otherwise.
+ * @retval aarch32 is TRUE if the specified Exception level is using  
AArch32;

+ * FALSE otherwise.
+ */
+std::pair
+ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el);
+
 bool ELIs32(ThreadContext *tc, ExceptionLevel el);

 bool ELIs64(ThreadContext *tc, ExceptionLevel el);

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Gerrit-Change-Number: 7222
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 

[gem5-dev] Change in public/gem5[master]: arch-arm: Correct Illegal Exception Return detection

[Giacomo Travaglini (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/7223

to review the following change.


Change subject: arch-arm: Correct Illegal Exception Return detection
..

arch-arm: Correct Illegal Exception Return detection

Fixed Illegal Exception Return detection, which was not
covering all the documented cases.

Change-Id: If08ddc1490d1c0a1fccee1489d116384770ce0a5
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/insts/static_inst.cc
1 file changed, 19 insertions(+), 6 deletions(-)



diff --git a/src/arch/arm/insts/static_inst.cc  
b/src/arch/arm/insts/static_inst.cc

index eeda3ad..61f31e5 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2014, 2016-2017 ARM Limited
+ * Copyright (c) 2010-2014, 2016-2018 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -897,27 +897,40 @@

 const OperatingMode cur_mode = (OperatingMode) (uint8_t)cpsr.mode;
 const ExceptionLevel target_el = opModeToEL(mode);
+
+HCR hcr = ((HCR)tc->readMiscReg(MISCREG_HCR_EL2));
+SCR scr = ((SCR)tc->readMiscReg(MISCREG_SCR_EL3));
+
 if (target_el > opModeToEL(cur_mode))
 return true;

-if (target_el == EL3 && !ArmSystem::haveSecurity(tc))
+if (!ArmSystem::haveEL(tc, target_el))
 return true;

-if (target_el == EL2 && !ArmSystem::haveVirtualization(tc))
+if (target_el == EL1 && ArmSystem::haveEL(tc, EL2) && scr.ns &&  
hcr.tge)

+return true;
+
+if (target_el == EL2 && ArmSystem::haveEL(tc, EL3) && !scr.ns)
+return true;
+
+bool spsr_mode_is_aarch32 = (spsr.width == 1);
+bool known, target_el_is_aarch32;
+std::tie(known, target_el_is_aarch32) = ELUsingAArch32K(tc, target_el);
+assert(known || (target_el == EL0 && ELIs64(tc, EL1)));
+
+if (known && (spsr_mode_is_aarch32 != target_el_is_aarch32))
 return true;

 if (!spsr.width) {
 // aarch64
 if (!ArmSystem::highestELIs64(tc))
 return true;
-
 if (spsr & 0x2)
 return true;
 if (target_el == EL0 && spsr.sp)
 return true;
-if (target_el == EL2  
&& !((SCR)tc->readMiscReg(MISCREG_SCR_EL3)).ns)

-return false;
 } else {
+// aarch32
 return badMode32(mode);
 }


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[gem5-dev] Change in public/gem5[master]: arch-arm: Fix incorrect assumptions in ELIs64

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/7141

to review the following change.


Change subject: arch-arm: Fix incorrect assumptions in ELIs64
..

arch-arm: Fix incorrect assumptions in ELIs64

The state of EL1 wasn't determined correctly when running in secure
mode if virtualisation was enabled. This changset updates the
implementation to match the canonical behavior from the ARM ARM.

Change-Id: I7ed6f5c003617773603f678667aac069d73b6f62
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
2 files changed, 41 insertions(+), 27 deletions(-)



diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index b26564c..56503ac 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009-2014, 2016 ARM Limited
+ * Copyright (c) 2009-2014, 2016-2017 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -230,33 +230,45 @@
 bool
 ELIs64(ThreadContext *tc, ExceptionLevel el)
 {
-if (ArmSystem::highestEL(tc) == el)
-// Register width is hard-wired
-return ArmSystem::highestELIs64(tc);
+return !ELIs32(tc, el);
+}

-switch (el) {
-  case EL0:
-return opModeIs64(currOpMode(tc));
-  case EL1:
-{
-if (ArmSystem::haveVirtualization(tc)) {
-HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
-return hcr.rw;
-} else if (ArmSystem::haveSecurity(tc)) {
-SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
-return scr.rw;
-}
-panic("must haveSecurity(tc)");
+bool
+ELIs32(ThreadContext *tc, ExceptionLevel el)
+{
+// Return true if the specified EL is in aarch32 state.
+
+const bool have_el3 = ArmSystem::haveSecurity(tc);
+const bool have_el2 = ArmSystem::haveVirtualization(tc);
+
+panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't  
exist");
+panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't  
exist");

+
+if (ArmSystem::highestELIs64(tc)
+  && ArmSystem::highestEL(tc) == el) {
+return false;
+} else if (!ArmSystem::highestELIs64(tc)) {
+// All levels are using AArch32
+return true;
+} else {
+SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+bool aarch32_below_el3 = (have_el3 && scr.rw == 0);
+
+HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+bool aarch32_at_el1 = (aarch32_below_el3
+|| (have_el2
+&& !inSecureState(tc) && hcr.rw == 0));
+
+// Only know if EL0 using AArch32 from PSTATE
+if (el == EL0 && !aarch32_at_el1) {
+CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+panic_if(cpsr.el != EL0, "EL0 state is UNKNOWN");
+// EL0 controlled by PSTATE
+return cpsr.width != 0;
+} else {
+return (aarch32_below_el3 && el != EL3)
+ || (aarch32_at_el1 && (el == EL0 || el == EL1) );
 }
-  case EL2:
-{
-assert(ArmSystem::haveSecurity(tc));
-SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
-return scr.rw;
-}
-  default:
-panic("Invalid exception level");
-break;
 }
 }

diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 640ba70..622fd12 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2016 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2016-2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -157,6 +157,8 @@
 return (ExceptionLevel) (uint8_t) cpsr.el;
 }

+bool ELIs32(ThreadContext *tc, ExceptionLevel el);
+
 bool ELIs64(ThreadContext *tc, ExceptionLevel el);

 bool isBigEndian64(ThreadContext *tc);

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[gem5-dev] Change in public/gem5[master]: cpu: MinorCPU handling IsSquashAfter flag

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5702 )


Change subject: cpu: MinorCPU handling IsSquashAfter flag
..

cpu: MinorCPU handling IsSquashAfter flag

MinorCPU was not handling IsSquashAfter flagged instructions. The
behaviour was to force a branch (hence enforcing refetching) for
SerializeAfter instructions only. This has now been extended to
SquashAfter in order to correctly support ISB barrier instruction
behaviour.

Change-Id: Ie525b23350b0de121372d3b98b433e36b097d5c4
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/5702
Reviewed-by: Gabe Black 
Maintainer: Andreas Sandberg 
---
M src/cpu/minor/execute.cc
1 file changed, 4 insertions(+), 3 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index a38a767..7b76ca2 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -219,13 +219,14 @@
 const TheISA::PCState _before = inst->pc;
 TheISA::PCState target = thread->pcState();

-/* Force a branch for SerializeAfter instructions at the end of  
micro-op

- *  sequence when we're not suspended */
+/* Force a branch for SerializeAfter/SquashAfter instructions
+ * at the end of micro-op sequence when we're not suspended */
 bool force_branch = thread->status() != ThreadContext::Suspended &&
 !inst->isFault() &&
 inst->isLastOpInInst() &&
 (inst->staticInst->isSerializeAfter() ||
-inst->staticInst->isIprAccess());
+ inst->staticInst->isSquashAfter() ||
+ inst->staticInst->isIprAccess());

 DPRINTF(Branch, "tryToBranch before: %s after: %s%s\n",
 pc_before, target, (force_branch ? " (forcing)" : ""));

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Gerrit-Change-Id: Ie525b23350b0de121372d3b98b433e36b097d5c4
Gerrit-Change-Number: 5702
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Removing Serializing flag from ISB

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5701 )


Change subject: arch-arm: Removing Serializing flag from ISB
..

arch-arm: Removing Serializing flag from ISB

ISB Serializing behaviour is guaranteed by IsSquashAfter,
which is inherently serializing; when instruction is commited,
consecutive instructions are flushed and refetched.

Change-Id: I05e61b4cf9f01113d95b1502c996d04cbd69b759
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/5701
Maintainer: Andreas Sandberg 
---
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/misc64.isa
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/isa/insts/misc.isa  
b/src/arch/arm/isa/insts/misc.isa

index ae8474f..5fd18c4 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -1154,7 +1154,7 @@
 isbIop = InstObjParams("isb", "Isb", "ImmOp",
  {"code": isbCode,
"predicate_test": predicateTest},
-['IsSerializeAfter', 'IsSquashAfter'])
+['IsSquashAfter'])
 header_output += ImmOpDeclare.subst(isbIop)
 decoder_output += ImmOpConstructor.subst(isbIop)
 exec_output += PredOpExecute.subst(isbIop)
diff --git a/src/arch/arm/isa/insts/misc64.isa  
b/src/arch/arm/isa/insts/misc64.isa

index dd6711e..2483b75 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -140,7 +140,7 @@
 exec_output += BasicExecute.subst(unknown64Iop)

 isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst", "",
-   ['IsSerializeAfter', 'IsSquashAfter'])
+   ['IsSquashAfter'])
 header_output += BasicDeclare.subst(isbIop)
 decoder_output += BasicConstructor64.subst(isbIop)
 exec_output += BasicExecute.subst(isbIop)

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Gerrit-Change-Id: I05e61b4cf9f01113d95b1502c996d04cbd69b759
Gerrit-Change-Number: 5701
Gerrit-PatchSet: 5
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[gem5-dev] Change in public/gem5[master]: arch-arm: Handle route to EL2 in Supervisor Trap

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/7961 )


Change subject: arch-arm: Handle route to EL2 in Supervisor Trap
..

arch-arm: Handle route to EL2 in Supervisor Trap

Supervisor Trap is supposed to be able to handle exceptions routed
to EL2, which is enabled by HCR_EL2.TGE. This fix adds routeToHyp()
function to Supervisor Trap to handle this, similar to that in
UndefinedFault, DataAbort, etc.

Change-Id: I1fcf9f2d445ecbc13c8f6d3b7d599728b0250ab7
Reviewed-by: Jack Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/7961
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 32 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index d143056..27894e0 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2014, 2016-2017 ARM Limited
+ * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -923,10 +923,37 @@
 return (from64 ? EC_SMC_64 : vals.ec);
 }

+bool
+SupervisorTrap::routeToHyp(ThreadContext *tc) const
+{
+bool toHyp = false;
+
+SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
+HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
+
+// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
+toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
+return toHyp;
+}
+
+uint32_t
+SupervisorTrap::iss() const
+{
+// If SupervisorTrap is routed to hypervisor, iss field is 0.
+if (hypRouted) {
+return 0;
+}
+return issRaw;
+}
+
 ExceptionClass
 SupervisorTrap::ec(ThreadContext *tc) const
 {
-return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
+if (hypRouted)
+return EC_UNKNOWN;
+else
+return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
 }

 ExceptionClass
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index fa6740a..bec2c0e 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2016-2017 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -335,6 +335,8 @@
 overrideEc(_overrideEc)
 {}

+bool routeToHyp(ThreadContext *tc) const override;
+uint32_t iss() const override;
 ExceptionClass ec(ThreadContext *tc) const override;
 };


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Gerrit-Change-Number: 7961
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[gem5-dev] Change in public/gem5[master]: arch-arm: Don't change PSTATE in Illegal Exception return

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8021 )


Change subject: arch-arm: Don't change PSTATE in Illegal Exception return
..

arch-arm: Don't change PSTATE in Illegal Exception return

This patch fixes the Illegal Exception return handler. According to the
armarm documentation, when PSTATE.IL is set to one because of an illegal
exception return, PSTATE.{EL, nRW, SP} are unchanged. This means the
Exception level, Execution state, and stack pointer selection do not
change as a result of the return.

Change-Id: I35f2fe68fb2822a54fc4a21930871eab7a1aaab4
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/8021
Maintainer: Andreas Sandberg 
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa.cc
2 files changed, 11 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/insts/static_inst.cc  
b/src/arch/arm/insts/static_inst.cc

index aace1de..a7ba91e 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1018,7 +1018,17 @@
 new_cpsr.ss = 0;

 if (illegalExceptionReturn(tc, cpsr, spsr)) {
+// If the SPSR specifies an illegal exception return,
+// then PSTATE.{M, nRW, EL, SP} are unchanged and PSTATE.IL
+// is set to 1.
 new_cpsr.il = 1;
+if (cpsr.width) {
+new_cpsr.mode = cpsr.mode;
+} else {
+new_cpsr.width = cpsr.width;
+new_cpsr.el = cpsr.el;
+new_cpsr.sp = cpsr.sp;
+}
 } else {
 new_cpsr.il = spsr.il;
 if (spsr.width && badMode32((OperatingMode)(uint8_t)spsr.mode)) {
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index c917aba..5d34e18 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -726,7 +726,7 @@
 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
 int old_mode = old_cpsr.mode;
 CPSR cpsr = val;
-if (old_mode != cpsr.mode) {
+if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
 getITBPtr(tc)->invalidateMiscReg();
 getDTBPtr(tc)->invalidateMiscReg();
 }

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Gerrit-Change-Number: 8021
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[gem5-dev] Change in public/gem5[master]: arch-arm: Correct SecureMonitorTrap vals for aarch32

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/8041

to review the following change.


Change subject: arch-arm: Correct SecureMonitorTrap vals for aarch32
..

arch-arm: Correct SecureMonitorTrap vals for aarch32

This patch replaces the dummy values which were defined for the
SecureMonitorTrap thus enabling its usage in aarch32 mode.  1) It
changes the vector table offset from 0x14 to 0x4 in compliance with the
armv8 documentation.  2) When trapping in monitor mode for aarch32, the
mon_lr is updated with the pc + a non zero offset (+4/2 depending on the
current instruction set: +4 for A32, +2 for T32).

Change-Id: I01e1e52bf5ecd405e7472e31e01cf9a599153b08
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/faults.cc
1 file changed, 4 insertions(+), 5 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 27894e0..b3c1b07 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -237,6 +237,10 @@
 "Hypervisor Trap",   0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
 };
+template<> ArmFault::FaultVals ArmFaultVals::vals = {
+"Secure Monitor Trap",   0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON,
+4, 2, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
+};
 template<> ArmFault::FaultVals ArmFaultVals::vals = {
 "IRQ",   0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
 4, 4, 0, 0, false, true,  false, EC_UNKNOWN, FaultStat()
@@ -258,11 +262,6 @@
 "Supervisor Trap",   0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
 };
-template<> ArmFault::FaultVals ArmFaultVals::vals = {
-// Some dummy values (SecureMonitorTrap is AArch64-only)
-"Secure Monitor Trap",   0x014, 0x000, 0x200, 0x400, 0x600, MODE_MON,
-0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
-};
 template<> ArmFault::FaultVals ArmFaultVals::vals = {
 // Some dummy values (PCAlignmentFault is AArch64-only)
 "PC Alignment Fault",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,

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[gem5-dev] Change in public/gem5[master]: arch-arm: Fixed error in choosing vector offset

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8001 )


Change subject: arch-arm: Fixed error in choosing vector offset
..

arch-arm: Fixed error in choosing vector offset

The old code chose vector offset associated with exceptions taken
to EL3 by incorrectly using "from64", which is associated with the
exception level where the exception was taken from. However, the
offset should depends on the ISA of the lower EL and not of the
starting EL itself, as specified in ARM ARM. This patch corrects
this by implementing the method in AArch64.TakeException in ARM ARM.

Change-Id: I8f7c9aa777c5f2eef9e2d89c36e9daee23f3a822
Reviewed-by: Jack Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/8001
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 31 insertions(+), 14 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 27894e0..e3488f4 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -350,7 +350,7 @@
 panic("Invalid target exception level");
 break;
 }
-return vbar + offset64();
+return vbar + offset64(tc);
 }

 MiscRegIndex
@@ -654,6 +654,8 @@
 ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset();
 tc->setMiscReg(elr_idx, ret_addr);

+Addr vec_address = getVector64(tc);
+
 // Update process state
 OperatingMode64 mode = 0;
 mode.spX = 1;
@@ -666,7 +668,7 @@
 tc->setMiscReg(MISCREG_CPSR, cpsr);

 // Set PC to start of exception handler
-Addr new_pc = purifyTaggedAddr(getVector64(tc), tc, toEL);
+Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL);
 DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x  
PC:%#x "
 "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr,  
new_pc);

 PCState pc(new_pc);
@@ -893,6 +895,31 @@
 return isHypTrap ? 0x14 : vals.offset;
 }

+template
+FaultOffset
+ArmFaultVals::offset64(ThreadContext *tc)
+{
+if (toEL == fromEL) {
+if (opModeIsT(fromMode))
+return vals.currELTOffset;
+return vals.currELHOffset;
+} else {
+bool lower_32 = false;
+if (toEL == EL3) {
+if (!inSecureState(tc) && ArmSystem::haveEL(tc, EL2))
+lower_32 = ELIs32(tc, EL2);
+else
+lower_32 = ELIs32(tc, EL1);
+} else {
+lower_32 = ELIs32(tc, static_cast(toEL - 1));
+}
+
+if (lower_32)
+return vals.lowerEL32Offset;
+return vals.lowerEL64Offset;
+}
+}
+
 // void
 // SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx)
 // {
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index bec2c0e..6ae4c06 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -191,7 +191,7 @@
 virtual void annotate(AnnotationIDs id, uint64_t val) {}
 virtual FaultStat& countStat() = 0;
 virtual FaultOffset offset(ThreadContext *tc) = 0;
-virtual FaultOffset offset64() = 0;
+virtual FaultOffset offset64(ThreadContext *tc) = 0;
 virtual OperatingMode nextMode() = 0;
 virtual bool routeToMonitor(ThreadContext *tc) const = 0;
 virtual bool routeToHyp(ThreadContext *tc) const { return false; }
@@ -221,17 +221,7 @@
 FaultStat & countStat() override { return vals.count; }
 FaultOffset offset(ThreadContext *tc) override;

-FaultOffset offset64() override {
-if (toEL == fromEL) {
-if (opModeIsT(fromMode))
-return vals.currELTOffset;
-return vals.currELHOffset;
-} else {
-if (from64)
-return vals.lowerEL64Offset;
-return vals.lowerEL32Offset;
-}
-}
+FaultOffset offset64(ThreadContext *tc) override;

 OperatingMode nextMode() override { return vals.nextMode; }
 virtual bool routeToMonitor(ThreadContext *tc) const override {

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Gerrit-Change-Id: I8f7c9aa777c5f2eef9e2d89c36e9daee23f3a822
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Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Don't change PSTATE in Illegal Exception return

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8021

to look at the new patch set (#2).

Change subject: arch-arm: Don't change PSTATE in Illegal Exception return
..

arch-arm: Don't change PSTATE in Illegal Exception return

This patch fixes the Illegal Exception return handler. According to the
armarm documentation, when PSTATE.IL is set to one because of an illegal
exception return, PSTATE.{EL, nRW, SP} are unchanged. This means the
Exception level, Execution state, and stack pointer selection do not
change as a result of the return.

Change-Id: I35f2fe68fb2822a54fc4a21930871eab7a1aaab4
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa.cc
2 files changed, 11 insertions(+), 1 deletion(-)


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Gerrit-Change-Number: 8021
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: arch-arm: IMPLEMENTATION DEFINED register

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/7922

to review the following change.


Change subject: arch-arm: IMPLEMENTATION DEFINED register
..

arch-arm: IMPLEMENTATION DEFINED register

A new pseudo register has been added to the Misc pool. It is the
implementation defined register. This kinds of registers are covered by
the architecture and must be treated differently than UNIMPLEMENTED
registers: their access can be trapped to EL2 (See HCR.TIDCP bit in the
arm arm).
Some previously undecoded registers in c9,c10,c11 have now this register
type.

Change-Id: Ibfc35982470b9dea0ecf39aaa6b1012a21852f53
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/insts/pseudo.cc
M src/arch/arm/insts/pseudo.hh
M src/arch/arm/isa/formats/misc.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
5 files changed, 88 insertions(+), 11 deletions(-)



diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc
index 40e00ac..e2504d6 100644
--- a/src/arch/arm/insts/pseudo.cc
+++ b/src/arch/arm/insts/pseudo.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014,2016-2017 ARM Limited
+ * Copyright (c) 2014,2016-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -181,10 +181,8 @@
 fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
 }

-
-
 McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst  
_machInst,

- uint64_t _iss, MiscRegIndex _miscReg)
+   uint64_t _iss, MiscRegIndex _miscReg)
 : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
 {
 flags[IsNonSpeculative] = true;
@@ -217,3 +215,37 @@
 {
 return csprintf("%-10s (pipe flush)", mnemonic);
 }
+
+McrMrcImplDefined::McrMrcImplDefined(const char *_mnemonic,
+ ExtMachInst _machInst, uint64_t _iss,
+ MiscRegIndex _miscReg)
+: McrMrcMiscInst(_mnemonic, _machInst, _iss, _miscReg)
+{}
+
+Fault
+McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData)  
const

+{
+uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR);
+uint32_t hcr = xc->readMiscReg(MISCREG_HCR);
+uint32_t scr = xc->readMiscReg(MISCREG_SCR);
+uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR);
+uint32_t hstr = xc->readMiscReg(MISCREG_HSTR);
+uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR);
+
+bool hypTrap  = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr,
+  hcptr, iss);
+if (hypTrap) {
+return std::make_shared(machInst, iss,
+EC_TRAPPED_CP15_MCR_MRC);
+} else {
+return std::make_shared(machInst, false,
+  mnemonic);
+}
+}
+
+std::string
+McrMrcImplDefined::generateDisassembly(Addr pc,
+   const SymbolTable *symtab) const
+{
+return csprintf("%-10s (implementation defined)", mnemonic);
+}
diff --git a/src/arch/arm/insts/pseudo.hh b/src/arch/arm/insts/pseudo.hh
index fe28789..5fb7499 100644
--- a/src/arch/arm/insts/pseudo.hh
+++ b/src/arch/arm/insts/pseudo.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014,2016 ARM Limited
+ * Copyright (c) 2014,2016,2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -123,7 +123,7 @@
  */
 class McrMrcMiscInst : public ArmStaticInst
 {
-  private:
+  protected:
 uint64_t iss;
 MiscRegIndex miscReg;

@@ -138,4 +138,21 @@

 };

+/**
+ * This class is also used for IMPLEMENTATION DEFINED registers, whose  
mcr/mrc

+ * behaviour is trappable even for unimplemented registers.
+ */
+class McrMrcImplDefined : public McrMrcMiscInst
+{
+  public:
+McrMrcImplDefined(const char *_mnemonic, ExtMachInst _machInst,
+  uint64_t _iss, MiscRegIndex _miscReg);
+
+Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+
+std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+};
+
 #endif
diff --git a/src/arch/arm/isa/formats/misc.isa  
b/src/arch/arm/isa/formats/misc.isa

index 4f834b8..a9acc21 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010-2013,2016-2017 ARM Limited
+// Copyright (c) 2010-2013,2016-2018 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -219,6 +219,11 @@
 machInst,
 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s  
unknown",

 crn, opc1, crm, opc2, isRead ? "read" : "write"));
+  case 

[gem5-dev] Change in public/gem5[master]: arch-arm: Arch regs and pseudo regs distinction

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/7921

to review the following change.


Change subject: arch-arm: Arch regs and pseudo regs distinction
..

arch-arm: Arch regs and pseudo regs distinction

A new identifier has been introduced: NUM_PHYS_MISCREGS, which is used
as a boundary for the number of physical (real) Misc registers in the
system.  Pseudo registers (like CP15_UNIMPL) have been moved after the
NUM_PHYS_MISCREGS identifier, so that their enum number is
(NUM_PHYS_MISCREGS < number < NUM_MISCREGS).  Moving away those
registers has created some free slots that can be used for future Misc
register implementation.
SERIALIZE and UNSERIALIZE now only save/restore PHYSICAL Misc Registers.
This allows us to define as many pseudo registers as we want without
being concerned about checkpoint compatibility.

Change-Id: I7e297b814eeaa4bee640e81bee625fb66710af45
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa.hh
M src/arch/arm/miscregs.hh
2 files changed, 38 insertions(+), 12 deletions(-)



diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 1711ee0..aa905e5 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2017 ARM Limited
+ * Copyright (c) 2010, 2012-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -629,7 +629,7 @@
 void serialize(CheckpointOut ) const
 {
 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
-SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
+SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);

 SERIALIZE_SCALAR(highestELIs64);
 SERIALIZE_SCALAR(haveSecurity);
@@ -641,7 +641,7 @@
 void unserialize(CheckpointIn )
 {
 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
-UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
+UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
 updateRegMap(tmp_cpsr);

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 779ead7..12f6f3f 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2017 ARM Limited
+ * Copyright (c) 2010-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -666,15 +666,32 @@
 MISCREG_CBAR_EL1,   // 598
 MISCREG_CONTEXTIDR_EL2, // 599

-// Dummy registers
-MISCREG_NOP,// 600
-MISCREG_RAZ,// 601
-MISCREG_CP14_UNIMPL,// 602
-MISCREG_CP15_UNIMPL,// 603
-MISCREG_A64_UNIMPL, // 604
-MISCREG_UNKNOWN,// 605
+// These MISCREG_FREESLOT are available Misc Register
+// slots for future registers to be implemented.
+MISCREG_FREESLOT_1, // 600
+MISCREG_FREESLOT_2, // 601
+MISCREG_FREESLOT_3, // 602
+MISCREG_FREESLOT_4, // 603
+MISCREG_FREESLOT_5, // 604
+MISCREG_FREESLOT_6, // 605

-NUM_MISCREGS// 606
+// NUM_PHYS_MISCREGS specifies the number of actual physical
+// registers, not considering the following pseudo-registers
+// (dummy registers), like UNKNOWN, CP15_UNIMPL...
+// Checkpointing should use this physical index when
+// saving/restoring register values.
+NUM_PHYS_MISCREGS = 606,// 606
+
+// Dummy registers
+MISCREG_NOP,
+MISCREG_RAZ,
+MISCREG_CP14_UNIMPL,
+MISCREG_CP15_UNIMPL,
+MISCREG_A64_UNIMPL,
+MISCREG_UNKNOWN,
+
+// Total number of Misc Registers: Physical + Dummy
+NUM_MISCREGS
 };

 enum MiscRegInfo {
@@ -1348,6 +1365,15 @@
 "cbar_el1",
 "contextidr_el2",

+"freeslot1",
+"freeslot2",
+"freeslot3",
+"freeslot4",
+"freeslot5",
+"freeslot6",
+
+"num_phys_regs",
+
 // Dummy registers
 "nop",
 "raz",

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Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix Secure state check in checkFPAdvSIMDTrap64

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/8081



Change subject: arch-arm: Fix Secure state check in checkFPAdvSIMDTrap64
..

arch-arm: Fix Secure state check in checkFPAdvSIMDTrap64

The old code does secure state check by using "el <= EL2", which
mis-considers secure EL1 and EL0. This patch fixes this by using
inSecureState as in ARM ARM.

Change-Id: I01d847c6af022c1462b16206cbc576f15f5569fd
Reviewed-by: Jack Travaglini 
---
M src/arch/arm/insts/static_inst.cc
1 file changed, 1 insertion(+), 3 deletions(-)



diff --git a/src/arch/arm/insts/static_inst.cc  
b/src/arch/arm/insts/static_inst.cc

index a7ba91e..40a1fe4 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -629,9 +629,7 @@
 Fault
 ArmStaticInst::checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const
 {
-const ExceptionLevel el = (ExceptionLevel) (uint8_t)cpsr.el;
-
-if (ArmSystem::haveVirtualization(tc) && el <= EL2) {
+if (ArmSystem::haveVirtualization(tc) && !inSecureState(tc)) {
 HCPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL2);
 if (cptrEnCheck.tfp)
 return advSIMDFPAccessTrap64(EL2);

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[gem5-dev] Change in public/gem5[master]: sim: Remove _numContexts member in System class

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini merged this change by Giacomo Travaglini. (  
https://gem5-review.googlesource.com/8062 )


Change subject: sim: Remove _numContexts member in System class
..

sim: Remove _numContexts member in System class

A System object has a _numContexts member variable which represent the
number of ThreadContext registered in the System.  Since this has to
match the size of the ThreadContext vector, this patch removes the
manually cached size. This was usually used as a for-loop index, whereas
we want to enforce the use of range-based loops whenever possible.

Change-Id: I1ba317c0393bcc9c1aeebbb1fc22d7b2bc2cf90c
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/8062
Reviewed-by: Gabe Black 
Maintainer: Brandon Potter 
---
M src/arch/arm/kvm/gic.cc
M src/arch/arm/linux/system.cc
M src/sim/system.cc
M src/sim/system.hh
4 files changed, 15 insertions(+), 20 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Brandon Potter: Looks good to me, approved



diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index 887fa8d..d2423a6 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -305,7 +305,7 @@
 MuxingKvmGic::copyBankedDistRange(BaseGicRegisters* from,  
BaseGicRegisters* to,

   Addr daddr, size_t size)
 {
-for (int ctx = 0; ctx < system._numContexts; ++ctx)
+for (int ctx = 0; ctx < system.numContexts(); ++ctx)
 for (auto a = daddr; a < daddr + size; a += 4)
 copyDistRegister(from, to, ctx, a);
 }
@@ -314,7 +314,7 @@
 MuxingKvmGic::clearBankedDistRange(BaseGicRegisters* to,
Addr daddr, size_t size)
 {
-for (int ctx = 0; ctx < system._numContexts; ++ctx)
+for (int ctx = 0; ctx < system.numContexts(); ++ctx)
 for (auto a = daddr; a < daddr + size; a += 4)
 to->writeDistributor(ctx, a, 0x);
 }
@@ -345,7 +345,7 @@
 // Copy CPU Interface Control Register (CTLR),
 //  Interrupt Priority Mask Register (PMR), and
 //  Binary Point Register (BPR)
-for (int ctx = 0; ctx < system._numContexts; ++ctx) {
+for (int ctx = 0; ctx < system.numContexts(); ++ctx) {
 copyCpuRegister(from, to, ctx, GICC_CTLR);
 copyCpuRegister(from, to, ctx, GICC_PMR);
 copyCpuRegister(from, to, ctx, GICC_BPR);
@@ -423,7 +423,7 @@
 // have been shifted by three bits due to its having been emulated by
 // a VGIC with only 5 PMR bits in its VMCR register.  Presently the
 // Linux kernel does not repair this inaccuracy, so we correct it here.
-for (int cpu = 0; cpu < system._numContexts; ++cpu) {
+for (int cpu = 0; cpu < system.numContexts(); ++cpu) {
cpuPriority[cpu] <<= 3;
assert((cpuPriority[cpu] & ~0xff) == 0);
 }
diff --git a/src/arch/arm/linux/system.cc b/src/arch/arm/linux/system.cc
index 7f06475..094e4d7 100644
--- a/src/arch/arm/linux/system.cc
+++ b/src/arch/arm/linux/system.cc
@@ -250,8 +250,7 @@
 std::string task_filename = "tasks.txt";
 taskFile = simout.create(name() + "." + task_filename);

-for (int i = 0; i < _numContexts; i++) {
-ThreadContext *tc = threadContexts[i];
+for (const auto tc : threadContexts) {
 uint32_t pid = tc->getCpuPtr()->getPid();
 if (pid != BaseCPU::invldPid) {
 mapPid(tc, pid);
diff --git a/src/sim/system.cc b/src/sim/system.cc
index ed01e0e..38eed1c 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -47,6 +47,8 @@

 #include "sim/system.hh"

+#include 
+
 #include "arch/remote_gdb.hh"
 #include "arch/utility.hh"
 #include "base/loader/object_file.hh"
@@ -87,7 +89,6 @@

 System::System(Params *p)
 : MemObject(p), _systemPort("system_port", this),
-  _numContexts(0),
   multiThread(p->multi_thread),
   pagePtr(0),
   init_param(p->init_param),
@@ -256,7 +257,6 @@
  "Cannot have two CPUs with the same id (%d)\n", id);

 threadContexts[id] = tc;
-_numContexts++;

 #if THE_ISA != NULL_ISA
 int port = getRemoteGDBPort();
@@ -287,12 +287,13 @@
 int
 System::numRunningContexts()
 {
-int running = 0;
-for (int i = 0; i < _numContexts; ++i) {
-if (threadContexts[i]->status() != ThreadContext::Halted)
-++running;
-}
-return running;
+return std::count_if(
+threadContexts.cbegin(),
+threadContexts.cend(),
+[] (ThreadContext* tc) {
+return tc->status() != ThreadContext::Halted;
+}
+);
 }

 void
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 5b0c178..a72f2a7 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -196,7 +196,6 @@
 #endif

 std::vector threadContexts;
-int 

[gem5-dev] Change in public/gem5[master]: sim: Make Stats truly non-copy-constructible

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini merged this change by Rekai Gonzalez-Alberquilla. (  
https://gem5-review.googlesource.com/8082 )


Change subject: sim: Make Stats truly non-copy-constructible
..

sim: Make Stats truly non-copy-constructible

The stats are silently non-copy constructible. Therefore, when someone
copy-constructs any object with stats, asserts happen when registering
the stats, as they were not constructed in the intended way.

This patch solves that by explicitly deleting the copy constructor,
trading an obscure run-time assert for a compile-time somehow more
meaningful error meassage.

This triggers some compilation errors as the FaultStats in the fault
definitions of ARM and SPARC use brace-enclosed initialisations in which
one of the elements derives from DataWrap, which is not
copy-constructible anymore. To fix that, this patch also adds a
constructor for the FaultVals in both ISAs.

Change-Id: I340e203b9386609b32c66e3b8918a015afe415a4
Reviewed-by: Curtis Dunham 
Reviewed-by: Sascha Bischoff 
Reviewed-on: https://gem5-review.googlesource.com/8082
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Reviewed-by: Gabe Black 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/sparc/faults.cc
M src/arch/sparc/faults.hh
M src/base/statistics.hh
5 files changed, 189 insertions(+), 167 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 0f54906..c36848e 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -198,100 +198,100 @@
 // Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next  
mode,

 // {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap,
 // {A, F} disable, class, stat
-template<> ArmFault::FaultVals ArmFaultVals::vals = {
+template<> ArmFault::FaultVals ArmFaultVals::vals(
 // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED
 // location in AArch64)
 "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
-0, 0, 0, 0, false, true,  true,  EC_UNKNOWN, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals::vals = {
+0, 0, 0, 0, false, true,  true,  EC_UNKNOWN
+);
+template<> ArmFault::FaultVals ArmFaultVals::vals(
 "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600,  
MODE_UNDEFINED,

-4, 2, 0, 0, true,  false, false, EC_UNKNOWN, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals::vals = {
+4, 2, 0, 0, true,  false, false, EC_UNKNOWN
+);
+template<> ArmFault::FaultVals ArmFaultVals::vals(
 "Supervisor Call",   0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
-4, 2, 4, 2, true,  false, false, EC_SVC_TO_HYP, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals::vals = {
+4, 2, 4, 2, true,  false, false, EC_SVC_TO_HYP
+);
+template<> ArmFault::FaultVals ArmFaultVals::vals(
 "Secure Monitor Call",   0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON,
-4, 4, 4, 4, false, true,  true,  EC_SMC_TO_HYP, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals::vals = {
+4, 4, 4, 4, false, true,  true,  EC_SMC_TO_HYP
+);
+template<> ArmFault::FaultVals ArmFaultVals::vals(
 "Hypervisor Call",   0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
-4, 4, 4, 4, true,  false, false, EC_HVC, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals::vals = {
+4, 4, 4, 4, true,  false, false, EC_HVC
+);
+template<> ArmFault::FaultVals ArmFaultVals::vals(
 "Prefetch Abort",0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
-4, 4, 0, 0, true,  true,  false, EC_PREFETCH_ABORT_TO_HYP, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals::vals = {
+4, 4, 0, 0, true,  true,  false, EC_PREFETCH_ABORT_TO_HYP
+);
+template<> ArmFault::FaultVals ArmFaultVals::vals(
 "Data Abort",0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
-8, 8, 0, 0, true,  true,  false, EC_DATA_ABORT_TO_HYP, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals::vals = {
+8, 8, 0, 0, true,  true,  false, EC_DATA_ABORT_TO_HYP
+);
+template<> ArmFault::FaultVals ArmFaultVals::vals(
 "Virtual Data Abort",0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
-8, 8, 0, 0, true,  true,  false, EC_INVALID, FaultStat()
-};
-template<> ArmFault::FaultVals ArmFaultVals::vals = {
+8, 8, 0, 0, true,  true,  false, EC_INVALID
+);
+template<> ArmFault::FaultVals ArmFaultVals::vals(
 // @todo: double check these values
 "Hypervisor Trap",   0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
-0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
-};

[gem5-dev] Change in public/gem5[master]: arch-arm: Change ArmFault cast from reinterpret to static

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/8241

to review the following change.


Change subject: arch-arm: Change ArmFault cast from reinterpret to static
..

arch-arm: Change ArmFault cast from reinterpret to static

Changing casting type in src/arch/arm/isa.cc

Change-Id: Ia19b30a1bf8b1b25df149b52613a3533eaced03a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa.cc
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 5d34e18..f667732 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1476,7 +1476,7 @@
   "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
   val, newVal);
   } else {
-  ArmFault *armFault = reinterpret_cast*>(fault.get());
+  ArmFault *armFault = static_cast*>(fault.get());

   // Set fault bit and FSR
   FSR fsr = armFault->getFsr(tc);

@@ -1725,7 +1725,7 @@
   "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
   val, newVal);
 } else {
-ArmFault *armFault = reinterpret_cast*>(fault.get());
+ArmFault *armFault = static_cast*>(fault.get());

 // Set fault bit and FSR
 FSR fsr = armFault->getFsr(tc);


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[gem5-dev] Change in public/gem5[master]: sim: Remove _numContexts member in System class

[Giacomo Travaglini (Gerrit)]

Hello Gabe Black, Jason Lowe-Power, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8062

to look at the new patch set (#2).

Change subject: sim: Remove _numContexts member in System class
..

sim: Remove _numContexts member in System class

A System object has a _numContexts member variable which represent the
number of ThreadContext registered in the System.  Since this has to
match the size of the ThreadContext vector, this patch removes the
manually cached size. This was usually used as a for-loop index, whereas
we want to enforce the use of range-based loops whenever possible.

Change-Id: I1ba317c0393bcc9c1aeebbb1fc22d7b2bc2cf90c
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/kvm/gic.cc
M src/arch/arm/linux/system.cc
M src/sim/system.cc
M src/sim/system.hh
4 files changed, 15 insertions(+), 20 deletions(-)


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Gerrit-Change-Id: I1ba317c0393bcc9c1aeebbb1fc22d7b2bc2cf90c
Gerrit-Change-Number: 8062
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
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Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Correct SecureMonitorTrap vals for aarch32

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8041 )


Change subject: arch-arm: Correct SecureMonitorTrap vals for aarch32
..

arch-arm: Correct SecureMonitorTrap vals for aarch32

This patch replaces the dummy values which were defined for the
SecureMonitorTrap thus enabling its usage in aarch32 mode.  1) It
changes the vector table offset from 0x14 to 0x4 in compliance with the
armv8 documentation.  2) When trapping in monitor mode for aarch32, the
mon_lr is updated with the pc + a non zero offset (+4/2 depending on the
current instruction set: +4 for A32, +2 for T32).

Change-Id: I01e1e52bf5ecd405e7472e31e01cf9a599153b08
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/8041
Maintainer: Andreas Sandberg 
---
M src/arch/arm/faults.cc
1 file changed, 4 insertions(+), 5 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index e3488f4..0f54906 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -237,6 +237,10 @@
 "Hypervisor Trap",   0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
 };
+template<> ArmFault::FaultVals ArmFaultVals::vals = {
+"Secure Monitor Trap",   0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON,
+4, 2, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
+};
 template<> ArmFault::FaultVals ArmFaultVals::vals = {
 "IRQ",   0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
 4, 4, 0, 0, false, true,  false, EC_UNKNOWN, FaultStat()
@@ -258,11 +262,6 @@
 "Supervisor Trap",   0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
 };
-template<> ArmFault::FaultVals ArmFaultVals::vals = {
-// Some dummy values (SecureMonitorTrap is AArch64-only)
-"Secure Monitor Trap",   0x014, 0x000, 0x200, 0x400, 0x600, MODE_MON,
-0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
-};
 template<> ArmFault::FaultVals ArmFaultVals::vals = {
 // Some dummy values (PCAlignmentFault is AArch64-only)
 "PC Alignment Fault",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I01e1e52bf5ecd405e7472e31e01cf9a599153b08
Gerrit-Change-Number: 8041
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in public/gem5[master]: sim: Remove _numContexts member in System class

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/8062

to review the following change.


Change subject: sim: Remove _numContexts member in System class
..

sim: Remove _numContexts member in System class

A System object has a _numContexts member variable which represent the
number of ThreadContext registered in the System.  Since this has to
match the size of the ThreadContext vector, this patch removes the
manually cached size. This was usually used as a for-loop index, whereas
we want to enforce the use of range-based loops whenever possible.

Change-Id: I1ba317c0393bcc9c1aeebbb1fc22d7b2bc2cf90c
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/kvm/gic.cc
M src/arch/arm/linux/system.cc
M src/sim/system.cc
M src/sim/system.hh
4 files changed, 13 insertions(+), 20 deletions(-)



diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index 887fa8d..d2423a6 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -305,7 +305,7 @@
 MuxingKvmGic::copyBankedDistRange(BaseGicRegisters* from,  
BaseGicRegisters* to,

   Addr daddr, size_t size)
 {
-for (int ctx = 0; ctx < system._numContexts; ++ctx)
+for (int ctx = 0; ctx < system.numContexts(); ++ctx)
 for (auto a = daddr; a < daddr + size; a += 4)
 copyDistRegister(from, to, ctx, a);
 }
@@ -314,7 +314,7 @@
 MuxingKvmGic::clearBankedDistRange(BaseGicRegisters* to,
Addr daddr, size_t size)
 {
-for (int ctx = 0; ctx < system._numContexts; ++ctx)
+for (int ctx = 0; ctx < system.numContexts(); ++ctx)
 for (auto a = daddr; a < daddr + size; a += 4)
 to->writeDistributor(ctx, a, 0x);
 }
@@ -345,7 +345,7 @@
 // Copy CPU Interface Control Register (CTLR),
 //  Interrupt Priority Mask Register (PMR), and
 //  Binary Point Register (BPR)
-for (int ctx = 0; ctx < system._numContexts; ++ctx) {
+for (int ctx = 0; ctx < system.numContexts(); ++ctx) {
 copyCpuRegister(from, to, ctx, GICC_CTLR);
 copyCpuRegister(from, to, ctx, GICC_PMR);
 copyCpuRegister(from, to, ctx, GICC_BPR);
@@ -423,7 +423,7 @@
 // have been shifted by three bits due to its having been emulated by
 // a VGIC with only 5 PMR bits in its VMCR register.  Presently the
 // Linux kernel does not repair this inaccuracy, so we correct it here.
-for (int cpu = 0; cpu < system._numContexts; ++cpu) {
+for (int cpu = 0; cpu < system.numContexts(); ++cpu) {
cpuPriority[cpu] <<= 3;
assert((cpuPriority[cpu] & ~0xff) == 0);
 }
diff --git a/src/arch/arm/linux/system.cc b/src/arch/arm/linux/system.cc
index 7f06475..094e4d7 100644
--- a/src/arch/arm/linux/system.cc
+++ b/src/arch/arm/linux/system.cc
@@ -250,8 +250,7 @@
 std::string task_filename = "tasks.txt";
 taskFile = simout.create(name() + "." + task_filename);

-for (int i = 0; i < _numContexts; i++) {
-ThreadContext *tc = threadContexts[i];
+for (const auto tc : threadContexts) {
 uint32_t pid = tc->getCpuPtr()->getPid();
 if (pid != BaseCPU::invldPid) {
 mapPid(tc, pid);
diff --git a/src/sim/system.cc b/src/sim/system.cc
index ed01e0e..4541d77 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -87,7 +87,6 @@

 System::System(Params *p)
 : MemObject(p), _systemPort("system_port", this),
-  _numContexts(0),
   multiThread(p->multi_thread),
   pagePtr(0),
   init_param(p->init_param),
@@ -256,7 +255,6 @@
  "Cannot have two CPUs with the same id (%d)\n", id);

 threadContexts[id] = tc;
-_numContexts++;

 #if THE_ISA != NULL_ISA
 int port = getRemoteGDBPort();
@@ -287,12 +285,13 @@
 int
 System::numRunningContexts()
 {
-int running = 0;
-for (int i = 0; i < _numContexts; ++i) {
-if (threadContexts[i]->status() != ThreadContext::Halted)
-++running;
-}
-return running;
+return std::count_if(
+threadContexts.cbegin(),
+threadContexts.cend(),
+[] (ThreadContext* tc) {
+return tc->status() != ThreadContext::Halted;
+}
+);
 }

 void
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 5b0c178..a72f2a7 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -196,7 +196,6 @@
 #endif

 std::vector threadContexts;
-int _numContexts;
 const bool multiThread;

 ThreadContext *getThreadContext(ContextID tid)
@@ -204,11 +203,7 @@
 return threadContexts[tid];
 }

-int numContexts()
-{
-assert(_numContexts == (int)threadContexts.size());
-return _numContexts;
-}
+unsigned numContexts() const { return threadContexts.size(); }

 /** 

[gem5-dev] Change in public/gem5[master]: arch-arm: Change function name for banked miscregs

[Giacomo Travaglini (Gerrit)]

Hello Nikos Nikoleris, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/7982

to look at the new patch set (#2).

Change subject: arch-arm: Change function name for banked miscregs
..

arch-arm: Change function name for banked miscregs

This commit changes the function's name used for retrieving the index of a
security banked register given the flatten index. This will avoid confusion
with flattenRegId, which has a different purpose.

Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
7 files changed, 31 insertions(+), 31 deletions(-)


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Gerrit-Change-Number: 7982
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[gem5-dev] Change in public/gem5[master]: arch-arm: Handle route to EL2 in Supervisor Trap

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/7961



Change subject: arch-arm: Handle route to EL2 in Supervisor Trap
..

arch-arm: Handle route to EL2 in Supervisor Trap

Supervisor Trap is supposed to be able to handle exceptions routed
to EL2, which is enabled by HCR_EL2.TGE. This fix adds routeToHyp()
function to Supervisor Trap to handle this, similar to that in
UndefinedFault, DataAbort, etc.

Change-Id: I1fcf9f2d445ecbc13c8f6d3b7d599728b0250ab7
Reviewed-by: Jack Travaglini 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 32 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index d143056..27894e0 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2014, 2016-2017 ARM Limited
+ * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -923,10 +923,37 @@
 return (from64 ? EC_SMC_64 : vals.ec);
 }

+bool
+SupervisorTrap::routeToHyp(ThreadContext *tc) const
+{
+bool toHyp = false;
+
+SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
+HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
+
+// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
+toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
+return toHyp;
+}
+
+uint32_t
+SupervisorTrap::iss() const
+{
+// If SupervisorTrap is routed to hypervisor, iss field is 0.
+if (hypRouted) {
+return 0;
+}
+return issRaw;
+}
+
 ExceptionClass
 SupervisorTrap::ec(ThreadContext *tc) const
 {
-return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
+if (hypRouted)
+return EC_UNKNOWN;
+else
+return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
 }

 ExceptionClass
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index fa6740a..bec2c0e 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2016-2017 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -335,6 +335,8 @@
 overrideEc(_overrideEc)
 {}

+bool routeToHyp(ThreadContext *tc) const override;
+uint32_t iss() const override;
 ExceptionClass ec(ThreadContext *tc) const override;
 };


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