The recent change which added a fatal for not having a default or
user set value for a parameter broke X86_FS. There wasn't any way to
really know that was going to happen since it wouldn't show up until run
time and X86_FS isn't generally in a known condition, so I'm not all
that upset
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed.
* build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic
passed.
* build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp
passed.
*
Sorry Gabe,
I ran all the other variants, I just don't have files, etc for x86.
Perhaps you should place some on zizzer. It is possible to turn your
changesets back into patches. The first thing I would do is clone the
repository though. That way you will have something to go back to if
Ali Saidi wrote:
Sorry Gabe,
I ran all the other variants, I just don't have files, etc for x86.
Perhaps you should place some on zizzer. It is possible to turn your
changesets back into patches. The first thing I would do is clone the
repository though. That way you will have
What's the syntax to set something to NULL by default? That's actually
what I want in this case, I think. I tried using None but apparently
that's not right.
There's actually a special parameter called NULL. :) Just use it.
Nate
___
m5-dev
I just noticed that while m5.debug is 54MB, but libm5_debug.a 197MB.
Do we know why it's so huge? That -can't- be good for performance.
Gabe
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
I just noticed that while m5.debug is 54MB, but libm5_debug.a 197MB.
Do we know why it's so huge? That -can't- be good for performance.
I'm pretty sure it's because there are multiple copies of many
functions in there. When C++ sees a template class member function,
it emits code for it in
I fixed the first problem which I would consider legitimate (specifying
NULL explicitly is better), but now I'm having the same problem with a
parameter I -have- provided a default value for. I'm assuming when I get
the message:
fatal: root.family without default or user set value
that it's
The problem here is that you're not providing a default, you're
providing a description. If there is only one parameter, it is the
description. If there are two, it is the default followed by the
description.
One of those, how did it ever work?
Nate
On Sun, Feb 1, 2009 at 2:58 PM, Gabe
My bad. Now that I'm running again I notice the warning URLs take up a
lot of screen real estate especially in x86 where there are
unimplemented instructions. The same URL comes up again and again
because but it provides no new information. How hard would it be to make
the URL part work like a
changeset da5f7e97958c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=da5f7e97958c
description:
X86: Set/correct some default values for x86 parameters.
diffstat:
2 files changed, 4 insertions(+), 4 deletions(-)
src/arch/x86/bios/ACPI.py|2 +-
changeset e0d0e58cfd8d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e0d0e58cfd8d
description:
X86: Initialize the value behind port 61 so unused bits are consistent.
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/dev/x86/speaker.hh |2 +-
diffs (12
changeset ac2c268bf4f1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ac2c268bf4f1
description:
X86: Rework interrupt pins to allow one to many connections.
diffstat:
16 files changed, 209 insertions(+), 70 deletions(-)
src/dev/x86/Cmos.py|4 +
changeset 5975aa055dc8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5975aa055dc8
description:
X86: Add some interrupt info to the intel MP tables.
diffstat:
1 file changed, 47 insertions(+), 2 deletions(-)
configs/common/FSConfig.py | 49
changeset 2fdbb27f8c70 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2fdbb27f8c70
description:
X86: Configure the IO APIC more.
diffstat:
1 file changed, 17 insertions(+)
src/dev/x86/pc.cc | 17 +
diffs (27 lines):
diff -r 5975aa055dc8 -r
changeset ee307cca6d31 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ee307cca6d31
description:
X86: Add a keyboard controller device.
diffstat:
5 files changed, 731 insertions(+)
src/dev/x86/I8042.py | 43 +++
src/dev/x86/SConscript |4
changeset 5a07c4e3249b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5a07c4e3249b
description:
X86: Plug in an IDE controller.
diffstat:
3 files changed, 19 insertions(+), 2 deletions(-)
configs/common/FSConfig.py |2 +-
src/dev/x86/Pc.py |2 +-
changeset b9e30a60dee4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b9e30a60dee4
description:
Devices: Add support for legacy fixed IO locations in BARs.
diffstat:
13 files changed, 139 insertions(+), 35 deletions(-)
src/dev/Pci.py |6 +++
changeset 4b6af0ca4565 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4b6af0ca4565
description:
X86: Make sure the predecoder is cleared out for interrupts.
diffstat:
1 file changed, 1 insertion(+)
src/cpu/simple/base.cc |1 +
diffs (11 lines):
diff -r
changeset 96b77f1f419a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=96b77f1f419a
description:
X86: Calculate flags based on the actual result.
diffstat:
1 file changed, 3 insertions(+)
src/arch/x86/insts/microregop.cc |3 +++
diffs (13 lines):
diff -r
changeset 831413564d0c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=831413564d0c
description:
X86: Compute PCI config addresses correctly.
diffstat:
1 file changed, 2 insertions(+), 1 deletion(-)
src/arch/x86/tlb.cc |3 ++-
diffs (13 lines):
diff -r
changeset 47ada83a8958 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=47ada83a8958
description:
X86: Add extended Intel MP entries correctly.
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/arch/x86/bios/IntelMP.py |2 +-
diffs (12 lines):
diff -r
changeset 4cc05b7f2a97 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4cc05b7f2a97
description:
X86: Fix some incorrect register widths.
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
src/arch/x86/isa/operands.isa |4 ++--
diffs (13 lines):
diff -r
changeset 6481e40d21eb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6481e40d21eb
description:
X86: Take out the IDE noprobe kernel arguments.
diffstat:
1 file changed, 1 insertion(+), 4 deletions(-)
configs/common/FSConfig.py |5 +
diffs (15 lines):
diff -r
changeset 08c65e29e57e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=08c65e29e57e
description:
X86: Hook in a hard drive image.
diffstat:
1 file changed, 8 insertions(+)
configs/common/FSConfig.py |8
diffs (25 lines):
diff -r 6481e40d21eb -r
changeset 1349786dd9a7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1349786dd9a7
description:
X86: Hook up the IDE controller interrupt line.
diffstat:
2 files changed, 3 insertions(+), 2 deletions(-)
src/dev/x86/SouthBridge.py |1 +
src/dev/x86/pc.cc |
changeset 66021eb985f5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=66021eb985f5
description:
X86: Fix the microcode for the LODS instruction.
diffstat:
1 file changed, 4 insertions(+), 4 deletions(-)
src/arch/x86/isa/insts/general_purpose/string/load_string.py |
changeset 02e0e93d1ba7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=02e0e93d1ba7
description:
X86: Find the natural lpj for this configuration.
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
configs/common/FSConfig.py |2 +-
diffs (12 lines):
diff -r
changeset 441f446c76f6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=441f446c76f6
description:
X86: Fix the time keeping of the Local APIC timer.
diffstat:
1 file changed, 19 insertions(+), 12 deletions(-)
src/arch/x86/interrupts.cc | 31
changeset 6496f11d80da in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6496f11d80da
description:
CPU: Don't always reset the micro pc on faults. Let the faults handle
it.
diffstat:
1 file changed, 2 deletions(-)
src/cpu/simple/base.cc |2 --
diffs (12 lines):
changeset 7bd73614dc1d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7bd73614dc1d
description:
X86: Keep track of the vector for all exceptions/faults.
diffstat:
1 file changed, 34 insertions(+), 33 deletions(-)
src/arch/x86/faults.hh | 67
changeset 1a40b07bbc30 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1a40b07bbc30
description:
X86: Touch up the interrupt entering microcode.
diffstat:
1 file changed, 29 insertions(+), 36 deletions(-)
src/arch/x86/isa/insts/romutil.py | 65
changeset f58bee925c28 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f58bee925c28
description:
X86: Fix the upper bound on some ranges that were setting up the micro
code assembler.
diffstat:
1 file changed, 3 insertions(+), 3 deletions(-)
changeset 606b9525071d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=606b9525071d
description:
X86: Make the chks microop check for the right int descriptor type.
diffstat:
2 files changed, 7 insertions(+), 10 deletions(-)
src/arch/x86/isa/insts/romutil.py | 11
changeset f770af5600c9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f770af5600c9
description:
X86: Make the long mode interrupt/exception microcode handle an error
code.
diffstat:
2 files changed, 49 insertions(+), 24 deletions(-)
src/arch/x86/faults.cc
changeset d4e54239ed37 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d4e54239ed37
description:
X86: Distinguish between hardware and software interrupts/exceptions
diffstat:
2 files changed, 5 insertions(+), 3 deletions(-)
src/arch/x86/isa/microasm.isa |2
changeset 54f64fb1bd62 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=54f64fb1bd62
description:
X86: All x86 fault classes now attempt to do something useful.
diffstat:
3 files changed, 69 insertions(+), 25 deletions(-)
src/arch/x86/faults.cc| 57
I've getting close to emptying my queue. I'm up to where I added a hack
for page faults. When we last left that discussion, we were talking
about how to connect the TLB so that it could delay responding and
whether it would be a good idea to use ports for something like that. If
it is ports,
hidden inside of or = hidden inside of the cpu or
Gabe Black wrote:
I've getting close to emptying my queue. I'm up to where I added a hack
for page faults. When we last left that discussion, we were talking
about how to connect the TLB so that it could delay responding and
whether it
-//panic(Need implementation\n);
+southBridge-ioApic-signalInterrupt(4);
+southBridge-pic1-signalInterrupt(4);
Can you put a #define somewhere with a comment instead of the magic constant?
___
m5-dev mailing list
m5-dev@m5sim.org
Can you put the images and kernels that you're working with somewhere
so people can play if they want?
Nate
On Sun, Feb 1, 2009 at 5:18 PM, Gabe Black gbl...@eecs.umich.edu wrote:
changeset 08c65e29e57e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=08c65e29e57e
I know that I wasn't good about this with Alpha, but a comment in the
code with a reference to documentation that explains the numbers
you've stuck in there would generally be very nice.
Nate
On Sun, Feb 1, 2009 at 5:18 PM, Gabe Black gbl...@eecs.umich.edu wrote:
changeset a2c317cefcf8 in
You're manually setting loops per jiffy?
On alpha at least, we have a hook for the function that calculates it
and programatically return the number based on the clock frequency
selected.
I guess I should respond via e-mail for the record.
See arch/alpha/linux/system.(cc|hh)
Sure. Does that work like warn once? It's in a position to be called a lot.
Gabe
nathan binkert wrote:
For the XXX this is a hack, can you please use the newish hack() function?
Thanks,
Nate
On Sun, Feb 1, 2009 at 5:18 PM, Gabe Black gbl...@eecs.umich.edu wrote:
changeset
nathan binkert wrote:
-//panic(Need implementation\n);
+southBridge-ioApic-signalInterrupt(4);
+southBridge-pic1-signalInterrupt(4);
Can you put a #define somewhere with a comment instead of the magic constant?
___
m5-dev mailing
Sure. Does that work like warn once? It's in a position to be called a lot.
There's hack() and hack_once(). Though, you bring up a good point as
to whether it is worth ever printing a hack message more than once.
Nate
___
m5-dev mailing list
Yes. They're both on zizzer. The kernel is in
/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 and the disk image is
in /dist/m5/system/disks/x86root.img. The head is up to the point where
you'll get the very first page fault for user code and it'll die.
Gabe
nathan binkert wrote:
Can you
Ok. Sometimes there isn't a very good single piece of documentation for
this stuff and I have to extrapolate from miscellaneous specs, random
websites and guesses. In the cases where there is an good source of
information I'll add a reference.
Gabe
nathan binkert wrote:
I know that I wasn't
48 matches
Mail list logo
