So, I think part of the confusion is that there are two names now,
debug flags and trace flags, but they're different views of the same
mechanism (yes? no?) It seems like the --trace* options are like the
--debug* options, except their intended use is a subset of --debug*,
specifically
ping
Quoting Gabe Black gbl...@eecs.umich.edu:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/719/
---
Review request for Default, Ali
ping
Quoting Gabe Black gbl...@eecs.umich.edu:
Ping...
On 05/05/11 10:38, Steve Reinhardt wrote:
On Wed, May 4, 2011 at 2:25 PM, Gabe Black gbl...@eecs.umich.edu wrote:
Did that make sense?
I see how that could work... I think I was more puzzled by how you would
figure out that
for
According to this:
http://m5sim.org/Special:AllPages
only one exists created by Ali last August. I'm all for getting rid of
those links and I think I've even suggested it a time or two in the
past.
Gabe
Quoting Steve Reinhardt ste...@gmail.com:
You know the For more information see:
X86 doesn't have an ASID hardware feature to the best of my knowledge,
except related to the virtualization extensions when working with
guest memory spaces. Would it make sense to use root page table
pointers for this? I don't know specifically how page tables are
managed in Linux, so I
Quoting Ali Saidi sa...@umich.edu:
On 2011-05-02 16:42:25, Gabe Black wrote:
util/statetrace/arch/arm/tracechild.cc, line 79
http://reviews.m5sim.org/r/669/diff/1/?file=12215#file12215line79
I don't know how easy this would be to accommodate, but
you're going to be sending a bunch
I deleted the build directory but I'll let it rerun naturally tonight.
If somebody wants to rerun them manually go ahead.
Gabe
Quoting Beckmann, Brad brad.beckm...@amd.com:
I can't reproduce these scons errors and they don't seem to happen
from a clean build. Can we blow away the current
That sounds reasonable. With too many reviews it gets harder to get to
all of them, and some obscure things may languish with no reviews
because only one person is comfortable with that code. Reviews are
generally a really good thing but they have some overhead. If we don't
get more
Quoting nathan binkert n...@binkert.org:
Anyway, it seems like it would be useful to be able to have multiple
binaries that can be built by scons, specifically the utility stuff and
unit tests. That way we could avoid having a hodge podge of small build
systems which are either isolated or not
Quoting nathan binkert n...@binkert.org:
A mechanism where I can say binary foo needs file bar, and then when I tell
it to build foo it build's it with bar, and bar doesn't get mixed in to
other things. I think you're new widget that was like mercurial patch guards
would help with that, right?
Quoting nathan binkert n...@binkert.org:
That doesn't really fit with how the ISA files work. They get broken into an
AST, but that gets consumed as it goes,
Does it have to be?
Making it not work that way would likely be very painful. The parser
part is finicky (like they all are in any
Combining FS and SE is a lot like the heterogeneous ISA stuff in that
it's something I'd really like to see happen but also where there are
definitely some steps in the middle. The detail work of combining FS
and SE will be easier, I think, but it will take more conceptual
Quoting Steve Reinhardt ste...@gmail.com:
On Tue, Apr 19, 2011 at 3:13 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Caching the list of generated SLICC files sounds like a good idea to
me. I'm not sure this would require recursive scons invocations,
since we manage to build
My first reaction is let's fix it, but I don't really understand the
problem or the impact of changing things. Anything serious?
Gabe
Quoting nathan binkert n...@binkert.org:
I'm trying to get my python stats stuff committed and I found a bug in
the classic cache stats. Look in
I don't see how it avoids depending on transitive includes...
Quoting nathan binkert n...@binkert.org:
I noticed a clever way to fix this in the google style guide that we
could adopt if we choose.
http://google-styleguide.googlecode.com/svn/trunk/cppguide.xml#Names_and_Order_of_Includes
Ah, ok, that makes more sense. I didn't expand the little blurb so it
looked like foo.cc's foo.hh would be last and not first. But in the
example code it's first which would make that work.
Gabe
Quoting nathan binkert n...@binkert.org:
I don't see how it avoids depending on transitive
Quoting Nilay Vaish ni...@cs.wisc.edu:
On Thu, 7 Apr 2011, Gabriel Michael Black wrote:
When you say this is portable, what do you mean? Portable between
compilers? We usually use gcc, but we have at least partial support
for other compilers. I think this is necessary on some platforms
When you say this is portable, what do you mean? Portable between
compilers? We usually use gcc, but we have at least partial support
for other compilers. I think this is necessary on some platforms.
Gabe
I would still root for using popcount() builtin available with GCC.
--
Nilay
It might be ok, but I've been busy and forgot to look at it. Please
give me a few more days.
Gabe
Quoting Lisa Hsu h...@eecs.umich.edu:
---
This is an automatically generated e-mail. To reply, visit:
The two issues below are copied from ARM_FS, but other targets had the
same problems.
These errors are making the build fail.
build/ARM_FS/cpu/testers/networktest/networktest.cc: In member
function 'void NetworkTest::completeRequest(Packet*)':
This looks like the compiler being a little over ambitious looking for
problems. Can we just turn off that warning?
Gabe
Quoting Korey Sewell ksew...@umich.edu:
Sorry, I didnt give the full details here. I'm using gcc4.4.1. And when I
compile for m5.opt/debug then I get the following
I just saw Ali's email (casting to UTick). I like that idea better
than mine. I had just assumed Tick already was unsigned, but
apparently that's not true.
Gabe
Quoting Gabriel Michael Black gbl...@eecs.umich.edu:
This looks like the compiler being a little over ambitious looking
Hey folks. My computer decided to eat itself yesterday and my file
system ended up mangled. I think the important stuff in my home
directory survived, but I'm in a Starbucks right now trying to get it
straightened out. Please give me a few days extra slack responding
since I don't know
They did mention the line that needed to be changed, so that's covered.
But I think we'll still need that other information (how to reproduce
it, basically) so we can verify the fix ourselves. In any case, thanks
for letting us know!
Gabe
Quoting Korey Sewell ksew...@umich.edu:
Many
Quoting Ali Saidi sa...@umich.edu:
On 2011-02-24 14:56:09, Gabe Black wrote:
This is actually better than my initial impression suggested. I
think I saw all the lines from the Ra-URa change and got confused
since those didn't have anything to do with RFE. I jumped to the
conclusion
I don't want to beat the issue to death (too late?), but I think
you'll agree that as implemented this is a hack. A sometimes useful
hack that hasn't caused any serious problems so far, but still a hack.
I'd like us to get rid of hacks by getting rid of the code or turning
them into
simulation scripts? That disambiguates the term and
hopefully makes it more obvious what, say, se.py is for and how to set
up a simulation. I think it's something people usually figure out
relatively quickly, but it wouldn't hurt to make it a little more
obvious.
Gabe
Quoting Gabriel Michael
Quoting Ali Saidi sa...@umich.edu:
Regarding /dist:
I think the directories of interest were binaries, disks, cpu2000.
What more of a rundown do you want?
That's not what I meant. I meant why is /dist in /dist at all? Where
did /dist come from? I've never seen it anywhere else.
Quoting Ali Saidi sa...@umich.edu:
On Feb 22, 2011, at 5:25 PM, Gabe Black wrote:
Like I said, why can't you just do that with a simple bash alias that
appends the options to the binary? Or a wrapper script? Why make a new
tool when an existing one works just as well?
I don't think any of
Independent of how the specifics end up hashed out, I think it's safe
to say it would be a good idea to set M5_PATH explicitly for the
regressions instead of relying on the default built into M5 being
tuned for that environment. I'd like to attempt to do that now. Does
anyone object? Could
Three places does seem like a lot. What are they specifically?
Hopefully we can get rid of one or two.
That said, using python to generate python to put in a hidden
directory to read with python embedded in a binary is, in my opinion,
WAY more complicated than the problem warrants. The
Quoting Ali Saidi sa...@umich.edu:
Let me ponder the other stuff in this for a day or two...
Ali
Speaking of the other stuff, could anyone give a quick rundown of /dist?
Gabe
___
m5-dev mailing list
m5-dev@m5sim.org
I was actually thinking about this the other day so I'll chime in. I
think the reason SLICC is being run is that you need to see what files
it's going to produce to set up dependencies, basically like you might
have to do if the ISA parser split up its output files. It might be
possible to
Could you please use review board? I wouldn't know what I'm looking
at, but other people might want a chance to look it over.
Gabe
Quoting Nilay Vaish ni...@cs.wisc.edu:
Can you email your patch, I'll take a look and commit the changes to
the repository.
Thanks!
Nilay
On Wed, 16 Feb
Hello again. I've had a chance to talk with an expert, and I have an
idea of how to approach this. It's going to require more flexibility
than the ISA parser has currently, though, specifically in how the
list of source and destination registers are managed. It would also be
nice to have a
Quoting Steve Reinhardt ste...@gmail.com:
Gabe, how many bytes at a time does the x86 predecoder fetch? If it
doesn't currently grab a cache line at a time, could it be made to do so,
and do you know if that would cause any issues with SMC?
All of the predecoders expect to receive one
I think there are two important aspects of this issue.
1. Using regression tests we can't distribute freely has some
important limitations. It would be nice to replace them with ones we
can.
2. The majority of the regression tests we have now are really
benchmarks which provide basic
I looked at Alpha's ISA description briefly, and I didn't see anywhere
an instruction did anything with the fault returned by a read/write in
initateAcc other than return it. Do have an example where that isn't
true? The only place I can think of where that would be useful is
prefetches,
No problem, I'd been meaning to do it for a while anyway.
As far as librt, I agree it has its drawbacks and I have no problem
with alternatives. An alternative for clock_nanosleep is nanosleep,
the big difference I think being that you can't tell it to wait until
an absolute time, and you
Ok, yeah, looking at it again I think you probably have something. I
keep mixing up the port and the containing device in my head when I
think about this. A revised version of my suggestion would be to move
the latency into IntDev and use it there. Sorry if I propagated any of
my own
Please update existing review requests instead of creating new ones.
Gabe
Quoting Brad Beckmann brad.beckm...@amd.com:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/418/
I'll have to look at this again and see if I can figure out what's
going on. For now I wanted to mention that Valgrind isn't necessarily
going to be useful in determining if there's a memory leak here
because these messages are sent infrequently and only leak a little
bit each time. In the
In reference to this and the next email, I don't think these should be
conditioned on the ARM ISA because it looks like those values are
valid and need to be serialized for all ISAs. It's just that the other
ISAs happen to have checkpoints that are old enough that they break,
and that's
[mailto:m5-dev-boun...@m5sim.org] On
Behalf Of Gabriel Michael Black
Sent: Thursday, December 09, 2010 9:04 PM
To: m5-dev@m5sim.org
Subject: Re: [m5-dev] changeset in m5: ARM: Add checkpointing support
In reference to this and the next email, I don't think these should be
conditioned on the ARM ISA
Quoting nathan binkert n...@binkert.org:
I put together a wiki page here:
http://m5sim.org/wiki/index.php/Python_Parameter_Types
that attempts to document the parameter types that are available and
how they work. If the experts (that's probably you, Steve and Nate)
could look it over and make
Quoting Ali Saidi sa...@umich.edu:
On Nov 15, 2010, at 8:29 PM, Gabriel Michael Black wrote:
It seems like our notion of serializing came from the definition
Alpha uses, and sometimes we need a stronger one. X86 is going to
have similar issues in some cases, although I couldn't necessarily
I put together a wiki page here:
http://m5sim.org/wiki/index.php/Python_Parameter_Types
that attempts to document the parameter types that are available and
how they work. If the experts (that's probably you, Steve and Nate)
could look it over and make sure I didn't misinterpret/mangle
I'd guess it's trying to be smart and make sure the single string
argument ends up being a single entry in argv. I'd also guess that's
why g++ is upset.
Gabe
Quoting Ali Saidi sa...@umich.edu:
g++ -o build/ARM_FS/arch/arm/predecoder.do -c -Wno-deprecated -pipe
-fno-strict-aliasing
Sorry about that. Do you need to fix it, or me? It may be simpler if you do.
That also brings up the question of testing with ARM. Internal to ARM
testing is fairly sophisticated and gets at most of what's implemented
instruction wise. External to ARM testing is much less so, so it's
hard
Quoting nathan binkert n...@binkert.org:
Feel free to propose some more verbose names, but the whole idea is
to remove the verbosity. Almost everything but [CC] and [SW] else
gets executed once per build. If there is an error it's going to be
pretty obvious where it came from, especially
I've done this before, just a sec...
(some googling)
I think you have to use an Action object instead of a raw command in
the Command builder. When building the Action object, the second
parameter is the alternative text to output.
It might look like the following:
env.Command(target,
Oh wait, that's not an environment variable, that's a scons variable
from the command line. My opinion still stands since it'd be sticky
and it's not as nice as a -- option, but it's better than an
environment variable.
Gabe
Quoting Gabriel Michael Black gbl...@eecs.umich.edu:
I've done
Is there a way to define custom parameter types, particularly from an
EXTRAS directory? I want to define an IPAddress type (or similar)
which takes input in the form a.b.c.d/n (netmask) or a.b.c.d
(plain IP) or a.b.c.d:p (with port) or something along those lines.
I see we have an
The best place to look is in the .py files in the src directory. These
are where the parameters are set up, and there isn't really any other
documentation. You shouldn't change the values in those files since
those just set the defaults, but that will let you know what
parameters there are
A little research shows that as of scons 0.98 the variant_dir variable
is available, older than 0.98.1 which we require. It looks like as of
2.0.1 they started complaining if you use build_dir. I'll put together
a patch to move us over in the next day or two. I expect it to be very
simple,
Quoting Steve Reinhardt ste...@gmail.com:
I don't see any responses from you on reviewboard, Gabe; clicking on
View Reviews does show a review from you at October 24th, 2010,
12:30 a.m., but it's empty as far as I can tell.
Anyway, as I think I mentioned earlier, I'm thinking that email works
Quoting Steve Reinhardt ste...@gmail.com:
On Sun, Oct 24, 2010 at 10:05 PM, Gabe Black gbl...@eecs.umich.edu wrote:
On 2010-10-22 10:30:06, Steve Reinhardt wrote:
src/arch/alpha/ev5.cc, line 63
http://reviews.m5sim.org/r/255/diff/11/?file=4275#file4275line63
Why not just redefine
OK, that seems like a good explanation, but (1) as Ali said, it really
needs to go in a doxygen comment where these accessors are defined in
the base PCState class and (2) I seem to recall some specific comments
where substitutions were made that didn't necessarily make sense wrt
this comment,
Quoting Steve Reinhardt ste...@gmail.com:
On Fri, Oct 22, 2010 at 10:57 AM, Gabe Black gbl...@eecs.umich.edu wrote:
Is this just to get STUPD to be a single uop instead of two
uops that communicate via a temp reg, without forcing dependent
instructions to wait for the STUPD to commit to get
One exception to that are the PCState structs I'm in the process of
adding. These each overload to print themselves as
(X1=X2=X3).(Y1=Y2) where the X*s are as many architecture level PCs
as are needed and the Y*s are microPCs. This is in the middle where
it's too complex for a single
I put this together a while ago but forgot to actually publish it. I
saw it again when I was clearing out submitted reviews.
Gabe
Quoting Gabe Black gbl...@eecs.umich.edu:
---
This is an automatically generated e-mail. To reply,
Yeah, I'd noticed that too but I wasn't sure what to do about it. I'll
take care of mine tonight.
Gabe
Quoting Steve Reinhardt ste...@gmail.com:
Hi folks,
Just a reminder that once you've committed a patch to the repo, you
should go back to reviewboard and mark the corresponding review
Quoting Gabe Black gbl...@eecs.umich.edu:
Gabe Black wrote:
This has come up in ARM and also in X86 with its STUPD (store with
update) microop. The problem has been updating the base register when,
one, the instruction may fault after initiateAcc and the initial value
is lost, and two,
Quoting Steve Reinhardt ste...@gmail.com:
On Sat, Sep 25, 2010 at 5:03 AM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
[...]
1 2 sound good to me.
3. For selectively trapped instructions, StaticInst properties might now
vary based on runtime information which doesn't really work
Quoting Steve Reinhardt ste...@gmail.com:
On Fri, Oct 1, 2010 at 5:44 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
3. For selectively trapped instructions, StaticInst properties might now
vary based on runtime information which doesn't really work.
I can see how
What I'm saying is that that won't work since the faked case is
-more- restrictive than the not faked case. You can't speculatively
execute a write syscall on behalf of the simulated code, but you can
speculatively execute a software interrupt instruction. Also, if you
need the syscall
, Sep 27, 2010 at 9:03 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
The function in question is here:
http://lxr.linux.no/linux+*/arch/x86/kernel/apic.c#L576
It looks complicated enough and does enough work that, to me, it doesn't
look feasible to fake, but you have more experience
Darn it, this is still not right. I must have forgotten to refresh the
patch. Before I create yet another review request, does anyone know
how to update the one I already have? I tried using the -u option to
postreview, but maybe I didn't do it right.
I think if you try to compile ARM with
Quoting nathan binkert n...@binkert.org:
So in debugging some python stuff, I was thinking to myself about how
it would be nice if we had DPRINTF support in python, so it got me
thinking about how I might implement that. It turns out that it isn't
that hard since I've already exposed the flags
Hi everybody. I'm reworking a lot of PC related stuff across CPUs and
ISAs (more to come soon) and I'm running into an assertion in the
branch predictor when running MIPS in O3. The assert is during a
squash when the branch that was mispredicted isn't the oldest pending
branch.
I don't
Quoting Korey Sewell ksew...@umich.edu:
comments below
On Sun, Aug 22, 2010 at 3:46 PM, Gabe Black gbl...@eecs.umich.edu wrote:
The CPSR might be that high because it's after the banks of registers
for all the modes. Korey, are you asking about register flattening in
general, or how the
the class from the the isa description, I
think
the change is correct. An alternate approach would be to have the
method
in
threadstate do nothing because it's unimportant for it.
Ali
On Tue, 17 Aug 2010 19:04:10 -0400, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Sorry if I
Or even something that builds a histogram of instructions/instruction
types executed.
Gabe
Quoting Gabriel Michael Black gbl...@eecs.umich.edu:
I'd like the CPUs to remain as dumb as possible as far as ISA
semantics and mechanisms so neither they nor the ISAs are
unnecessarily
of state is available
that would be impossible to do.
The point should be to create interfaces that encapsulate features, and
not architectures. Predication is a feature of an architecture. Itanium
predicates lots of instructions too...
Ali
On Fri, 20 Aug 2010 15:18:45 -0400, Gabriel Michael Black
Quoting Ali Saidi sa...@umich.edu:
We're not forcing all cpu models to support predication, only have to a
function allows the cpu to understand if an instruction didn't execute
because it was predicated. If the CPU chooses to do nothing with that, as
the simple cpus do, then so be it.
It's
approach would be to have the method in
threadstate do nothing because it's unimportant for it.
Ali
On Tue, 17 Aug 2010 19:04:10 -0400, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Sorry if I wasn't clear before (I reread my post and it sounded a
little vague) but what the simple CPU does
Quoting Ali Saidi sa...@umich.edu:
On Tue, 17 Aug 2010 14:19:49 -0400, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Quoting Steve Reinhardt ste...@gmail.com:
On Sun, Aug 15, 2010 at 6:07 PM, Min Kyu Jeong mkje...@gmail.com
wrote:
I needed to spit out a code that reads from
Quoting Steve Reinhardt ste...@gmail.com:
I don't think I changed anything here... hg annotate seems to back me
up on that, too. I think the fundamental (but subtle) issue here is
that once you successfully send a packet, the ownership for that
packet object is conceptually handed off to the
that looks like it would lend itself better to nesting
walks too then that would be a preferable direction to go.
Steve
On Wed, Aug 18, 2010 at 8:14 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Off hand I would say yes, queuing up a second request behind one that caused
a table walk makes
Off hand I would say yes, queuing up a second request behind one that
caused a table walk makes sense. Since there should only be one other
request, just having a variable for the on deck request should be
sufficient instead of a full blown queue. Please let me know if you
think otherwise.
Quoting Steve Reinhardt ste...@gmail.com:
On Sun, Aug 15, 2010 at 6:07 PM, Min Kyu Jeong mkje...@gmail.com wrote:
I needed to spit out a code that reads from a register, and writes to it
again. The thing is arch reg indices are renamed (reg renaming and shadow
reg file), so many structures
That seems reasonable, but I still don't think being deterministic is
a good distinguishing characteristic. M5 is designed to always be
deterministic and the regressions assume the same test will always get
the same answer, so -all- tests are deterministic, even if they're
determinstically
It's fine with me, but we'd need to be really careful the semantics
(64 bit vs. 32 bit operands, flags, etc.) are translated correctly. If
a syscall isn't there at all it's obvious why it's not going to work,
but if it is there and slightly wrong it'd be a lot harder to figure
out what's
According to the linux kernel sources:
#define _STRUCT_TIMESPEC
struct timespec {
time_t tv_sec; /* seconds */
longtv_nsec;/* nanoseconds */
};
#endif
It basically depends on sizeof(long) for each ISA. If all ISAs
supported are 64bit it can be moved to
,
Joel
On Fri, Jul 23, 2010 at 3:45 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Quoting Ali Saidi sa...@umich.edu:
On Fri, 23 Jul 2010 16:59:08 -0400, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Hmm, maybe we should be building these regularly too... What do you
think, Ali
I don't think we/I found a good solution. I had (and may still have)
copied and pasted versions of things with a 32 appended for SPARC, and
x86 just doesn't have any 32 bit tests. The 32 bit SPARC tests may
have just been in my own tree and never committed.
Gabe
Quoting Ali Saidi
Quoting Joel Hestness hestn...@cs.utexas.edu:
Hey Gabe,
Comments are in-lined below. If you'd like me to resubmit another review
of all or part, just let me know.
Thanks,
Joel
util/m5/Makefile.x86
http://reviews.m5sim.org/r/64/#comment248
Why is this necessary? Is this so it runs
Quoting Ali Saidi sa...@umich.edu:
On Fri, 23 Jul 2010 16:59:08 -0400, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Hmm, maybe we should be building these regularly too... What do you
think, Ali? Would it be possible to return reserved1_func and use a
different code?
It was reserved
Yes it does, and that sounds reasonable to me. I'd still like to see
us use ISA hooks as minimally as possible, but this seems ok.
Gabe
Quoting Timothy M Jones tjon...@inf.ed.ac.uk:
Oh, ok, I see where you're going with that. However, the main idea
of having TheISA::HasUnalignedMemAcc was
executed on those ISAs. Maybe for a little one-liner like this it's
not a big deal either way, but for bigger hunks of code I think that
clarification is potentially useful.
Steve
On Thu, Jul 22, 2010 at 1:10 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Yes it does, and that sounds
place, in
which case great, we're on the same page. I'd been debating whether to
send out my little list anyway since I think it's productive to spend
a few cycles thinking about this stuff.
Gabe
Quoting Gabriel Michael Black gbl...@eecs.umich.edu:
To me there's actually a spectrum of ISA
You're probably right as far your diagnosis and fix for the problem,
but please give me a chance to verify before you check in.
The M, R and P suffixes are for the different operand types, and as
I'm sure you guessed, M means memory and R means register. P means RIP
relative memory
I'm not running on a lot of sleep, so sorry in advance if this email
is less coherent than normal.
I was actually thinking about this the other day I think because of
the SMARTS config changes. My suggestion would be to build up
composite primitives that can be wrapped up in thin,
It would be better to send this to m5-users where you'll reach more
people. I expect basically everyone on this list is on that list as
well.
Gabe
Quoting Krishna, Tushar tushar.kris...@amd.com:
Hi,
I am trying to run the tests in the m5threads package through M5's X86_SE.
[I was
Awesome :-).
Gabe
Quoting Ali Saidi sa...@umich.edu:
The uart is still a bit flaky and there is tons more todo, however:
m5 slave terminal: Terminal 0
[0.00] Linux version 2.6.28-arm2-eb-a9-arm-nano-tiny-up-wa-4.3.3
(alisa...@aus-bc5-b7) (gcc version 4.3.3 (Sourcery G++
it tomorrow and let you know.
On Mon, Jul 12, 2010 at 6:51 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Did that patch fix it?
Gabe
Quoting Gabe Black gbl...@eecs.umich.edu:
Here's more or less what's going on as far as the register index. The
load microop needs to store
I think you've mostly interpretted this correctly. The instructions
aren't retried if the translation fails, they just hang around and
wait for it. The check if fault == NoFault will work if the
translation is finished by the time initiateTranslation is done.
That's true for everything we
Quoting Ali Saidi sa...@umich.edu:
On Tue, 13 Jul 2010 11:20:26 -0700, Gabe Black gbl...@eecs.umich.edu
wrote:
This also brings up another idea I've been rolling around for a while.
Why is all the control state local to the miscregfile/it's decendant the
ISA object? Why don't we put control
Quoting Steve Reinhardt ste...@gmail.com:
On Tue, Jul 13, 2010 at 11:20 AM, Gabe Black gbl...@eecs.umich.edu wrote:
I can't say it was -the- reason, but one reason is that the TLBs as is
don't actually send the packets for the CPU, so they can't split
anything into multiple transactions
:23 PM, Gabriel Michael Black
gbl...@eecs.umich.edu mailto:gbl...@eecs.umich.edu wrote:
Thanks for the extra info which should be very helpful. Can you
please tell us what the actual bytes are for the junk instruction?
Gabe
Quoting Min Kyu Jeong mkje...@gmail.com mailto:mkje
1 - 100 of 219 matches
Mail list logo
