Re: [m5-dev] Review Request: Time: Add a mechanism to prevent M5 from running faster than real time.

nathan binkert wrote: > > If you add a function for it I'll use it. We should be careful, though, > since when nanoseconds (or microseconds or milliseconds) spill into seconds > might get a little tricky. Actually, right now nanoseconds, microseconds, and > milliseconds all change the same d

Re: [m5-dev] Review Request: Time: Add a mechanism to prevent M5 from running faster than real time.

> > If you add a function for it I'll use it. We should be careful, though, since > when nanoseconds (or microseconds or milliseconds) spill into seconds might > get a little tricky. Actually, right now nanoseconds, microseconds, and > milliseconds all change the same data, but seconds are separ

Re: [m5-dev] Review Request: Time: Add a mechanism to prevent M5 from running faster than real time.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/419/ --- (Updated 2011-01-18 23:21:55.573947) Review request for Default, Ali Saidi, Gabe Bl

Re: [m5-dev] Review Request: Time: Add a mechanism to prevent M5 from running faster than real time.

> On 2011-01-18 17:57:05, Steve Reinhardt wrote: > > src/sim/root.hh, line 85 > > > > > > Now that these methods are part of Root, I think they need a little > > more context in their names, e.g.: > > timeSyncEnabled() > >

Re: [m5-dev] Review Request: Time: Add a mechanism to prevent M5 from running faster than real time.

> On 2011-01-18 17:07:45, Nathan Binkert wrote: > > src/sim/root.hh, line 117 > > > > > > No big deal, but we usually have a comment here Done > On 2011-01-18 17:07:45, Nathan Binkert wrote: > > src/sim/root.cc, line 87 > >

Re: [m5-dev] (no subject)

I agree, but at times I find it difficult to come up with some apt subject. -- Nilay On Wed, 19 Jan 2011, Korey Sewell wrote: Hello, I don't mean to disrupt this conversation but for archiving purposes can we put a relevant title in the subject of the m5-dev emails? Myself and another stude

Re: [m5-dev] (no subject)

Hello, I don't mean to disrupt this conversation but for archiving purposes can we put a relevant title in the subject of the m5-dev emails? Myself and another student at UM are trying to spin up on the Ruby/M5 stuff but it makes it harder when an email doesn't have a subject. Again, dont mean t

Re: [m5-dev] (no subject)

I think there are different topology file for different layouts and thus allowing different number of controllers. For example, topology named "MeshDirCorners" would allow a configuration with "--num-cpus 16 --num-l2caches 16 --num-dirs 4 ". This essentially places the MCs (a.k.a dirs) at the c

Re: [m5-dev] (no subject)

I noticed that CPUs other than CPU 0 are started some time later in the simulation. Why is it so? -- Nilay On Tue, 18 Jan 2011, Nilay wrote: Brad, I got the simulation working. It seems to me that you wrote Mesh.py under the assumption that number of cpus = number of L1 controllers = number

Re: [m5-dev] (no subject)

Brad, I got the simulation working. It seems to me that you wrote Mesh.py under the assumption that number of cpus = number of L1 controllers = number of L2 controllers (if present) = number of directory controllers. The following options worked after some struggle and some help from Arka - ./bu

Re: [m5-dev] Question on SLICC

Brad, What was the purpose of libruby? Don't want to sound critical, but when I went through that code, I had the feeling it could have been done in a better fashion. I had similar thoughts about ruby/common/Address.hh, in particular about the fact that it makes calls to RubySystem. Those function

Re: [m5-dev] Question on SLICC

Nilay, Are you trying to replace CacheMsg with RubyRequest? I agree that we can probably get rid of one of them. If I recall, right now RubyRequest is defined in libruby.hh. Is the Ruby library interface still important to you all at Wisconsin? If not, I would like to get rid of the libruby

Re: [m5-dev] Review Request: Time: Add a mechanism to prevent M5 from running faster than real time.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/419/#review776 --- src/sim/root.hh Now th

Re: [m5-dev] Review Request: Time: Add a mechanism to prevent M5 from running faster than real time.

> On 2011-01-18 07:03:49, Ali Saidi wrote: > > src/sim/root.hh, line 93 > > > > > > This seems large enough that it should just go in the cc file Done > On 2011-01-18 07:03:49, Ali Saidi wrote: > > src/sim/root.cc, line 52 >

Re: [m5-dev] Review Request: Time: Add a mechanism to prevent M5 from running faster than real time.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/419/#review774 --- Ship it! Looks good to me. src/sim/root.hh

Re: [m5-dev] Review Request: Time: Add a mechanism to prevent M5 from running faster than real time.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/419/ --- (Updated 2011-01-18 16:49:14.839440) Review request for Default, Ali Saidi, Gabe Bl

Re: [m5-dev] Compile Error with gcc-4.5.2 with m5-unstable

This is fixed in the dev repository. The fix was to cast the value being switched on to an int. The compiler then no longer expects all the case values to be members of the same enum. Gabe Richard Strong wrote: > Hi all, > > I checked out the unstable M5 last Thursday and saw a gcc-4.5.2 > warnin

[m5-dev] Compile Error with gcc-4.5.2 with m5-unstable

Hi all, I checked out the unstable M5 last Thursday and saw a gcc-4.5.2 warning that is being treated as an error: scons: Building targets ... [ CXX] ALPHA_SE/cpu/inorder/resource_pool.cc -> .do cc1plus: warnings being treated as errors /home/rstrong/build/m5-idle/build/ALPHA_SE/cpu/inorder/

Re: [m5-dev] changeset in m5: O3: Fix some variable length instruction issues...

I'm pretty sure I mentioned twice that this is likely not the right way to do this. The ARM predecoder should consume the bytes it has, not ensure through special behavior in fetch that what it needs will always be there. I haven't tried it yet, but I remember having concerns that this would break

Re: [m5-dev] Review Request: VNC: Add vnc server to M5 and support to use it for ARM.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/432/ --- (Updated 2011-01-18 14:49:34.075341) Review request for Default, Ali Saidi, Gabe Bl

[m5-dev] Review Request: imported patch ext/vnc.patch

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/432/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

[m5-dev] Review Request: SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk occurs.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/431/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

[m5-dev] changeset in m5: ARM/O3: Add regressions for ARM w/ O3 CPU.

changeset 32b6354d2ae6 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=32b6354d2ae6 description: ARM/O3: Add regressions for ARM w/ O3 CPU. diffstat: tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini | 517 tests/long/00.gzip/ref/arm/linux/o3-timing/si

[m5-dev] changeset in m5: Stats: Update stats for previous set of patches.

changeset 535cc70e8663 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=535cc70e8663 description: Stats: Update stats for previous set of patches. diffstat: tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout | 6 +- tests/long/00.gzip/ref/a

[m5-dev] changeset in m5: O3: Fix itstate prediction and recovery.

changeset ee6641d7c713 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=ee6641d7c713 description: O3: Fix itstate prediction and recovery. Any change of control flow now resets the itstate to 0 mask and 0 condition, except where the control flow alteratio

[m5-dev] changeset in m5: O3: Keep around the last committed instruction ...

changeset c0be563517da in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=c0be563517da description: O3: Keep around the last committed instruction and use for squashing. Without this change 0 is always used for the youngest sequence number if a squash occure

[m5-dev] changeset in m5: O3: Fix some variable length instruction issues...

changeset b2c7e56572a4 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=b2c7e56572a4 description: O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA. diffstat: src/arch/arm/predecoder.cc | 15 +++ src/arch/arm/predecoder.hh | 22 +

[m5-dev] changeset in m5: O3: Don't test misprediction on load instructio...

changeset d25827665112 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=d25827665112 description: O3: Don't test misprediction on load instructions until executed. diffstat: src/cpu/o3/iew_impl.hh | 6 +- 1 files changed, 5 insertions(+), 1 deletions(-) diffs (16

[m5-dev] changeset in m5: O3: Don't try to scoreboard misc registers.

changeset 3c6783497976 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=3c6783497976 description: O3: Don't try to scoreboard misc registers. I'm not positive this is the correct fix, but it's working right now. Either we need to do something like this, pr

[m5-dev] changeset in m5: ARM: The ARM decoder should not panic when deco...

changeset 69aae4379062 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=69aae4379062 description: ARM: The ARM decoder should not panic when decoding undefined holes is arch. This can abort simulations when the fetch unit runs ahead and speculatively dec

[m5-dev] changeset in m5: O3: Fix corner cases where multiple squashes/fe...

changeset 07ba4754ae0a in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=07ba4754ae0a description: O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf. diffstat: src/cpu/o3/iew_impl.hh | 69 ++-- s

[m5-dev] changeset in m5: ARM: Add code for a simple bootloader for MP boot.

changeset fb777f10f3df in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=fb777f10f3df description: ARM: Add code for a simple bootloader for MP boot. diffstat: system/arm/simple_bootloader/Makefile | 60 + system/arm/simple_bootloader/simple.

[m5-dev] changeset in m5: O3: Fix mispredicts from non control instructions.

changeset bb38f0c47ade in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=bb38f0c47ade description: O3: Fix mispredicts from non control instructions. The squash inside the fetch unit should not attempt to remove them from the branch predictor as non-control

[m5-dev] changeset in m5: O3: Fixes the way prefetches are handled inside...

changeset 02450f4443ce in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=02450f4443ce description: O3: Fixes the way prefetches are handled inside the iew unit. This patch prevents the prefetch being added to the instCommit queue twice. diffstat: src/arch/arm/f

[m5-dev] changeset in m5: O3: Support timing translations for O3 CPU fetch.

changeset 2290428b5f04 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=2290428b5f04 description: O3: Support timing translations for O3 CPU fetch. diffstat: src/cpu/o3/fetch.hh | 38 - src/cpu/o3/fetch_impl.hh | 371 ++---

[m5-dev] changeset in m5: ARM: Add support for moving predicated false de...

changeset cc5e64f8423f in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=cc5e64f8423f description: ARM: Add support for moving predicated false dest operands from sources. diffstat: src/arch/arm/isa/insts/misc.isa | 3 +- src/arch/arm/isa/templates/basic.isa

[m5-dev] changeset in m5: O3: Fixes fetch deadlock when the interrupt cle...

changeset 0c6613ad8f18 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=0c6613ad8f18 description: O3: Fixes fetch deadlock when the interrupt clears before CPU handles it. When this condition occurs the cpu should restart the fetch stage to fetch from th

[m5-dev] changeset in m5: ARM: fix mismatched new/delete.

changeset 714be811f978 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=714be811f978 description: ARM: fix mismatched new/delete. diffstat: src/arch/arm/insts/mem.hh | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diffs (12 lines): diff -r 7902269340f8 -r 71

[m5-dev] changeset in m5: mkblankimage: bash != sh on many systems and th...

changeset 7902269340f8 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=7902269340f8 description: mkblankimage: bash != sh on many systems and this script needs bash diffstat: util/mkblankimage.sh | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diffs (9 lines

[m5-dev] changeset in m5: ARM: Use an actual NOP instead of a instruction...

changeset ff8e3075d762 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=ff8e3075d762 description: ARM: Use an actual NOP instead of a instruction that happens to do nothing diffstat: src/arch/arm/isa_traits.hh | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)

Re: [m5-dev] Question on SLICC

Figured that out last night. I also noticed that there is comment about it in RubySlicc_Types.sm (should read files more carefully). Actually, I am trying to get rid of CacheMsg class. Currently, RubyRequest is created from packet (which I believe is an m5 primitive) and then a CacheMsg is crea

Re: [m5-dev] Question on SLICC

> There are certain types defined in the file > src/mem/protocol/RubySlicc_Types.sm. For each of the type is .hh is gets > written which contains the path of the actual header file to be used. For > example, the file RubySlicc_Types.sm defines CacheMemory type. This type is > actually defined in th

Re: [m5-dev] (no subject)

Hi Nilay, My plan is to tackle the functional access support as soon as I check in our current group of outstanding patches. I'm hoping to at least check in the majority of them in the next couple of days. Now that you've completed the CacheMemory access changes, you may want to re-profile GE

Re: [m5-dev] Review Request: Time: Add a mechanism to prevent M5 from running faster than real time.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/419/#review764 --- src/sim/root.hh @file

[m5-dev] (no subject)

Hi Brad Now that those changes to CacheMemory, SLICC and protocol files have been pushed in, what's next that you think we should work on? I was going through some of the earlier emails. You have mentioned functional access support in Ruby, design of the Perfect Switch, consolidation of stat

Re: [m5-dev] Review Request: Time: Add a mechanism to prevent M5 from running faster than real time.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/419/ --- (Updated 2011-01-18 04:25:09.655881) Review request for Default, Ali Saidi, Gabe Bl

[m5-dev] changeset in m5: Unit tests: Convert the refcnttest unit test to...

changeset 4c0f7929ee33 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=4c0f7929ee33 description: Unit tests: Convert the refcnttest unit test to use the new EXPECT macros. diffstat: src/unittest/refcnttest.cc | 93 - 1 file

[m5-dev] changeset in m5: Unit tests: Define a header file for common uni...

changeset 703fbf20c620 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=703fbf20c620 description: Unit tests: Define a header file for common unit testing functions/macros. diffstat: src/unittest/SConscript |2 + src/unittest/unittest.cc | 93 +++

[m5-dev] Cron /z/m5/regression/do-regression quick

scons: *** Found dependency cycle(s): * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing passed. * build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby passed. * build/