Luming Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56609 )
Change subject: arch-riscv: fix memory leak problem in page table walker
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arch-riscv: fix memory leak problem
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/43593 )
Change subject: sim,tests: Add unit test for Globals
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sim,tests: Add unit test for Globals
Add a unit test for
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44107 )
Change subject: sim,tests: Add a tag for gem5 events
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sim,tests: Add a tag for gem5 events
This tag can be used to
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56596 )
Change subject: mem: Add TLB invalidation flags to the Request object
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mem: Add TLB invalidation flags
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56591 )
Change subject: cpu: Handle Request::NO_ACCESS flag in MinorCPU and O3CPU
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cpu: Handle
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56599 )
Change subject: cpu: Allow TLB shootdown requests in the timing cpu
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cpu: Allow TLB shootdown requests
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56598 )
Change subject: cpu: Rename initiateHtmCmd to be more generic
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cpu: Rename initiateHtmCmd to be more
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56603 )
Change subject: arch-arm: Add DVM enabled flag in the ExtMachInst/Decoder
class
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arch-arm: Add DVM
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56607 )
Change subject: arch-arm: Implement DSB Shareable as a DVM op
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arch-arm: Implement DSB Shareable as a
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56601 )
Change subject: arch-arm: Add helper MISCREG to track a pending DVM
operation
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arch-arm: Add helper
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44108 )
Change subject: sim,tests: Add a tag for drain-related files
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sim,tests: Add a tag for drain-related files
This tag
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56592 )
Change subject: arch-arm: Replace mcrMrc15TrapToHyp with mcrMrc15Trap
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arch-arm: Replace
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56602 )
Change subject: arch-arm: Create a magic PendingDvm operand
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arch-arm: Create a magic PendingDvm
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56606 )
Change subject: arch-arm: Implement TLBI Shareable as a DVM op
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arch-arm: Implement TLBI Shareable as a
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56597 )
Change subject: cpu: Fix SimpleExecContext coding style
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cpu: Fix SimpleExecContext coding style
JIRA:
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56600 )
Change subject: cpu: Allow TLB shootdown requests in the o3 cpu
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cpu: Allow TLB shootdown requests in
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56594 )
Change subject: arch-arm: Implement DSB Shareable with a separate class
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arch-arm: Implement DSB
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56593 )
Change subject: arch-arm: Reuse MCR15 trapping code in DC instructions
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arch-arm: Reuse MCR15 trapping
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56605 )
Change subject: arch-arm: Add warning when DVM is enabled in the decoder
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arch-arm: Add warning when
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56604 )
Change subject: arch-arm: Add DVM ISA templates
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arch-arm: Add DVM ISA templates
These will be used by
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56649 )
Change subject: python: Update gem5 url output by the simulator
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python: Update gem5 url output by the
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44110 )
(
12 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-cache,tests: Add unit test for
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55744 )
Change subject: tests: Add x86 mutlicore boot tests for timing CPUs
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tests: Add x86 mutlicore boot tests for timing CPUs
Daecheol You has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56610 )
Change subject: mem-ruby: Memory range configuration for NUMA system
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mem-ruby: Memory range configuration
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