.
Diffs
-
src/dev/mc146818.hh f72bd92d39d2
src/dev/mc146818.cc f72bd92d39d2
Diff: http://reviews.gem5.org/r/2687/diff/
Testing
---
Note that I haven't tested the SPARC tests 02.insttest and
40.m5threads-test-atomic. All other tests pass.
Thanks,
Nikos Niko
the next event with negative offset.
Diffs (updated)
-
src/dev/mc146818.cc UNKNOWN
Diff: http://reviews.gem5.org/r/2687/diff/
Testing
---
Note that I haven't tested the SPARC tests 02.insttest and
40.m5threads-test-atomic. All other tests pass.
Thanks,
Nikos Niko
the next event with negative offset.
Diffs (updated)
-
src/dev/mc146818.cc f72bd92d39d2
Diff: http://reviews.gem5.org/r/2687/diff/
Testing
---
Note that I haven't tested the SPARC tests 02.insttest and
40.m5threads-test-atomic. All other tests pass.
Thanks,
Nikos Niko
the next event with negative offset.
Diffs (updated)
-
src/dev/mc146818.cc 655ff3f6352d
Diff: http://reviews.gem5.org/r/2687/diff/
Testing
---
Note that I haven't tested the SPARC tests 02.insttest and
40.m5threads-test-atomic. All other tests pass.
Thanks,
Nikos Niko
the next event with negative offset.
Diffs (updated)
-
src/dev/mc146818.cc 655ff3f6352d
Diff: http://reviews.gem5.org/r/2687/diff/
Testing
---
Note that I haven't tested the SPARC tests 02.insttest and
40.m5threads-test-atomic. All other tests pass.
Thanks,
Nikos Niko
.
Diffs
-
src/dev/mc146818.cc 655ff3f6352d
Diff: http://reviews.gem5.org/r/2699/diff/
Testing
---
Note that I haven't tested the SPARC tests 02.insttest and
40.m5threads-test-atomic. All other tests pass.
Thanks,
Nikos Nikoleris
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ors only, additional errors omitted ...]
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changeset 68d688cbe26c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=68d688cbe26c
description:
cpu: fix system total instructions accounting
The totalInstructions counter is only incremented when the whole
instruction is
commited and not on every mi
f the MMIO, when the function call returns).
Diffs
-
src/cpu/kvm/base.cc fbdaa08aaa42
Diff: http://reviews.gem5.org/r/2774/diff/
Testing
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e the kernel will first emulate the instruction
and then update the guest's register state.
Diffs
-
src/cpu/kvm/base.cc fbdaa08aaa42
Diff: http://reviews.gem5.org/r/2774/diff/
Testing
---
Thanks,
Nikos Nikoleris
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the TC,
and this patch will break it. So we need more work to fix this.
- Nikos Nikoleris
On May 11, 2015, 3:52 p.m., Nikos Nikoleris wrote:
>
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://review
87/control/save_and_restore_x87_environment.py
fbdaa08aaa42
Diff: http://reviews.gem5.org/r/2881/diff/
Testing
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src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
fbdaa08aaa42
Diff: http://reviews.gem5.org/r/2881/diff/
Testing
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fbdaa08aaa42
src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
fbdaa08aaa42
Diff: http://reviews.gem5.org/r/2881/diff/
Testing
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fbdaa08aaa42
src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
fbdaa08aaa42
Diff: http://reviews.gem5.org/r/2881/diff/
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---
On May 11, 2015, 3:52 p.m., Nikos Nikoleris wrote:
>
> ---
> This is an automatically generated e-mail. To reply, visit
changeset b8b8ad2c72dd in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b8b8ad2c72dd
description:
x86: Adjust the size of the values written to the x87 misc registers
All x87 misc registers are implemented in an array of 64 bit values
but in real hardwar
Hi folks,
I would like to create a couple of unit tests in gem5 using the included
google test library. Some of these unit test instantiate objects which
inherit from SimObject and as a result the code depends on a lot of
other classes.
The dependency tree proved to be quite big and instead of tr
Hi gem5 Devs,
I've posted a set of patches that add support for some basic
write-streaming optimizations in the cache (classic memory). The basic
idea is that once we've detected write-streaming behavior
1) we can coalesce multiple WriteReq into full WriteLineReq to avoid
fetching blocks from memo
Hey all,
The bigger opportunity is probably around packets as sometimes we are
allocating a number of them per request.
A custom allocator would be a great contribution if it would make gem5
substantially faster. But if it proved make things only marginally
better, I agree with Jason, we would ne
Hi Oliver,
I think there are at least two different issues here. One of them can be
fixed by applying this patch:
https://gem5-review.googlesource.com/c/public/gem5/+/14818
The other one has to do with PyTrafficGen and a quick fix for you is to
remove the macro M5_LOCAL from the declaration in
sr
in,
> Pau
>
> -Original Message-
> From: Nikos Nikoleris [mailto:nikos.nikole...@gmail.com]
> Sent: Thursday, June 15, 2017 14:19
> To: gem5 Developer List
> Subject: Re: [gem5-dev] update ARM Full-System Files
> (aarch-system-2014-10.tar.xz)
>
> Hi Pau,
>
>
Hi Gabe,
You can already get the master ID through the request pointer of the
packet (pkt->req->masterId()). But you're right, currently even if you
use something like the master ID to populate the ID field, unless you
keep track of more information you can't know where the packets in the
trace or
Hi Everyone,
I've just posted a set of patches that add support for some of the cache
maintenance instructions found in arm systems. The corresponding operations
supported in the memory system are cache cleans and/or invalidates to the point
of unification or point of coherence as specified by
Hi Daniel,
I am afraid, I can't reproduce the error you're experiencing, and the outputs
from your runs are not very telling of the problem. I run the
realview-simple-atomic-checkpoint regression at:
* 68af229490fc811aebddf68b3e2e09e63a5fa475 and
* 0473286ab1e9992a906eff38bf90c82eeccb
and bo
changeset 479d053f05af in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=479d053f05af
description:
arm: Mark uninitialized new TLB entries as not valid
Previously when we initialized the TLB we would allocate a number of
TLB entries which would be marked
changeset 2383451ff6a5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2383451ff6a5
description:
mem: Fix the snoop filter when there is a downstream addr mapper
The snoop filter handles requests in two steps which preceed and
follow the call to send t
ost of this code in the constructor? The flag
sequentialAccess and the condition lookupLatency >= dataLantency shouldn't
change during the simulation.
src/mem/cache/tags/fa_lru.cc (line 212)
<http://reviews.gem5.org/r/3502/#comment7315>
Same here
- Nikos Nikoleris
On Jun
2>
Please wrap the comment such it does not violate the 79 char per line limit
- Nikos Nikoleris
On June 20, 2016, 3:07 p.m., Sophiane SENNI wrote:
>
> ---
> This is an automatically generated e-mail
body
should be wrapped such that no line is more than 75 characters rather than the
whole body being limited to 76 char.
- Nikos Nikoleris
On June 28, 2016, 9:57 a.m., Sophiane SENNI wrote:
>
> ---
> This is an automatically ge
> On June 27, 2016, 5 p.m., Nikos Nikoleris wrote:
> > src/mem/cache/tags/base_set_assoc.hh, line 218
> > <http://reviews.gem5.org/r/3502/diff/8/?file=56390#file56390line218>
> >
> > Would it make sense to move most of this code in the constructor? The
changeset b921b96cbf74 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b921b96cbf74
description:
mem: Remove stale argument from a DPRINTF in the cache code
Change-Id: I70dd11c23b45dfc606ef08233d2e50fcc0817505
Reviewed-by: Andreas Sandberg
diffstat:
> On June 27, 2016, 5 p.m., Nikos Nikoleris wrote:
> > src/mem/cache/tags/base_set_assoc.hh, line 218
> > <http://reviews.gem5.org/r/3502/diff/8/?file=56390#file56390line218>
> >
> > Would it make sense to move most of this code in the constructor? The
> On June 27, 2016, 5 p.m., Nikos Nikoleris wrote:
> > src/mem/cache/tags/base_set_assoc.hh, line 218
> > <http://reviews.gem5.org/r/3502/diff/8/?file=56390#file56390line218>
> >
> > Would it make sense to move most of this code in the constructor? The
src/mem/cache/tags/base.cc (line 66)
<http://reviews.gem5.org/r/3502/#comment7395>
you don't need the parenthesis here over
- Nikos Nikoleris
On July 20, 2016, 1:32 p.m., Sophiane SENNI wrote:
>
> ---
> This
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3502/#review8525
---
Ship it!
Ship It!
- Nikos Nikoleris
On July 25, 2016, 1:16 p.m
> On July 25, 2016, 1:18 p.m., Nikos Nikoleris wrote:
> > Ship It!
>
> Sophiane SENNI wrote:
> How can I commit the patch ? I am not sure I have the commit access ?
You can't commit it youself, one of the maintainers will have to commit
changeset 65ae342b627b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=65ae342b627b
description:
mem: Add support for secure packets in the snoop filter
Secure and non-secure data can coexist in the cache and therefore the
snoop filter should treat dif
changeset 6319a1125f1c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6319a1125f1c
description:
cpu, arch: fix the type used for the request flags
Change-Id: I183b9942929c873c3272ce6d1abd4ebc472c7132
Reviewed-by: Andreas Sandberg
diffstat:
src/arc
changeset 3fb50f935a6a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3fb50f935a6a
description:
mem: Print an MSHR without triggering any assertions
Previously printing an mshr would trigger an assertion if the MSHR was
not in service or if the target
state.
Change-Id: I3f7a8e97bfd3e2e49bebad056d11bbfb087aad91
Reviewed-by: Andreas Hansson
Reviewed-by: Stephan Diestelhorst
Diffs
-
src/mem/cache/mshr.cc 1d085f66c4ca
src/mem/cache/mshr.hh 1d085f66c4ca
Diff: http://reviews.gem5.org/r/3723/diff/
Testing
---
Thanks,
Nikos
: If3ec2516992f42a6d9da907009ffe3ab8d0d2021
Reviewed-by: Andreas Hansson
Reviewed-by: Stephan Diestelhorst
Diffs
-
src/mem/cache/cache.cc 1d085f66c4ca
src/mem/cache/mshr.hh 1d085f66c4ca
src/mem/cache/mshr.cc 1d085f66c4ca
Diff: http://reviews.gem5.org/r/3724/diff/
Testing
---
Thanks,
Nikos
1d085f66c4ca
src/mem/cache/mshr.cc 1d085f66c4ca
Diff: http://reviews.gem5.org/r/3725/diff/
Testing
---
Thanks,
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useful for the
memchecker.
Change-Id: Id1a6b8f02853789b108ef6003f4c32ab929bb123
Reviewed-by: Andreas Hansson
Reviewed-by: Stephan Diestelhorst
Diffs
-
src/cpu/testers/traffic_gen/generators.cc 1d085f66c4ca
Diff: http://reviews.gem5.org/r/3726/diff/
Testing
---
Thanks,
Nikos
,
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/r/3730/diff/
Testing
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/3731/diff/
Testing
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c/mem/snoop_filter.cc 1d085f66c4ca
Diff: http://reviews.gem5.org/r/3732/diff/
Testing
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Thanks,
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Hansson
Diffs
-
src/mem/cache/cache.cc 1d085f66c4ca
Diff: http://reviews.gem5.org/r/3733/diff/
Testing
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Thanks,
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://reviews.gem5.org/r/3734/diff/
Testing
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/diff/
Testing
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src/mem/cache/mshr.cc 1d085f66c4ca
Diff: http://reviews.gem5.org/r/3735/diff/
Testing
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/coherent_xbar.cc 1d085f66c4ca
src/mem/packet.cc 1d085f66c4ca
src/mem/snoop_filter.cc 1d085f66c4ca
Diff: http://reviews.gem5.org/r/3728/diff/
Testing
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: Id2c2fe82a8175d9a67eb4cd7f3d2e2720a809b60
Reviewed-by: Andreas Hansson
Diffs
-
configs/example/memcheck.py 1d085f66c4ca
Diff: http://reviews.gem5.org/r/3737/diff/
Testing
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Fellow gem5 developers,
I have just posted a number of patches on the reviewboard that address two
issues with the memory model of the classic memory system. This is a short
description of the context for these patches to help out with any reviews.
The first set of patches deals with memory ord
ker's coverage)
10) #3737 - config: Add an option to generate a random topology in memcheck
Thanks,
Nikos
____
From: Nikos Nikoleris
Sent: 18 November 2016 17:20:57
To: Default
Subject: Memory model patches for review
Fellow gem5 developers,
I have just posted a
changeset 6e1cb0f750c0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6e1cb0f750c0
description:
mem: Add support for repopulating the flags of an MSHR TargetList
This patch adds support for repopulating the flags of an MSHR
TargetList. The added funct
changeset 72916416d2e2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=72916416d2e2
description:
mem: Keep track of allocOnFill in the TargetList
Previously the information of whether a response was allocating or not
was a property of the MSHR. This ch
changeset 6b84b831f47d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6b84b831f47d
description:
mem: Assert that the responderHadWritable is set only once
Change-Id: Ie3beeef25331f84a0a5bcc17f7a791f4a829695b
Reviewed-by: Andreas Hansson
Revie
changeset 3dcf0b891749 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3dcf0b891749
description:
mem: Service only the 1st FromCPU MSHR target on ReadRespWithInv
A response to a ReadReq can either be a ReadResp or a
ReadRespWithInvalidate. As we add ta
changeset e922938edf18 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e922938edf18
description:
config: Add whole line accesses to improve memchecker's coverage
Change-Id: Ie1a047139e350ce7400f3a20be644eaff1e21428
Reviewed-by: Andreas Hansson
diffst
changeset 5d33c6972dda in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5d33c6972dda
description:
mem: Make packet debug printing more uniform
Previously DPRINTFs printing information about a packet would use ad hoc
formats. This patch changes all DPRIN
changeset cd6248b276a8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cd6248b276a8
description:
mem: Respond to InvalidateReq when the block is (pending) dirty
Previously when an InvalidateReq snooped a cache with a dirty block or
a pending modified M
changeset 55bd32c72867 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=55bd32c72867
description:
mem: Don't use hasSharers in the snoopFilter for memory responses
When the snoopFilter receives a response, it updates its state using
the hasSharers flag
changeset a6da15219f95 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a6da15219f95
description:
mem: Always use InvalidateReq to service WriteLineReq misses
Previously, a WriteLineReq that missed in a cache would send out an
InvalidateReq if the block
changeset 6aefb19ff369 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6aefb19ff369
description:
config: Add an option to generate a random topology in memcheck
This change adds the option to use the memcheck with random memory
hierarchies at the momen
changeset 3b2cb95f48ed in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3b2cb95f48ed
description:
mem: Allow non invalidating snoops on an InvalidateReq MSHR
This patch changes an assertion that previously assumed that a non
invalidating snoop request s
changeset c15cc4d973ea in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c15cc4d973ea
description:
mem: Invalidate a blk when servicing the 1st invalidating target
Previously an MSHR with one or more invalidating targets would first
service all targets i
> On Jan. 5, 2017, 4:32 p.m., Tony Gutierrez wrote:
> > Is there anything holding this up from being shipped?
>
> Andreas Hansson wrote:
> In my view the patch needs two things:
>
> 1) Some thought around the design. I am still hoping there is a less
> invasive way of accommodating
obably be better code, but it's a huge amount
> of work that I don't see anyone signing up for right now, so I think it's
> better to put this change in as is for now, and put "restructuring the cache"
> on the to-do list.
>
> Nikos Nikoleris wrote:
>
494ab5474716
Diff: http://reviews.gem5.org/r/3779/diff/
Testing
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Hi Kirk,
The problem is that protobuf relies on the fact that undefined
preprocessor symbols are expanded by default to 0. This is causing
problems for gem5 as for sanity we force the compiler to warn for
undefined symbols.
I posted a workaround on the reviewboard
http://reviews.gem5.org/r/3779/
uncacheable
request if I am not mistaken.
- Nikos Nikoleris
On Dec. 19, 2016, 7:39 p.m., Eric Clark wrote:
>
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem
obably be better code, but it's a huge amount
> of work that I don't see anyone signing up for right now, so I think it's
> better to put this change in as is for now, and put "restructuring the cache"
> on the to-do list.
>
> Nikos Nikoleris wrote:
>
changeset 63325e5b0a9d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=63325e5b0a9d
description:
proto: Fix warnings for protoc v3
protoc v3 introduces a new syntax for proto files and warns when the
syntax is not explicitly stated.
protoc rel
changeset 7ba0f5d4ad70 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7ba0f5d4ad70
description:
misc: Add dtb files to the ignore list for git and mercurial
Change-Id: Ifb135c60e050c55769914e853b07a387c06e4007
Reviewed-by: Curtis Dunham
Signe
changeset b47dda418ae6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b47dda418ae6
description:
mem: Remove stale argument from a panic statement
Change-Id: I7ae5fa44a937f641a2ddd242a49e0cd23f68b9f2
Reviewed-by: Sudhanshu Jha
Reviewed-by: Cur
changeset 608f8c34f549 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=608f8c34f549
description:
mem: Populate the secure flag in the writeback visitor
Previously the writeback visitor would not consider and set the secure
flag for the blocks that are
changeset 1342b4dbc556 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1342b4dbc556
description:
mem: Always use the helper function to invalidate a block
Policies like the LRU need to be notified when a block is invalidated,
the helper function does t
changeset cc435f8f8b05 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cc435f8f8b05
description:
mem: Remove unused functions from the tag classes
Change-Id: I4f3c2c027b1acaaf791a4c71086f34a9b9fbf4df
Reviewed-by: Andreas Hansson
Signed-off-by:
changeset b470020b29de in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b470020b29de
description:
mem: Remove unused arguments (asid/contex_id) from accessBlock
Change-Id: I79c2662fc81630ab321db8a75be6cd15fa07d372
Reviewed-by: Andreas Hansson
S
changeset ba90ffa751b6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ba90ffa751b6
description:
mem: Remove unused size field from the CacheBlk class
Change-Id: I6149290d6d2ac1a4bd6165871c93d7b7d6a980ad
Reviewed-by: Andreas Hansson
Signed-off
changeset aa9d04c7e3bb in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=aa9d04c7e3bb
description:
mem: Remove unused type BlkList from the cache and the tags
Change-Id: If9ebb8488e8db587482ecfa99d2c12cfe5734fb9
Reviewed-by: Andreas Hansson
Sign
changeset 474ac613d0d7 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=474ac613d0d7
description:
mem: Remove the unused asid field from the CacheBlk class
Change-Id: I29f45733c5fad822bdd0d8dcc7939d86b2e8c97b
Reviewed-by: Andreas Hansson
Signed
changeset 9684637f3339 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9684637f3339
description:
arm: Blame the right instruction address on a Prefetch Abort
CPU models (e.g., O3CPU) issue instruction fetches for the whole cache
block rather than a spe
changeset ce333ae9ee02 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ce333ae9ee02
description:
arm: Fix DPRINTFs with arguments in the instruction declarations
Change-Id: I0e373536897aa5bb4501b00945c2a0836100ddf4
Reviewed-by: Curtis Dunham
S
494ab5474716
Diff: http://reviews.gem5.org/r/3828/diff/
Testing
---
Thanks,
Nikos Nikoleris
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/mem/cache/tags/base_set_assoc.cc 494ab5474716
src/mem/cache/tags/fa_lru.hh 494ab5474716
Diff: http://reviews.gem5.org/r/3829/diff/
Testing
---
Thanks,
Nikos Nikoleris
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Hi all,
Last week posted a patch for a review [1], which uses case ranges. Case ranges
make switch statements more concise, an example would be
switch (var) {
case 1 ... 3:
break;
}
Without case ranges, we would either need to use if statements or multiple case
statements if the range i
Hi Everyone,
I've just posted a set of patches that allow ARM Realview systems to boot Linux
with Ruby.
The major change in these patches is the added support for address ranges in
the Directory. Systems like ARM that don't assume a continuous memory range
starting from 0 used to be a problem
Hi Pau,
Thanks again for providing the scripts and the binaries for the new
ARM system files.
I was trying them today and it seems that for the 32bit ARM (aarch32)
system files, the m5 util is copied to /sbin/m5.aarch32 rather than
/sbin/m5. This will likely break bootscripts that expect the m5
u
Hi Daniel,
If I remember correctly, the rules on commit tags changed about 2.5
years ago (see also git log MAINTAINERS) along with the migration from
mercurial to git. Previously tags such as arch-arm and arch-x86 were
simply arm and x86. In addition tags such as dev-arm, systemc were added
more r
Nikos Nikoleris has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10422 )
Change subject: mem-cache: Determine if an MSHR has requests from another
cache
..
mem-cache: Determine if an MSHR
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I09902d648d7272f0f9ec2851fa6376f7305ba418
Gerrit-Change-Number: 10424
Gerrit-PatchSet: 4
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G
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each block in the tag store and apply a visitor to the
* block.
*
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ge-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
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