can we get to a place
where we can have
(c) 200X University of Michigan
(c) 200X MIPS
(c) 200X FSU
instead of 100 lines of license?
Ali
On Tue, Mar 11, 2008 at 1:15 AM, Ali Saidi [EMAIL PROTECTED] wrote:
Also, we really need to be able to just append the X copyright holders
to the same bsd
I think the question is it OK with the legal dept of FSU?
Ali
On Mar 18, 2008, at 7:23 PM, Stephen Hines wrote:
I only copied/pasted the license for anything that says FSU on it.
If it needs
to be changed, it is ok with me.
Steve
--
Stephen Hines
[EMAIL
the license. That might make their lawyers feel a bit more
at ease.
Nate
On Tue, Mar 18, 2008 at 1:41 PM, Ali Saidi [EMAIL PROTECTED] wrote:
What about replacing company/university name with, above mentioned
copyright holders, or something similar.
That seems to solve both problems,
Ali
On Mar 17
On Mar 23, 2008, at 5:32 PM, nathan binkert wrote:
scons: *** [build/SPARC_FS/params/params_wrap.cc] Error 1
Looks like this was just a pool glitch... I reran the script and it
biult fine.
This is actually due to a missing dependency that I found/fixed last
night. I'll commit it as soon
I moved some things around to make this work. Unfortunately, diff made
the changset look a lot bigger than it really is.
Ali
On Apr 5, 2008, at 2:06 PM, Ali Saidi wrote:
# HG changeset patch
# User Ali Saidi [EMAIL PROTECTED]
# Date 1207418753 14400
# Node ID
Ahh... I get it. We don't pass the BATCH_CMD command into the lower
level SConscripts to libelf doesn't get built with qdo2. That would be
ok, except that zizzer is now a 64 bit host.
Ali
On Apr 6, 2008, at 3:10 PM, Ali Saidi wrote:
This happened because some how build/libelf/ was compiled
with ISAs
User who did this: - Ali Saidi (saidi)
Attached to Project - M5 Bugs
Summary - Fix makeExtMI to be more flexible with ISAs
Task Type - Bug
Category - CPU
Status - New
Assigned To - Kevin Lim
Operating System - All
Severity - Medium
Priority - Normal
Reported Version - 1.1
Due in Version - Due
information about what has changed, visit the URL and click the
History tab.
FS#126 - SPARC ISA support
User who did this: - Ali Saidi (saidi)
Attached to Project - M5 Bugs
Summary - SPARC ISA support
Task Type - Major Feature
Category - ISA Support
Status - Assigned
Assigned To - Gabe Black
Operating
I'll fix it soon.
Ali
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It's back up... If you get a redirection error you need to clear your
cookies.
Ali
On Apr 11, 2008, at 3:05 PM, Ali Saidi wrote:
I'll fix it soon.
Ali
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Everyone,
We've moved all of the outstanding tasks and bugs from our internal
bug tracker to flyspray at: http://www.m5sim.org/flyspray/
We list the various features and bugs and what release we would like
them to by done by. If you have any suggestions, comments please add
them and if
We talked about doing precisely that several years ago. You can also
then compress the individual pages and also hash them so that you only
need one copy of any page that's replicated. There is a probably a
flyspray task to do just that, but no one got around to doing it. In
the short term
The failed I would guess is a real error. The time out is just because
that test takes over 6 hours on the pool nodes and qdo times out.
Ali
On Apr 27, 2008, at 1:34 PM, Gabe Black wrote:
Are these real errors or pool errors?
Cron Daemon wrote:
*
changeset 7738a042628b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7738a042628b
summary: SCons: More scons fixing for SCons bug 2006
diffstat:
1 file changed, 6 insertions(+)
src/kern/SConscript |6 ++
diffs (13 lines):
diff -r e4987b6ca365 -r 7738a042628b
changeset 1af0b428ac2f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1af0b428ac2f
summary: Make sure that output files are always checked success before they're
used.
diffstat:
5 files changed, 14 insertions(+), 14 deletions(-)
src/base/output.cc |4 ++--
, 2008, at 2:05 PM, Ali Saidi [EMAIL PROTECTED] wrote:
We can't because the date is created by the compiler with the
__DATE__ __TIME__ macros. The only way to do something like this
would be create a dummy file that we write a string to in the
SConscript. We can set it's dependencies to be all
was compiled with assuming you have patches on top of it. It's
something that could be handy although I'm sure we'd survive without
it.
Gabe
Ali Saidi wrote:
Why do we care about the central repository version?
Ali
On May 22, 2008, at 8:13 PM, Gabe Black wrote:
So anyway, now that we seem
changeset 3db61f7be690 in /z/repo/linux/patches
details: http://m5sim.org/repolinux/patches?cmd=changeset;node=3db61f7be690
summary: M5 Struct: add two missing symbols for M5 ThreadInfo
diffstat:
1 file changed, 3 insertions(+), 1 deletion(-)
m5/m5struct.diff |4 +++-
diffs (20 lines):
diff
On May 28, 2008, at 11:23 AM, nathan binkert wrote:
panic() -- An assert that isn't compiled out
fatal() -- some configuration parameter caused a problem
Ok, I thought so. Do we want to keep these names? I will promise
that I have learned finally, but the names seem a bit to synonymous to
Why can't you just stick it in the constructor? You'll need to
serialize that timer value when a checkpoint is dropped and create an
event when the checkpoint is restored from, but you would need to do
that anyway. You can take a look at how we serialize the PIT for an
idea.
Ali
On May
It's because the repository isn't where it should be, so the
regression script just errors out on something near the first line.
Ali
On Jun 2, 2008, at 3:24 AM, Gabe Black wrote:
This doesn't seem very helpful...
Cron Daemon wrote:
See /z/m5/regression/regress-2008-06-02-03:00:01 for
What if it's supposed to be UM and MIPS?
[(UM, [2006], ['Blah']), (MIPS, [2007], ['Foo'])] ??
Ali
On Jun 1, 2008, at 4:34 PM, nathan binkert wrote:
Looking through the mips directory for files that are just
copyright MIPS
and not UM
interrupts.cc seems to be derived from
changeset 3768873ebbc6 in /z/repo/linux/patches
details: http://m5sim.org/repolinux/patches?cmd=changeset;node=3768873ebbc6
summary: Add Linux 2.6.22 default config
diffstat:
2 files changed, 1059 insertions(+)
m5/defaultconfig_2.6.22.diff | 1058 ++
series
On Jun 7, 2008, at 2:09 PM, Steve Reinhardt wrote:
My biggest worry about 3-6 months is that we often have fixes that
are
important and more recent than 3-6 months. Beta 5 is barely three
months old and has at least two important patches, right?
I was just going to use that same
I'm not really concerned if it catches all the exceptions. I guess I
would rather have it say it's unknown, instead raising an exception
that doesn't really matter all that much.
Ali
On Jun 7, 2008, at 4:19 PM, nathan binkert wrote:
How about this? (I didn't actually run it). I just worry
On Jun 7, 2008, at 5:52 PM, Ali Saidi wrote:
On Jun 7, 2008, at 5:44 PM, nathan binkert wrote:
Aren't these statements contradictory? If you have the patch sets
under separate subdirs, can they come from different repos? Would
you
still have to manually merge the series file? I don't
I quickly scanned the SCons documentation and couldn't find anything
built in, but clearly the kernel does it so it can be done.
Ali
On Jun 9, 2008, at 5:48 AM, Gabe Black wrote:
Is there some way we can make m5 link incrementally, or in other
words
link subsystems together
I've done some reading online and it doesn't appear that incremental
linking will cut down on the link time much at all. Doing it in
smaller chunks doesn't help if all the symbols end up being exported
at the end. The two ways to speed it up are to (a) not include any
debugging information
symbols. That said, is it faster to incremental link strip and then
finish the link? I'm just curious if there are any symbols that we
can automatically strip.
Then again, I build debug most of the time and you wouldn't want to
strip that, so...
Nate
On Mon, Jun 9, 2008 at 10:50 AM, Ali
If we wait 1 week (the 18th), it will be exactly 2 years from when we
said we would have 2.0 done and the repository released at the M5
tutorial at ISCA 2006. :)
Ali
On Jun 11, 2008, at 7:38 PM, nathan binkert wrote:
Unless anyone has an objection, I think the new repository is open for
The hgrc for the repo didn't exist/wasn't copied from the old
directory. I've added it and I imagine the e-mails will now be sent.
Ali
On Jun 12, 2008, at 2:25 AM, Gabe Black wrote:
I just did a big push but there was no email... Also, I made sure
everything compiled and ran all the quick
I did a little bit of digging and you can specify a taged version of
the repo like this:
http://site/repo/archive/tag.tar.bz2 and it will download version of
the repo.
Ali
On Jun 12, 2008, at 10:06 AM, Ali Saidi wrote:
The hgrc for the repo didn't exist/wasn't copied from the old
Looking at this code it seems like the easiest thing is to make sure
that dmi_get_year(DMI_BIOS_DATE) = 2001.Do you have a DMI table? If
you set the BIOS date 2001 the function could be skipped. It's just
checking if it some device exists that makes it think this is actually
PCI that it's
On Jun 13, 2008, at 11:48 AM, nathan binkert wrote:
Are instances of class objects uniquely identifiable and usable as
keys?
Only if they provide a __hash__ function, but in theory it should be
possible.
If so, you could use the class as a key using the same mechanism
instead
of
On Jun 16, 2008, at 1:01 PM, Nathan Binkert wrote:
I mentioned in a e-mail last night that I'd like to rename the various
things that are called console so that the names are not as ambiguous.
The following renames apply:
SimConsole - Terminal
AlphaConsole - AlphaBackdoor
MipsConsole -
On Jun 20, 2008, at 10:06 PM, Steve Reinhardt wrote:
/** Return a virtual port. If no thread context is specified then
a static
* port is returned. Otherwise a port is created and returned. It
must be
* deleted by deleteVirtPort(). */
VirtualPort*
00:19:51 [saidi:zizzer /z/m5/regression/poolfs/m5] cat build/ALPHA_FS/
tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-
atomic/stderr
warn: kernel located at: /dist/m5/system/binaries/vmlinux
panic: ListenSocket(listen): listen() failed!
@ cycle 0
changeset ebec0a848220 in /z/repo/m5-stable
details: http://repo.m5sim.org/m5-stable?cmd=changeset;node=ebec0a848220
summary: Checkpoinging/SWIG: Undo part of changeset 5464 since it broke
checkpointing.
diffstat:
1 file changed, 1 deletion(-)
src/python/swig/event.i |1 -
diffs (14 lines):
This changeset creates an extraordinarily large memory leak. Every
time getVirtPort(tc) is called a peer seems to be created that is
never deleted. This is particularly problematic since CopyString*()
uses getVirtPort(tc) and so within a minute of executing a kernel with
a lot of
) calls then I could probably
uncomment the disconnectFromPeer() call in Port::setPeer() and that
would go a long way toward fixing the actual memory leak.
Steve
On Fri, Jun 27, 2008 at 3:50 PM, Ali Saidi [EMAIL PROTECTED] wrote:
This changeset creates an extraordinarily large memory leak. Every
I vote for (1) until it can be shown that it matters. A single pointer
doesn't seem like a big deal, especially since most of the things we
create and destroy frequently aren't SimObjects but other classes.
Ali
On Jun 29, 2008, at 12:23 PM, nathan binkert wrote:
I'm nearly done with the
# HG changeset patch
# User Ali Saidi [EMAIL PROTECTED]
# Date 1214782927 14400
# Node ID ada5724fbc53640aa6b85ba82e5a43d2e7a67092
# Parent d9de38fba64c204f5eb5ea87adb9b9c0c9e9c1c6
After a checkpoint (and thus a stats reset), the
not_idle_fraction/notIdleFraction statistic is really wrong
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# HG changeset patch
# User Ali Saidi [EMAIL PROTECTED]
# Date 1214782929 14400
# Node ID 363df5ea90da6ff8283c0f3d9c29a4e26efbe4a5
# Parent 8f98b8f28e474fc98d16f5e3973b01a5f2b0a6ff
Make the cached virtPort have a thread context so it can do everything that a
newly created one can.
diff --git
# HG changeset patch
# User Ali Saidi [EMAIL PROTECTED]
# Date 1214783163 14400
# Node ID 1c93d818b049e51e3b86c123d3ad86a1555a467b
# Parent 363df5ea90da6ff8283c0f3d9c29a4e26efbe4a5
Change everything to use the cached virtPort rather than created their own each
time.
This appears to work, but I
there is a status() accessor method, but nothing uses. It seems
unnecessary to to have a method to read the a variable that only the
object that contains that variable uses.
Ali
On Jun 29, 2008, at 7:45 PM, Ali Saidi wrote:
# HG changeset patch
# User Ali Saidi [EMAIL PROTECTED]
# Date
On Jun 29, 2008, at 10:53 PM, Ali Saidi wrote:
On Jun 29, 2008, at 8:28 PM, Steve Reinhardt wrote:
On Sun, Jun 29, 2008 at 4:49 PM, Ali Saidi [EMAIL PROTECTED]
wrote:
one question
is how to enforce encourage objects that call getVirtPort() to not
cache the virtual port
since if the CPU
On Jun 30, 2008, at 5:15 PM, Steve Reinhardt wrote:
On Mon, Jun 30, 2008 at 9:11 AM, Ali Saidi [EMAIL PROTECTED] wrote:
The FastAlloc pools and StaticInst cache should clearly be
duplicated.
Why would you want to duplicate the StaticInst cache? It's a
read-mostly structure so you'd only
changeset 6899b894166f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6899b894166f
summary: After a checkpoint (and thus a stats reset), the
not_idle_fraction/notIdleFraction statistic is really wrong.
changeset 89a6483d7047 in /z/repo/m5
details:
Ummm... why are their output file differences? All the regressions
have been passing just fine.
Ali
On Jul 21, 2008, at 8:12 PM, nathan binkert wrote:
I'm running a full regression on zizzer right now and I'm going to
commit all of the changes since there are a bunch of output file
Hi Jiayuan,
I've just briefly started looking at your patches. All of them compile
with the exception of SimpleMultiThreads.patch. When I attempt to
compile it I get the following errors:
In file included from build/ALPHA_FS/cpu/simple/atomic.hh:35,
from
changeset d8ab33f5ff9a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d8ab33f5ff9a
description:
Return an UnimpFault for an ITB translation of an uncachable address.
We don't support fetching from uncached addresses in Alpha and it means that a
speculative fetch can
changeset 92b89377be48 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=92b89377be48
description:
More subtle fixes to how interrupts are supposed to work in the device.
Fix postedInterrupts statistics.
diffstat:
0 files changed
diffs (59 lines):
diff -r d8ab33f5ff9a
changeset 9eaf72819836 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9eaf72819836
description:
Add the ability for a DMA to tack on an extra delay after the DMA is
actually finished.
diffstat:
2 files changed, 3 insertions(+), 3 deletions(-)
src/dev/io_device.cc |
changeset 24d9f0941095 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=24d9f0941095
description:
Add the ability to specify a think time before descriptor
fetch/writeback starts/ends as well as after read/write dmas
diffstat:
3 files changed, 7 insertions(+), 1
Some recent change causes the params_wrap.cc file to be constantly
rebuilt. Every time I build M5 (even if there have been no changes) I
see the following swig line:
swig -c++ -python -modern -templatereduce -Iext/dnet -I/usr/include/
python2.5 -Ibuild/libelf -Ibuild/ALPHA_FS -outdir
You can do a trick like we do for adding the caches to the CPU. Add
all of the objects to a member that begins with an underscore and then
have a connectAllSouthBridge() function that makes all the connections.
Ali
On Aug 20, 2008, at 10:20 PM, Gabe Black wrote:
I'm working on breaking
Why not have an keep the SouthBridge in the hierarchy to manage the
pieces while having them all directly connect to the bus. This seems
like a lot of work to get rid of a SimObject in C++ that won't be
doing much.
Ali
On Aug 21, 2008, at 4:46 PM, [EMAIL PROTECTED] wrote:
I don't think
Everyone should hold off pushing patches to the dev tree for the next
two weeks so we can create a new stable release. Please only push
fixes to known problems and test the repository in the next two weeks.
Thanks,
Ali
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messages
3. Better statistics for the caches.
4. FS mode doesn't work under Cygwin
5. memtest regression crashes under Cygwin
6. Make repository public
7. Testing
8. Validation
On Aug 24, 2008, at 9:55 AM, Ali Saidi wrote:
Everyone should hold off pushing patches to the dev tree for the next
changeset 3bd1fa125989 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3bd1fa125989
description:
IGbE: Patches I neglected to apply before pushing the previous igbe
changeset
diffstat:
2 files changed, 2 insertions(+)
src/dev/i8254xGBe.cc |1 +
src/dev/i8254xGBe.hh
gone away on it's own, but I don't think
anyone actively tried to fix it.
Gabe
Ali Saidi wrote:
From the release notes the following are still outstanding for a 2.0
release. I don't really care about the Cygwin problems and I'm not
sure that anyone else does, so I move to strike those
The changeset that caused this was:
changeset: 5520:cf280b3621cf
user:Steve Reinhardt [EMAIL PROTECTED]
date:Sun Aug 03 18:13:29 2008 -0400
summary: Make default PhysicalMemory latency slightly more
realistic.
It must be a latent bug that was exposed when Steve changed the
of
the regression. It might have gone away on it's own, but I don't
think
anyone actively tried to fix it.
Gabe
Ali Saidi wrote:
From the release notes the following are still outstanding for a 2.0
release. I don't really care about the Cygwin problems and I'm not
sure that anyone else
Is there a way to forward declare a typedef? We used PacketPtr and
RequestPtr all over the place in header files which requires including
packet.hh and request.hh. However, in many cases the only reason we
need to include the header files is because of the typedef.
Ali
PacketPtr and PacketReq aren't reference counting. We just starting
using them incase we wanted reference counting pointers. Looking at
the code we do a reasonably job of using PacketPtr everywhere, but
RequestPtr is used maybe 40% of the time.
Ali
On Aug 24, 2008, at 3:20 PM, Gabe Black
This sounds interesting.
Ali
Begin forwarded message:
From: Peter Arrenbrecht [EMAIL PROTECTED]
Date: August 26, 2008 11:26:31 AM GMT-04:00
To: mercurial [EMAIL PROTECTED]
Subject: RFC: stacks - patch management extension inspired by bzr-loom
Reply-To: [EMAIL PROTECTED]
Hi all
I've
# HG changeset patch
# User Ali Saidi [EMAIL PROTECTED]
# Date 1220389563 14400
# Node ID 5de467c4d71880ff9767158561e8490c4afaeaf0
# Parent 6a27bc3fc267be638942ba02ac058812aaed86da
Make m5term use select() so OS X is happy.
diff --git a/util/term/term.c b/util/term/term.c
--- a/util/term/term.c
I finally sat down and made the m5term work with OS X. I haven't
tested it that much, so please give it a try and let me know if
anything is broken.
Ali
On Sep 2, 2008, at 5:07 PM, Ali Saidi wrote:
# HG changeset patch
# User Ali Saidi [EMAIL PROTECTED]
# Date 1220389563 14400
# Node
I would say that it probably doesn't matter since I doubt anyone is
using x86. We're trying to get a new stable release ready anyway, so
we should probably just wait for that.
Ali
On Sep 2, 2008, at 5:23 PM, Steve Reinhardt wrote:
It's fine with me, since it probably doesn't touch anything
I don't think there should be any problem with these working.
Ali
On Sep 5, 2008, at 2:48 AM, Gabe Black wrote:
More concretely, if you look in appendix F of the third Intel
manual, it
shows the formats of the messages the APICs would send each other over
the special purpose APIC bus.
Statistics cleanup? gcc 4.2?
Ali
On Sep 6, 2008, at 1:25 PM, nathan binkert wrote:
What's still left to do for stable? There's the SMT regression
failure. Korey or Kevin can you guys look into that so we can get
this done? Is there anything else? I have stuff just waiting to get
into
On Sep 6, 2008, at 4:26 PM, Gabe Black wrote:
There are two major problems with using the DmaPort. First, I'd want
to
send the interrupt -now- not when the DMA queuing latency, etc gets
used
up. Second, DmaPort will fragment a packet which, while maybe
necessary
in some cases, will
Seems reasonable to me.
Ali
On Sep 8, 2008, at 6:32 PM, nathan binkert wrote:
I'm trying to get thing working in gcc 4.3, so I installed a beta of
intrepid ibex.
The first bug was that the logic for detecting GCC is wrong in some
way. How about the attached diff. It seems right for old
I don't think this optimization will work. The reason that the get and
update parts were separated was because getInterupt() is supposed to
be callable without changing the interrupt/system state. If memory
serves the reason for this is because there are cases where you might
call get a
On Sep 8, 2008, at 8:19 PM, nathan binkert wrote:
As usual the gnu guys are out to make our life easier. I've more or
less got things working with 4.3, but there are a couple of issues we
need to sort out. I'll also need people to compile M5 on as many
systems as possible to make sure that
run expand on the patch files before trying to apply them...
Everything should work fine.
Ali
On Sep 10, 2008, at 4:44 PM, [EMAIL PROTECTED] wrote:
I really hope this isn't going to make applying all my patches
significantly
harder...
Gabe
Quoting Ali Saidi [EMAIL PROTECTED
.
Gabe
Quoting Ali Saidi [EMAIL PROTECTED]:
changeset 3af77710f397 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3af77710f397
description:
style: Remove non-leading tabs everywhere they shouldn't be.
Developers
should configure their editors to not insert tabs
From a quick read it sounds like option 2 would be better, cleaner,
and more extensible. In reality other than Alpha all ISAs have some
microcoded instructions. I don't see a reason not to deal with
microops as first class operations.
Ali
On Sep 14, 2008, at 5:19 PM, Gabe Black wrote:
I kind of ran into a similar thing with sparc. There is configuration
code that needed to inform the system about the speed/size/type of
various objects. It would be good to have a C++ interface to easily
query the object tree to be able to make those determinations.
Ali
On Sep 20, 2008,
changeset e82da424c28f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e82da424c28f
description:
SCons: Update compare_versions() to ignore trailing charecters in
versions.
diffstat:
0 files changed
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You're talking about replacing return flags[t]; with a space optimized
bit vector? I imagine it would help performance some if for no other
reason that the trace flags would fit is a single cache block rather
than spanning multiple as they do now.
Ali
On Sep 23, 2008, at 2:42 AM, Gabe
On Sep 23, 2008, at 9:28 PM, Steve Reinhardt wrote:
I believe it's impossible fault on a microop in the middle of a
macroop and then resume where you left off in the middle of the
macroop flow. If you fault you will roll back to the state at the
beginning of the macroop and then on
I could go either way. If it forced us to just get it done in 2 or 3
days then it would be worth it. Otherwise, we should push it off, but
not too far.
Ali
On Sep 26, 2008, at 11:51 PM, nathan binkert wrote:
Do you want to hold off on letting a stable out for this stuff? I'd
say that we
Unless Korey can come up with a fix by tomorrow, I vote to put in a
panic() (not an assert) so we can create a stable release that works
with gcc 4.3.
Ali
On Sep 24, 2008, at 9:43 AM, nathan binkert wrote:
oh i think I see now...
This shadow set code and DSP/MT was done by myself and
changeset 6be5ac0eb1ea in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6be5ac0eb1ea
description:
Cleanup m5term changes with Nate's comments.
diffstat:
1 file changed, 4 deletions(-)
util/term/term.c |4
diffs (48 lines):
diff -r 29cd33ac16cb -r 6be5ac0eb1ea
changeset 5e1863e9afa2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5e1863e9afa2
description:
Output: Verify output files are open after opening them.
diffstat:
2 files changed, 1 insertion(+), 1 deletion(-)
src/base/stats/text.cc |1 -
src/sim/serialize.cc |
I'm pretty sure that is the way it works right now, since the alpha
quiesce instruction works in a similar fashion.
Ali
On Oct 8, 2008, at 3:52 AM, Gabe Black wrote:
I'm at the point where a timer interrupt needs to wake the CPU out
of its idle thread. The idle thread uses a hlt
I just tried to compile m5 on a fc9 machine and it didn't work
We shouldn't push stable until I get that fixed...
Ali
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It's the mysql version string in compare versions. I thought I fixed
it, but I'm looking at it now...
Ali
On Oct 8, 2008, at 4:09 PM, nathan binkert wrote:
That's odd. I thought I had done that. What compiler is it? What
swig, etc?
On Wed, Oct 8, 2008 at 1:01 PM, Ali Saidi [EMAIL
changeset d8b246a665c1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d8b246a665c1
description:
Scons: Update compare_versions() to ignore trailing charecters after an
int. This is a fix for a mysql version number that includes a (E.g. 5.0.51a)
diffstat:
0 files
I just pushed a fix I wrote it and I thought I had committed it,
but apparently not.
Ali
On Oct 8, 2008, at 6:18 PM, Ali Saidi wrote:
It's the mysql version string in compare versions. I thought I fixed
it, but I'm looking at it now...
Ali
On Oct 8, 2008, at 4:09 PM, nathan binkert
The hardware for m5sim.org was just updated. Sorry about the downtime,
everything that could have gone wrong did.
Ali
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I'm fairly certain you broke the O3 cpu for Alpha FS with this change.
The TLB returns an access violation on a superpage access when the
palcode does a hwrei to entSys from callpal_callsys. Something is
preventing the mode bit from being set and the call reads a stale
value resulting in
cpuId/contextId
Some other comments to throw in the mix:
How does this affect switch-over and sampling? Does each unique cpu in
the system have a different id? (e.g. If you start with two timing
cpus (0,1) and then switch to two details cpus (2,3) would you have
statistics for cpus
changeset 96614cd66f76 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=96614cd66f76
description:
BATCH: Run as, ar, and ranlib with BATCH_CMD so that they execute on
the batch hosts, not local host.
diffstat:
1 file changed, 1 insertion(+), 2 deletions(-)
SConstruct |
My last commit fixed the bug that has been plaguing the sunday
regressions for a while now. All the regressions passed but parser/x86
and I'm still pretty confident that there is something non-
deterministic in the x86 architecture code that is causing this to
happen.
Ali
On Oct 26, 2008,
I think I must be missing something. How are x86 unaligned accesses
handled now? 1 unaligned access - 3 aligned accesses that are
combined? What chops them into piece? microcode? Some other means?
The issue is that an access could span a page boundary so half of it
could be in the TLB
to the d
cache port.
Gabe
Ali Saidi wrote:
I think I must be missing something. How are x86 unaligned
accesses
handled now? 1 unaligned access - 3 aligned accesses that are
combined? What chops them into piece? microcode? Some other
means?
The issue is that an access could span
Clint,
Does this patch fix your building problem?
Thanks,
Ali
On Oct 28, 2008, at 6:13 PM, Ali Saidi wrote:
# HG changeset patch
# User Ali Saidi [EMAIL PROTECTED]
# Date 1225242801 14400
# Node ID 93eb7f6185172f31eb7bf8d6bec459a5a1d36065
# Parent b44dd45bd604fd12892de07245c060499728830b
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