[gem5-users] accessing the GEM5 101 webpages

Hi everyone, Does anyone know the backup links for the GEM5 101 links as they are down? I cannot seem to access all of them thanks ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] Re: Cache level 1 miss rate is the same with and without level 2 cache

of size 1kB. but again i just see a slight increase in the miss rate. it goes up to just 6-7%. This doesn't seem logical to me, Please be kind enough to explain to me as to why the low cache miss rate. Thanks On Thu, 22 Oct 2020 at 20:32, Eliot Moss wrote: > On 10/22/2020 1:26 PM, Muhammad Aa

[gem5-users] Re: Cache level 1 miss rate is the same with and without level 2 cache

On Thu, Oct 22, 2020 at 1:01 PM Muhammad Aamir via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi everyone, >> >> I have noticed that the stat: >> "system.cpu.dcache.overall_miss_rate::total" is the same if I only use 1 >> level of cache or u

[gem5-users] Cache level 1 miss rate is the same with and without level 2 cache

Hi everyone, I have noticed that the stat: "system.cpu.dcache.overall_miss_rate::total" is the same if I only use 1 level of cache or use the system with a level 2 cache. As we know it should change but it remains exactly the same, how is this possible? Would someone be kind enough to explain

[gem5-users] Cache miss rate is very low

Hi everyone, I am running the pagerank algorithm that is provided by the GAP Benchmark, and it is well known that pagerank has very bad cache utilization. But when I run the code in GEM5 on one level of cache i get a very low missrate, i.e. approximately 1% and it goes to a maximum of 3% for a

[gem5-users] Why using guest code with pseudo-instructions has less number of simulated ticks

Hi everyone, I have noticed that when I am using pseudo-instructions such as: m5_reset_stats(0,0), m5_dump_stats(0,0) and m5_rpns() i get a less number of simulated ticks compared to when I don't use them. Am particularly interested in m5_rpns() as I am measuring the time taken by a certain

[gem5-users] Cannot read from main memory with a new cpu port similar to dcacheport

Hi everyone, I have created a new cpu port which accesses the main memory and bypassing the caches when reading from memory. When I try to read from the main memory via this port, I sometimes fail to read it and it is read as a 0. This only happens when I try to read a value almost after updating

[gem5-users] Adding a new port to a CPU similar to a dcacheport

Hi everyone, i am trying to add an additional CPU port to the MinorCPU, which is similar to a dcacheport, i have tried to implement it and i have gone to a point to also edit the BaseCPU, so it can accept the new port, but when building GEM5 I get the following errors, Would someone explain to me

[gem5-users] Packet request send directly to memory without searching in cache

Hi everyone, As the title suggests, is it possible to send for a request from the CPU asking for data in the memory without looking into the caches? If yes, how can it be done. Also is it advisable to create another port like the dcacheport, and connect that port directly to the memory bus? i.e.

[gem5-users] Re: Sending more than one memory request to the memory through sendTimingReq

cpu->getPort().sendFunctional(newPkt) > ------ > *From:* Muhammad Aamir via gem5-users > *Sent:* Tuesday, August 18, 2020 1:04 PM > *To:* Jason Lowe-Power ; gem5 users mailing list < > gem5-users@gem5.org> > *Cc:* Muhammad Aamir > *

[gem5-users] Re: Sending more than one memory request to the memory through sendTimingReq

Hi Jason, I was able to solve the problem, i had set my MSHR's to 1 thus making it a blocking cache. Needed to change this parameter. Thank you for pointing out to look at my memory system. Thanks, Aamir On Tue, 18 Aug 2020 at 12:43, Muhammad Aamir wrote: > Hi Jason, > > Is there a

[gem5-users] Re: Sending more than one memory request to the memory through sendTimingReq

low (closer to memory) a > "point-of-coherence" crossbar. Also, I believe that by default that > crossbar is on 16 bytes wide, so a single cache line request could take 4 > cycles, which might be why the CPU is blocking? > > Cheers, > Jason > > On Sun, Aug 16, 202

[gem5-users] Sending more than one memory request to the memory through sendTimingReq

Hi everyone, Is it possible to send more than one memory request from the dcacheport to the memory system without stalling the pipeline. What i have seen so far is that when one memory instruction is send to the memory, then another memory request cannot be send to the memory as sendTimingReq

[gem5-users] Modifying MinorCPU to be slightly out of order for some memory instructions

ne. Should it not consider this ticks as that instruction is no longer in the inFlightInsts queue? Also, is there a way I can fix this so that it doesn't add upto the final count of ticks for those instructions? Any help would be appreciated. Thanks, Muhammad Aamir Saeed __

[gem5-users] Re: Getting tick number from C code

gt;> if you don't care to implement your own pseudo instruction. >> >> So I guess for your purposes, record the ticks at the beginning and end >> of your function. >> >> Best, >> >> Dan >> >> On Thu, Aug 6, 2020 at 1:07 PM Muhammad Aam

[gem5-users] Getting tick number from C code

be appreciated. Thanks, Muhammad Aamir Saeed ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] Re: How to use eclipse or any other IDE to debug user code in GEM5

Hi Boris, I am referring to the guest code, I can't just seem to configure GEM5 as a "remote target" in debug configuration as you have mentioned. It would be nice if you could list the steps. Thanks again, ___ gem5-users mailing list --

[gem5-users] How to use eclipse or any other IDE to debug user code in GEM5

Hi everyone, I have been following this tutorial( http://www.m5sim.org/wiki/images/b/b2/Tsinghua%27s_Presentation_for_gem5_Workshop_2012.pdf) to integrate GEM5 to the eclipse debugger but I am not able to do it, maybe because the tutorial is quite old. It would be really helpful if someone could

[gem5-users] Re: Address incrementing by 8 instead of 4 for int when SimpleMemory is configured as SPM

Here is the attached disassembly code, which has been generated by the -S flag of g++ https://drive.google.com/file/d/1xyuX3-f-JShikUzhPbXJ5VmRJjOX_K3K/view?usp=sharing On 17.06.2020 19:26, Eliot Moss via gem5-users wrote: Can you show us a disassembly of your compiled code? I am wondering

[gem5-users] Re: Address incrementing by 8 instead of 4 for int when SimpleMemory is configured as SPM

Hi Bobby, In my workload, am simply calling pointer++ once, but I do not know how it automatically increments as if I am calling pointer++ twice, here is an example of a very simple version of my workload which also provides the incorrect address reading int main() { // spm address starts

[gem5-users] Address incrementing by 8 instead of 4 for int when SimpleMemory is configured as SPM

Hi again everyone, It would be really nice if someone could assist me as I've tried almost everything and I cannot figure it out. Thanks ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] Address incrementing by 8 instead of 4 for int when SimpleMemory is configured as SPM

Hi everyone, I have made a system that includes a scratchpad memory(using the class Simple Memory as SPM) at the same level as a level 2 cache. The problem that am facing is that I can read and write to it in increments of 8 rather than 4 for type int, i.e. Pointer++ gives wrong value at an

[gem5-users] Unable to find destination on system.membus while connecting a Scratchpad Memory

Hi everyone, I am trying to connect a SPM(Scratchpad memory) (SPM is derived from the class SimpleMemory) to my gem5 configuration, where the spm is at almost the same level as the cache. But when I try to read or write to it, it gives an error that the memory address is not found. I have tried

[gem5-users] Why is inst->inLSQ in MinorCPU never set to false even after it is popped from the LSQ

Hi everyone, I was going through the MinorCPU and finding how the instructions enter and leave the LSQ. And I realised that an instruction is never marked as left i.e. inst->inLSQ is always true even after lsq.popResponse(response) is called. Why is this so Also in the documentation of MinorCPU

[gem5-users] Using the REX prefix in one byte opcodes to modify the instruction to decode

Hi everyone, I am trying to add my own custom MOV instruction, and with respect to this post on stackoverflow: https://stackoverflow.com/questions/60745735/which-mov-instructions-in-the-x86-are-not-used-or-the-least-used-and-can-be-use According to the post one way to add a custom instruction

[gem5-users] How can I make my custom x86 macro op be recognized from GCC

Hi everyone, I have made a custom x86 macro op and I wish to simulate its effects but to do that I need it to be recognized in my C code(am using my custom macroop via inline assembly). but it will not compile as GCC wont recognize it as it is not a basic x86 instruction. Is there anyway e.g. by

[gem5-users] modifying x86 macroops

Hi everyone, Am trying to implement a custom macroop, using the already build in microops in the x86 architecture, the problem that I am running into is that when we define a certain macroop we have to implement it in 3 different ways. i.e. one that only uses registers (_R), one that reads one of

[gem5-users] Are the memory requests in MinorCPU LSQ request queue overlapping?

Hi everyone, With respect to the request queue in LSQ in the Minor CPU, when requests are send to the memory to access data, to they overlap i..e send one after the another in nearly concurrent cycles or they wait for one request to be send to the memory then wait for the memory to acknowledge

Re: [gem5-users] Getting the virtual address of a specific physical address in x86 se mode

ed to do this in FS mode, > you'll most likely have to write a new kernel driver for your scratchpads > (just like if they were real hardware!). > > Cheers, > Jason > > On Thu, Feb 13, 2020 at 8:40 AM Muhammad Aamir > wrote: > >> Hi everyone, >> >> I have ba

[gem5-users] Getting the virtual address of a specific physical address in x86 se mode

Hi everyone, I have basically initialized some simplememory class as a Scratchpad memories, and I intend to write to them. One way that i have figured to access them is using addresses, As I know once initialized they are assigned some virtual addresses by the pagetables, and since each virtual

[gem5-users] Getting latency of a X86 micro-op before it is Executed or runned.

Hi everyone, If I wanted to get the latency of a micro-op in X86 before it is "executed", what files or folders should I look into to get the latency. As we know they are two types of latencies associated with any micro-op or any instruction(one latency of actually executing it and the other for

Re: [gem5-users] In which format/language are the x86 macroops written

gt; please contribute anything back that you fix! You can find out more about > how to contribute here: http://new.gem5.org/contributing, and I'm happy > to help any way I can! > > Cheers, > Jason > > On Thu, Jan 23, 2020 at 8:42 AM Muhammad Aamir > wrote: > >> Hi

[gem5-users] In which format/language are the x86 macroops written

Hi everyone, I am trying to extend the x86 instruction set, and I have come across some microops written in macrops that are not the typical x86 instructions e.g rdip limm riprel. Basically, I am referring to the files located in this directory: gem5/src/arch/x86/isa/insts In which

[gem5-users] Can we use inorder-cpu(MinoCPU) with x86

Hi, According to this list, http://gem5.org/Status_Matrix, The inorderCPU(or MinorCPU) doesnot work with the x86 architecture, but according to this mailing list https://www.mail-archive.com/gem5-users@gem5.org/msg12214.html Someone was able to to use the inorderCPU(MinorCPU) for the x86

Re: [gem5-users] How to make a tightly coupled memory, with a simple Memory and Non-coherent caches.

019 at 17:30, Muhammad Aamir wrote: > Hi everyone, > This might not be a big of a challenge, but I am quite confuse on how to > get it done. > I basically want to create a TCM type of memory which is defined as > follows: > >SimpleMemory >

[gem5-users] How to make a tightly coupled memory, with a simple Memory and Non-coherent caches.

Hi everyone, This might not be a big of a challenge, but I am quite confuse on how to get it done. I basically want to create a TCM type of memory which is defined as follows: SimpleMemory ^ | CPU -->Non-coherentBus-->non-coherent-cache-->memory

Re: [gem5-users] 回复： 回复： ask for help about simulate with noncherentcahe

Hi yuan, would you please state how you were able to get rid of the "Non-coherent cache received functional snoop request" error? As I would like to know as well. Thanks On Thu, 19 Dec 2019 at 12:58, 616653241 <616653...@qq.com> wrote: > Hi, Giacomo, > Thank you very much. That is what i

[gem5-users] How to decide which one will be Masterport and Slaveport

Hi everyone, I was looking into build a simple architecture, where I have one or more Scratchpad memories connected to a noncoherentXBar, but before I even do that, how should one decide which port will be the master and which one will be the slave,any rule of thumb? In the tutorial provided by