El 30/06/17 a las 10:36, Eyad Majali escribió:
>
>
> On Friday, June 30, 2017 at 4:33:56 PM UTC+3, Emilio López wrote:
>
> Hi,
>
> El 30/06/17 a las 10:25, Eyad Majali escribió:
> > Hi
> > i created a github repo for zet6221 complete tou
Hi,
El 30/06/17 a las 10:25, Eyad Majali escribió:
> Hi
> i created a github repo for zet6221 complete touch driver for
> linux-sunxi and want to edit http://linux-sunxi.org/Touchscreen to add
> my repo there,
> thus version supports all zet62xx chips with firmwares here's the repo
>
Hi,
El 30/03/17 a las 23:48, Vinicius Maciel escribió:
> Hi,
>
> I'm calling spi_sync_transfer inside a threaded interrupt function and
> makes kernel crash.
> Threaded interrupt functions are supposed can sleep. Could be a problem
> on sun4i_spi_transfer_one
> when call
Hi,
I spotted a couple of things here on a quick look, see below
El 27/02/17 a las 18:09, Priit Laes escribió:
> Convert sun7i-a20.dtsi to new CCU driver.
>
> Signed-off-by: Priit Laes
> ---
> arch/arm/boot/dts/sun7i-a20.dtsi | 719
> +--
>
Small nitpick:
El 08/11/16 a las 13:38, Olliver Schinagl escribió:
> All internal defines in the realtek phy are with a small X,
> except MIIM_RTL8211X_CTRL1000T_MASTER. Make this more concistent
s/concistent/consistent/ both here and on the subject :)
Cheers!
Emilio
--
You received this
Hi,
El 07/03/16 a las 12:47, Boris Brezillon escribió:
(...)
>> Does SPI refer the Serial Peripheral Interface?
>>
>> If yes, then I would point out that current sun4i SPI driver doesn't
>> actually use DMA [1]
>>
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-February/411
>>
From: Emilio López emi...@elopez.com.ar
This patch adds support for 64 byte or bigger transfers on the
sun4i SPI controller. Said transfers will be performed via DMA.
Signed-off-by: Emilio López emi...@elopez.com.ar
Tested-by: Michal Suchanek hramr...@gmail.com
---
drivers/spi/spi-sun4i.c | 145
Hi Maxime, Vinod,
El 20/05/15 a las 18:17, Maxime Ripard escibió:
+static struct dma_async_tx_descriptor *
+sun4i_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf, size_t len,
+ size_t period_len, enum dma_transfer_direction dir,
+
This patch adds support for 64 byte or bigger transfers on the
sun4i SPI controller. Said transfers will be performed via DMA.
Signed-off-by: Emilio López emi...@elopez.com.ar
Tested-by: Michal Suchanek hramr...@gmail.com
---
drivers/spi/spi-sun4i.c | 140
Hi,
El 24/03/15 a las 09:34, Michal Suchanek escibió:
6) I have no idea how to bind spidev (in DT?) even if spi worked
You need to declare your device, like with a properly supported device,
except your device's driver will be a spidev. See below for an example patch
from when I tested DMA
Hi,
El 23/03/15 a las 11:19, Michal Suchanek escibió:
Hello,
I tried to load the spidev driver with the 3.4 kernel and it did .. nothing.
So I upgraded to linux 4.0rc4 and tried to convince it to boot on the
a10s olinuxino.
Problems
(...)
5) did not manage to get SPI working. I patched
Hi :)
El 10/02/15 a las 01:15, Saket Sinha escibió:
Hi,
I am interested in Improving Allwinner SoCs support on mainline
Linux as a part of GSOC-2015.
Last year a similar project was taken by Emilio -
http://www.google-melange.com/gsoc/project/details/google/gsoc2014/emilio/5673385510043648
.
Hi,
El 01/02/15 a las 07:03, Priit Laes escibió:
On Sat, 2015-01-31 at 19:58 -0300, Emilio López wrote:
This patch adds support for the DMA engine present on Allwinner A10,
A13, A10S and A20 SoCs. This engine has two kinds of channels:
normal and dedicated. The main difference is in the mode
Hi,
El 03/02/15 a las 16:39, jonsm...@gmail.com escibió:
Did you fix multiple simultaneous DMA transfers in this? And easy test
is to start jack audio. Jack will start simultaneous cyclic transfers
on both the ALSA input and output. Since cyclic transfers never end,
multiple simultaneous
Hi,
El 03/02/15 a las 17:38, FREDERIC MARTIN escibió:
On this page some links did not work:
http://linux-sunxi.org/A10
These:
* A10 Supported DDR list
http://service.awbase.com:8000/faq/index.php/A10_DDR%E5%88%97%E8%A1%A8
* A10 Supported NAND list
Hi,
El 31/01/15 a las 20:25, bruce bushby escibió:
Hi
I'm hoping a list member could offer some advice setting a UART with a
custom speed.
I was hoping to calculate the required divisor and use setserial to set
my speed (10), however both Python's pySerial and the setserial
command cause
operate simultaneously provided there is no
overlap of source or destination.
Hardware documentation can be found on A10 User Manual (section 12), A13
User Manual (section 14) and A20 User Manual (section 1.12)
Signed-off-by: Emilio López emi...@elopez.com.ar
---
(Partial?) changes from v3:
* Drop
Emilio López (1):
dma: sun4i: Add support for the DMA engine on sun[457]i SoCs
.../devicetree/bindings/dma/sun4i-dma.txt | 46 +
drivers/dma/Kconfig| 11 +
drivers/dma/Makefile |1 +
drivers/dma/sun4i-dma.c
Hi Tobias,
El 23/12/14 a las 10:28, Tobias Andresen escibió:
---
drivers/watchdog/sunxi_wdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
index b62301e..00de94b 100644
--- a/drivers/watchdog/sunxi_wdt.c
+++
Hi,
El 23/12/14 a las 18:05, tandresen1...@gmail.com escibió:
Hi,
thanks for your response. I will fix the remaining issues.
@Emilio: Do you have any news regarding audio for me?
Nothing really interesting to report; I've been improving the DMA driver
a bit and I'll get back to the audio
Hi Hans,
El 20/12/14 a las 15:27, Hans de Goede escibió:
Hi All,
There are 3 topics which I would like to cover in this mail:
1) Switching over to upstream u-boot for the linux-sunxi project
(...)
Here are some example instructions on how to build upstream u-boot for
the Cubietruck:
git
Hi,
El 21/12/14 a las 17:28, Siarhei Siamashka escibió:
On Sun, 21 Dec 2014 17:00:46 -0300
Emilio López emi...@elopez.com.ar wrote:
Hi Hans,
El 20/12/14 a las 15:27, Hans de Goede escibió:
Hi All,
There are 3 topics which I would like to cover in this mail:
1) Switching over to upstream u
El 15/09/14 a las 20:13, Julian Calaby escibió:
Hi Tim,
On Tue, Sep 16, 2014 at 6:52 AM, Tim Tisdall tisd...@gmail.com wrote:
At http://linux-sunxi.org/U-Boot#DRAM it says copy an existing file to a
filename relevant for your device and edit the entries manually but all of
those files also say
El 15/09/14 a las 20:29, Julian Calaby escibió:
Hi Emilio,
On Tue, Sep 16, 2014 at 9:22 AM, Emilio López t...@linux-sunxi.org wrote:
(...)
`fexc` in sunxi-tools (the tool behind bin2fex/fex2bin aliases) can do it.
Note that for it to work, the fex file needs to have valid values.
Ah
Hi!
El 06/09/14 a las 11:58, B.R. Oake escibió:
Hi,
I'm new to this group. I want to use analogue audio with a mainline kernel
on my Olinuxino A20, so I've been trying out the recent work of Emilio
López, Jon Smirl and others to add mainline audio support, and I'd like to
report my findings
Hi everyone,
Given that the firm pencils down date for GSoC 2014 is today, I need
to give the project a bit of formal closure. I will keep on working on
this (as well as DMA and related clocking), but it won't be as part of
GSoC any longer. For this reason, I've pushed a branch with the
current
Hi Luc,
El 18/08/14 a las 03:34, Luc Verhaegen escibió:
Now we write out a dram file for u-boot directly.
Signed-off-by: Luc Verhaegen l...@skynet.be
---
meminfo.c | 59 ---
1 files changed, 40 insertions(+), 19 deletions(-)
diff
El 18/08/14 a las 03:34, Luc Verhaegen escibió:
No functional changes.
Signed-off-by: Luc Verhaegen l...@skynet.be
---
meminfo.c | 39 +--
1 files changed, 21 insertions(+), 18 deletions(-)
diff --git a/meminfo.c b/meminfo.c
index 44d5c78..0b7bfe2
El 13/08/14 a las 13:34, jonsm...@gmail.com escibió:
Is there any way to generate a clock on a pin with the A20 other than
the two PWM units? I just need a simple, always on clock.
I need another clock because apparently you can't put I2S into slave
mode as long as MCLKEN (ie MCLK on a pin) is
Hi everyone,
Here's a status update on my GSoC project for these last two weeks; you
can find the two previous updates on the list archives[0][1]
First of all, I have started to prepare for university exams, so that
has taken some of the time I was using to work on the project. I have
not
El 24/07/14 a las 08:36, behrooz vosough escibió:
hello
I am using goodix-gt811 ctp 7 inch and i have not problem to use this
module but when i modprobe gpio-sunxi , the interrupt of my ctp disable
1- when gt811_ts is intalled and i modprobe gpio-sunxi ,this message
shown on Putty
the message is
Hi everyone,
Here's this week's update on my GSoC project; if you missed the first
issue or you want a refresher of what this is about, you can read it on
the list archives[0]
A couple of days after the last report, and with the help of Jon Smirl,
I got the hardware working on mainline
Hi,
El 10/07/14 17:39, Maxime Ripard escribió:
Lately, I have also been working on the audio part, now that I have
a working DMA driver. After implementing cyclic DMA transfers and
some clock code, and armed with a Buildroot image with mpg123 and an
OpenBSD release track[5] in mp3 format, I've
Hi everyone,
As some of you may know, I'm currently participating in Google Summer of
Code under the Linux Foundation, working on a proposal titled Improve
Allwinner SoCs support on mainline Linux. There is a great quantity of
devices out there that are powered by Allwinner processors,
Hi there,
El 01/07/14 18:47, bruce bushby escribió:
Hi
I wanted to ask if anybody has tried to build spi-sun7.c for mainline
kernels?
I followed this excellent guide:
http://will-tm.com/spi-on-the-cubieboard2/
...but the compile fails with
drivers/spi/spi-sun7i.c:30:22: fatal error:
Hi there,
El 27/06/14 08:05, Paul Jones escribió:
Hi,
If the wiki administrator is lurking here, just an FYI that the wiki is
slightly broken:
linux-sunxi.org could not send your confirmation mail. Please check your
email address for invalid characters.
I tried to send you an email through
El 17/06/14 09:45, Enrico escribió:
Il giorno martedì 17 giugno 2014 13:34:45 UTC+2, baani@gmail.com ha
scritto:
hi enrico,
are you able to fix the tvin drivers ?? can you pls send binaries
for 3.4.79 lubuntu to baani.harjeet [a] gmail.com http://gmail.com
please please
El 13/06/14 13:22, jonsm...@gmail.com escribió:
What should the clocks be?
Why are there three I2S devices?
Did I get interrupt and DMA values right?
spdif@1c21000 {
compatible = allwinner,sun7i-a20-spdif;
reg = 0x01C21000 0x20;
interrupts = 0 13 4;
clocks = apb1_gates 16;
dmas = dma 0 2, dma 0
El 13/06/14 23:55, jonsm...@gmail.com escribió:
So correct setting for codec clock is?
codec_clk: clk@01c20140 {
#clock-cells = 0;
compatible = allwinner,sun4i-a10-mod0-clk;
It does not look like a mod0 to me. User manual shows just 1 bit to gate
the clock, so it should just be a simple gate
El 12/06/14 19:11, jonsm...@gmail.com escribió:
What has replaced sw_get_ic_ver() on 3.15?
Codec code varies on every chip revision A,B,C and A10/20.
A10/A20 can be determined by the compatible string. Chip revision is
going to be trickier though, there is no direct replacement of
El 11/06/14 11:43, jonsm...@gmail.com escribió:
On Wed, Jun 11, 2014 at 10:25 AM, Chen-Yu Tsai w...@csie.org wrote:
On Wed, Jun 11, 2014 at 10:23 PM, jonsm...@gmail.com jonsm...@gmail.com wrote:
On Wed, Jun 11, 2014 at 10:17 AM, Chen-Yu Tsai w...@csie.org wrote:
On Wed, Jun 11, 2014 at 10:05
El 11/06/14 12:14, Chen-Yu Tsai escribió:
On Wed, Jun 11, 2014 at 11:11 PM, Emilio López emi...@elopez.com.ar wrote:
El 11/06/14 11:43, jonsm...@gmail.com escribió:
On Wed, Jun 11, 2014 at 10:25 AM, Chen-Yu Tsai w...@csie.org wrote:
On Wed, Jun 11, 2014 at 10:23 PM, jonsm...@gmail.com jonsm
El 11/06/14 12:23, jonsm...@gmail.com escribió:
On Wed, Jun 11, 2014 at 11:14 AM, Chen-Yu Tsai w...@csie.org wrote:
On Wed, Jun 11, 2014 at 11:11 PM, Emilio López emi...@elopez.com.ar wrote:
El 11/06/14 11:43, jonsm...@gmail.com escribió:
On Wed, Jun 11, 2014 at 10:25 AM, Chen-Yu Tsai w
El 11/06/14 12:30, jonsm...@gmail.com escribió:
On Wed, Jun 11, 2014 at 11:28 AM, Emilio López emi...@elopez.com.ar wrote:
So does this mythical DMAEngine implementation for the A20 exist?
It's under development, but yes it does :) I'll be sending a first round
of patches to the respective
El 11/06/14 14:37, jonsm...@gmail.com escribió:
On Wed, Jun 11, 2014 at 12:37 PM, Emilio López emi...@elopez.com.ar wrote:
El 11/06/14 12:30, jonsm...@gmail.com escribió:
On Wed, Jun 11, 2014 at 11:28 AM, Emilio López emi...@elopez.com.ar
wrote:
So does this mythical DMAEngine implementation
Hi Maxime,
El 24/04/14 11:22, Maxime Ripard escribió:
The Allwinner A31 has a 16 channels DMA controller that it shares with the
newer A23. Although sharing some similarities with the DMA controller of the
older Allwinner SoCs, it's significantly different, I don't expect it to be
possible to
El 12/05/14 22:12, Mike Turquette escribió:
Quoting Emilio López (2014-05-10 10:22:15)
Hi Maxime,
El 10/05/14 00:33, Maxime Ripard escribió:
Hi everyone,
This patchset fixes a few things that have been pending for quite a
while in the clock driver.
First, it removes the clk_put calls
Hi Boris,
El 15/05/14 05:55, Boris BREZILLON escribió:
Hello,
This patch series adds support for some functions provided by the PRCM
(Power/Reset/Clock Management) unit:
- AR100, AHB0 and APB0 clocks
- APB0 reset controller
(snip)
clk: sunxi: add PRCM (Power/Reset/Clock Management) clks
Hi,
El 14/05/14 08:28, Paul Jones escribió:
Hi All,
I'm trying out the new 3.15 kernel on my A13-OLinuXino, but I'm having trouble
getting usb to work.
After eventually finding the option to turn on the usb phy (Why can't usb
options be in the usb menu??) there is a clock problem. (See the
Hi Boris,
First of all, thanks for working on this :)
While reading the code below I noticed a complete lack of comments. I
think it would be good to have at least some to aid readability,
considering these clocks are poorly documented on AW's material.
El 09/05/14 08:11, Boris BREZILLON
clock compatible
Support for the USB gates and resets on A31 has been recently added
using a new compatible, so let's document it here.
Signed-off-by: Emilio López emi...@elopez.com.ar
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Hi,
El 12/05/14 16:36, Maxime Ripard escribió:
On Sat, May 10, 2014 at 02:07:07PM -0300, Emilio López wrote:
+
+ clk = clk_register_composite(NULL, clk_name,
+ parents, SUN7I_A20_GMAC_PARENTS,
+ mux-hw, clk_mux_ops,
+ NULL
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Hi Maxime,
[let's hope this email goes through as non-empty]
El 10/05/14 00:33, Maxime Ripard escribió:
Since we have a folder of our own, we can actually make use of it by splitting
the huge clock file into several sub drivers.
The gmac clock is pretty easy to deal with, since it's pretty
Hi Maxime,
El 10/05/14 00:33, Maxime Ripard escribió:
Hi everyone,
This patchset fixes a few things that have been pending for quite a
while in the clock driver.
First, it removes the clk_put calls in the clock protection
part. Since it's not really something that should be done, I guess
this
El 11/05/14 01:35, Maxime Ripard escribió:
On Sat, May 10, 2014 at 01:46:38PM -0300, Emilio López wrote:
There was probably something interesting here, but both the messages
you sent are full of empty :)
My email client decided it was cool to drop my email body on my first
email and my
Hi,
El 07/05/14 10:22, jonsm...@gmail.com escribió:
sunxi-bsp is missing support for the A20. Has it not been
implemented, or did it get broken?
Anyone have a good build system for making Cubietruck images?
A20 support on the BSP should be working, with the exception of livesuit
image
Hi,
El 06/05/14 15:51, Maxime Ripard escribió:
Hi Emilio,
On Fri, May 02, 2014 at 05:57:15PM +0200, Hans de Goede wrote:
From: Emilio López emi...@elopez.com.ar
This commit implements .determine_rate, so that our factor clocks can be
reparented when needed.
Signed-off-by: Emilio López emi
From: Emilio López t...@linux-sunxi.org
Although Hans had introduced support for TWI3 and TWI4, the functions
handling the clocks and pins were limited to only TWI0-2. Let's fix the
clock lists to include the new A20 names, as well as generalize the pin
functions to handle all 5 buses.
Reported
Hi Boris,
El 28/04/14 11:58, Boris BREZILLON escribió:
The PRCM (Power/Reset/Clock Management) unit provides several clock
devices:
- AR100 clk: used to clock the Power Management co-processor
- AHB0 clk: used to clock the AHB0 bus
- APB0 clk and gates: used to clk
Add support for these clks
El 26/04/14 02:14, Puneet B escribió:
Hi Emilio,
Can you tell how to make phonix card?.
Is there any software to make it?.
Yes, it's called PhoenixCard as I said earlier. Use Google and the wiki
to learn more. I am not familiar with it.
--
You received this message because you are
El 25/04/14 10:50, Dave McLaughlin escribió:
I think this is very possible from a suitably written custom SD boot
option but you are going to have to write your own drivers to do this.
From what I can tell, the A20 looks on the SD for a boot partition so
if you can create your own boot you
Hi Hans,
El 22/04/14 08:01, Hans de Goede escribió:
Hi All,
Here is v8 of the sunxi-mmc patch-set David Lanzendörfer and I have been
working on.
The first 2 patches are depenencies which should go in through the clk tree,
Mike can you pick these 2 up please ? :
clk: sunxi: factors:
Hi Stefan,
El 14/04/14 18:00, Stefan Monnier escribió:
The wiki page http://linux-sunxi.org/Linux_mainlining_effort
doesn't talk about cpufreq support, so I somehow assumed this support
for inherited from general ARM CPU support (for A8, A7, ...), but my
sunxi-devel build doesn't seem to have
From: Emilio López t...@linux-sunxi.org
The -Warray-bounds flag was triggering a build failure. Fix it.
Signed-off-by: Emilio López t...@linux-sunxi.org
---
drivers/media/video/sun4i_csi/device/mt9m112.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/media/video/sun4i_csi/device
From: Emilio López t...@linux-sunxi.org
This lets us specify keybindings on the fex using a [tabletkeys_para]
section.
Signed-off-by: Emilio López t...@linux-sunxi.org
---
This makes my volume keys work correctly, as the default driver mapping
doesn't match my hardware.
arch/arm/configs
Hi,
El 25/03/14 20:23, Dimitar Penev escribió:
We need 16bit wide SRAM interface so NAND flash port doesn't suit
us.
We plan to build SRAM on top of GPIO system.
The interface is going to be used sporadically for a fraction of
second,
so I guess we will be able
Hi Ian,
El vie 21 mar 2014 18:40:04 ART, Ian Campbell escribió:
As advised by Tom.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Cc: Tom Rini tr...@ti.com
---
include/configs/sunxi-common.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Hi Igor,
El 18/03/14 23:36, Igor Cardoso escribió:
Hello,
I was trying to make a bootable SD CARD for A31 from scratch but I have
a problem. A lot of places that helps build SD CARD for Allwinner
processors talk about a file called spl/sunxi-spl.bin, but that doesn't
exist on A31 folders...
Hi there,
El 19/03/14 14:14, Daniel Mosquera escribió:
Hi,
I have built the kernel directly using sun5i_defconfig, but it refuses
to boot.
I have tested with the last uboot and with the Fedora R18 uboot provided
by Hans de Goede,
and in both cases Hans' image boots but the one built with
Hi there,
El 11/03/14 00:40, Ezequiel Garcia escribió:
André,
I'm leaving the question intact for context, and adding some folks.
On Mon, Mar 10, 2014 at 8:55 PM, André Kerber aker...@ymail.com wrote:
I am sorry to disturb you because of the old stk1160 driver, but I am very
stuck and did
Hello Russell,
El 24/02/14 13:30, Russell King - ARM Linux escribió:
On Mon, Feb 24, 2014 at 05:22:43PM +0100, Maxime Ripard wrote:
Right now, AHB is an indirect child clock of the CPU clock. If that happens to
change, since the CPU clock has no other consumers declared in Linux, it would
be
Hi Russell,
El 24/02/14 21:01, Russell King - ARM Linux escribió:
Hi Emilio.
On Mon, Feb 24, 2014 at 08:38:44PM -0300, Emilio López wrote:
Why is this so? Can't a clock be left enabled while nobody has a
reference to it? I have looked around in Documentation/ (rather quickly
I must say
Hi there!
El 23/02/14 10:42, mati8...@gmail.com escribió:
Hi people,
First of all, thank you very much for all your work. =)
I'm thinking buying a laptop with a microprocessor Allwinner A20. There is not
much information. Only this: http://www.kanjitech.com.ar/productos/display/157
Comes
Hi,
Ok. Thanks for confirm it.
There is much confusion among Allwinner and Wondermedia?.
Vendors say allwinner A20. But I can never know.. I can confirm from android?
It's not uncommon for the chinese to mislabel the contents of their
products. For example, Luc bought an A13 tablet some time
El 07/02/14 16:24, Maxime Ripard escribió:
On Mon, Feb 03, 2014 at 09:51:36AM +0800, Chen-Yu Tsai wrote:
Hi everyone,
This is v4 of the clock node renaming patch series, which renames
the clock nodes in sunxi dts to conform to device tree naming
conventions, i.e. clk@N. Dummy clocks that will
El 05/02/14 10:05, Maxime Ripard escribió:
The A31 has a slightly different PLL6 clock. Add support for this new clock in
our driver.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Taken via sunxi-clk-for-mike.
Thanks!
Emilio
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You received this message because you are
El 10/02/14 16:47, Maxime Ripard escribió:
Hi Chen-Yu,
On Mon, Feb 10, 2014 at 06:35:46PM +0800, Chen-Yu Tsai wrote:
Hi,
This is the v4 of the remaining Allwinner A20 GMAC glue layer patches.
The stmmac driver changes have been merged through net-next. The
remaining bits are clock and DT
Hi,
El 12/02/14 02:30, Dave McLaughlin escribió:
Hopefully this is the right place to post this as I have been tearing
out what little hair I have left with this.
I have an Olimex-A20 board and the Linux kernel boots ok but Android
fails to boot completely and I see this in the Logcat ouput.
Hi Maxime,
El 29/01/14 08:10, Maxime Ripard escribió:
The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
SoCs.
It supports DMA, but the driver only does PIO for now, and DMA will be
supported eventually.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Hi Hans,
El 22/01/14 18:36, Hans de Goede escribió:
The usb-clk register is special in that it not only contains clk gate bits,
but also has a few reset bits. This commit adds support for this by allowing
gates type sunxi clks to also register a reset controller.
Signed-off-by: Hans de Goede
Hi,
El 09/01/14 05:52, Chen-Yu Tsai escribió:
clock-output-names is now required for most of sunxi clock nodes, to
provide the name of the corresponding clock. Add the new requirements,
exceptions, as well as examples.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Hi Hans,
2014/1/10 Hans de Goede hdego...@redhat.com:
The usb-clk register is special in that it not only contains clk gate bits,
but also has a few reset bits. This commit adds support for this by allowing
gates type sunxi clks to also register a reset controller.
Signed-off-by: Hans de
Hi Hans,
2014/1/10 Hans de Goede hdego...@redhat.com:
From: arokux aro...@gmail.com
I thought this was settled already :) You should use a real name here.
Add register definitions for the usb-clk register found on sun4i, sun5i and
sun7i SoCs.
Signed-off-by: Hans de Goede
Hi,
El 23/12/13 05:37, Chen-Yu Tsai escribió:
This commit adds the two external clock outputs available on A20 to
its device tree. A dummy fixed factor clock is also added to serve as
the first input of the clock outputs, which according to AW's A20 user
manual, is the 24MHz oscillator divided
El 23/12/13 13:43, Chen-Yu Tsai escribió:
Hi,
On Tue, Dec 24, 2013 at 12:21 AM, Emilio López emi...@elopez.com.ar wrote:
Hi,
El 23/12/13 05:37, Chen-Yu Tsai escribió:
This commit adds the two external clock outputs available on A20 to
its device tree. A dummy fixed factor clock is also
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