I could be wrong about a PSU complying with the Low Voltage Directive (LVD),
as my experience only covers EN60950 which deals with IT equipment (which
may include a PSU) rather than PSUs on their own. From an EMC point of
view, a PSU has no intrinsic function and as you say shouldn't be marked
Hello all,
I dont know what I have done to get this warning, but it keeps me bothering.
I never had the intention to place any prims on the internal plane. Does
anyone know how this can happen, or better how to find this prim. to delete
it.
* * * * * * * * * * * * * * * * * * * * * * * * * * *
Sometime then I do DRC I get an error message.
Broken-nets contraint
Net GND
Warning nets constain unpladet pads.
How do I find this unplated pads!!!
Wy must SMD-pads bee plated!!!
Any comments or suggestions??
Regards
Tommy
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To
Tommy
Do you have any of your SMD pads set as multilayer?
I have only seen this message when I made that mistake.
Bob
Tommy kesson wrote:
Sometime then I do DRC I get an error message.
Broken-nets contraint
Net GND
Warning nets constain unpladet pads.
How do I find this unplated
Hi All,
I have a request from a customer to take in their Alegro PCB files and
modify/finish work that has been started in house. I am aware of
Router Solutions but have been told it converts to 2.8. Does anybody
have practical experience as to the completeness of the conversion
and
Thank you Ian for your detailed hints. I could solve the problem. see below:
-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: Monday, August 13, 2001 1:59 PM
To: Protel EDA Forum
Subject: Re: [PEDA] DRC warns: Primitives found on Internal Planes
On 12:25 PM
Okej, perhaps... But how do I find them?
Tommy
-Ursprungligt meddelande-
Från: Bob Fearon [mailto:[EMAIL PROTECTED]]
Skickat: den 13 augusti 2001 15:55
Till: Protel EDA Forum
Ämne: Re: [PEDA] Unplated SMD-pads??
Tommy
Do you have any of your SMD pads set as multilayer?
I
-Original Message-
From: Robison Michael R CNIN [mailto:[EMAIL PROTECTED]]
Sent: 13 August 2001 15:53
To: '[EMAIL PROTECTED]'
Subject: [PEDA] multipage schematic question
but what makes me nervous is that in the last multi-sheet schematic,
in the explorer window the sub-sheets appear
They should show up on the screen as a different color ( multilayer
color) instead of top layer or bottom layer.
Tommy kesson wrote:
Okej, perhaps... But how do I find them?
Tommy
-Ursprungligt meddelande-
Fr n: Bob Fearon [mailto:[EMAIL PROTECTED]]
Skickat: den 13 augusti 2001
No cant find any. But if its a multilayer but not plated?. How can i find
this?? Okej I know the hard way, click on every pad and check propertys.
This will take hours.
Tommy
-Ursprungligt meddelande-
Från: Bob Fearon [mailto:[EMAIL PROTECTED]]
Skickat: den 13 augusti 2001 18:02
I always use Create Symbol from Sheet to create the sheet symbols. This way
it gets the right sheet name and ports and everything. Of course I
have also done the old close and forget to save thing too.
Rob
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* To post
Evan Scarborough wrote:
I get these naughty bits too using the same process and I see them in many
Protel generated gerber files from other designers.
It seems to me that the auto-router leaves extra line segments after
cleanup (and it seems to be worse if the routing grid and the
They do not go away. I brought this up to Protel when they released SPK6,
that's when I noticed it. I would auto route a board and when finished hit
unroute and it would leave floaters in different spots across the board. At
first I thought it was just a fluke but I tried it again same thing, I
hi everybody,
well, i'm not having a banner day here. somebody else here needs
to look at a pcb of mine in protel. since i'm using ddb's (it was either
ddb's or not be able to read the footprints libraries) of course, there
is no actual powsup.pcb. so i emailed him a 20MB ddb.
we're still
have you tried to repair the data base?
Ted
-Original Message-
From: Robison Michael R CNIN [mailto:[EMAIL PROTECTED]]
Sent: Monday, August 13, 2001 2:54 PM
To: 'Protel EDA Forum'
Subject: [PEDA] ddb transfer failure ??
hi everybody,
well, i'm not having a banner day here. somebody
[EMAIL PROTECTED] wrote:
Hello all,
I dont know what I have done to get this warning, but it keeps me bothering.
I never had the intention to place any prims on the internal plane. Does
anyone know how this can happen, or better how to find this prim. to delete
it.
Make sure the
I've seen this happen with both Multilayer and top only SMD...just happened
to me yesterday...
Best way to find it is to look at the report (menu - Reports - Board
Information - then generate the report by setting to all). You'll see a
heading for non-plated hole sizes like so:
Non-Plated
Warning
Could not process message with given Content-Type:
multipart/mixed; boundary=#DM587985656#
Robison Michael R CNIN wrote:
it isn't broke on my system... ivan just can't open it on his
machine. like i said, since i can't send him an actual powsup.pcb,
i sent him the whole darned ddb. maybe thats not the way to move
a job from one pc to another, but thats the method i tried,
thanks brad,
i sent it over the intranet and i believe they've got that running at
100MB, so no, i didn't zip the file.
and i guess i should also have stated that this is exactly the same
version of protel that i am using... in fact its coming off the same
cd that i used. (don't be thinking
The problem could be the email system not transferring the *.ddb file correctly,
specially
if it goes through different servers in the system. The file type is probably
unknown.
Try zipping the ddb, if that doesnt work, zip and FTP it.
libraries was what i was thinking too, and it still could be that. to
be honest, i'm a configuration pig. i've got several jobs in this ddb,
and i'm almost positive that some of the jobs call libraries from
another ddb. but the job i wanted him to see used no libraries. i
just brute-force
Mike,
as more of the story comes out here I have a new suggestion. Since
Ivan is a mechanical guy, why not just export the PCB to ACAD DWG or DXF
format, export it and email it to him. He can open it in ACAD and make much
faster and more precise measurements. This is what I do to transfer
Hi,
I use 256 pin DSP BGA's and have been there and got the hat and
shirt!! Call me and I will be happy to explain the different ways to solve
your problems.
R. Gordon Price
Director of Research Engineering
Loronix Indormation Systems, Inc.
Del Mar CA
(858) 523-9424
-Original
What is the ball pitch? There are ways to play with both track, via, and
ball size to route the board with lots of room left to run tracks from out
side the BGA. Is the ball grid causing you to go to the 10 layer count? what
size vias are you using, what size tracks? If the ball grid has a lage
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