I'm looking forward to the PCB conference that's coming soon to see if the
new router will work better. Protel is supposed to be showing something.
Tony
> -Original Message-
> From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]On
> Behalf Of Jon Elson
> Sent: Friday, March 15, 2002 12:31
On 12:20 PM 15/03/2002 -0800, Dwight said:
>Ian, it's already there - 2001/02/09, summary is "Client: If document tabs
>exceed window width, they become unreliable"
I think I have been doing too much lately - brain is becoming increasingly
frazzled.
Ian
* * * * * * * * * * * * * * * * * * * * *
"Cobbe,John" wrote:
> Hi Kiernan
> You will not be able to route on the internal plane layers.
There is a way to do this. You can define a new split plane region
for every net you will route on the plane. If there are just a few nets
left to route, and they won't mind a lot of extra capacitanc
An option that would help in this regard (not in remembering to do it,
though!) would be to have an "Open read only" command/facility. Access has
this. In the Open dialog box, adjacent to the Open button is a drop-down
that includes "Open read-only" and "Open exclusive".
This would get around t
Ian, it's already there - 2001/02/09, summary is "Client: If document tabs
exceed window width, they become unreliable"
> -Original Message-
> From: Ian Wilson [mailto:[EMAIL PROTECTED]]
> Sent: Friday, March 15, 2002 1:57 AM
>
> On 08:55 AM 15/03/2002 +0100, [EMAIL PROTECTED] said:
>
> >
I'm doing a power supply with a hard-wired plug & switch. What type of pads
should I use so I can "wire" these parts on an internal layer, in order to
satisfy the netlist?
Sean James
PCB Designer
Telecast Fiber Systems
102 Grove Street
Worcester, MA 01603
TEL 508-754-4858 x33
FAX 413-541-6170
- Original Message -
From: "Bob Jones" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Friday, March 15, 2002 11:43 AM
Subject: Re: [PEDA] Limitations on InternalPlane layers
>
> - Original Message -
> From: <[EMAIL PROTECTED]>
> To: "Protel EDA Forum" <[EMA
Kiernan,
>I'm still on my first PCB under P99SE. I need to add quite a few extra
routes,
>but the PCB is really dense. Can I route these on the InternalPlane
layers?
As the following text shows that you are talking about plane layers, I
would strongly discourage you to do so, though it technica
Rene,
>The update design has spurious errors. It may happen that changing
>a string ( 10k to 100k) in the schematic, leads to a hole bunch
>of actions during update design. Quite often remove a connection
>and redo the same connection. This appears to be some propagated
>errors. The probability
Thanks to all the folks who suggested setting the "read-only" file
attribute. I already knew I could do this, but I usually forget to do it
until after I have opened the file, then it's too late!
Just one more thing I have to keep track of, that I shouldn't have to keep
track of...
Best regards
Hi, Kiernan;
Using Mid Layers with Polygon Pours and routed tracks works fairly well.
Obviously, breaks in the Internal Plane can wreak havoc with controlled-
impedance traces, switching-supply circuitry and the like, so it's good
to confine this approach to areas where Plane continuity isn't cri
> > I've got more "effective" MIPS,
> >MOPS, TFLOPS, etc. and a better pattern recognizer than a computer.
>
> Don't count on that lasting forever. Moore's law, after all. Sure, switch
> density will reach a limit, but then there are three dimensions, and the
> problem with AI now is not really
Hi Kiernan
You will not be able to route on the internal plane layers.
Any primitives added will simply be voids in the copper
Generally used only if you want to avoid parasitic capacitance on adjacent
layer tracks.
I would use standard route layers and pour ground fill when done.
The polygon reli
I'm still on my first PCB under P99SE. I need to add quite a few extra routes,
but the PCB is really dense. Can I route these on the InternalPlane layers?
Should I have used Polygon pours on ordinary layers instead? If I am allowed to
use the plane layers, then how can I tell whether I'm going
It took a while until I realized that JP1_? doesn't make unique
identifiers when annotating. Strange, I got JP1_1 .. JP1_4 twice.
While the schematic lists them twice in the component list, the
pcbeditor does not.
The pcbeditor got the habit of interrupting 'place track'.
Meaning 'pt' & leftmou
>
>
>
>Just guessing, I think the most accomodating thing to do for footprints
>would be:
>1) Allow underscores
>2) Allow lowercase and uppercase
>3) Be case insensitive (uppercase and lowercase evaluate the same)
>4) Don't allow spaces in the name
>
>This would allow those folks who want to u
Matt
for there seames to only silence to your question here my coments and
thoughts
< -- snip -- >
>
> I'm wondering, too... Are there any other repositories for shared
> libraries or such for components and footprints? More importantly, if not,
> are folks out there interested
On 08:55 AM 15/03/2002 +0100, [EMAIL PROTECTED] said:
>I don't know of any fix, but this also is a known, old bug. Is it on the
>bug list already, Ian and Abdul?
>
>Regards,
>
>Gisbert
No not yet...
If someone wants to fill make a really nice cut-and-pastable summary I will
add it.
To really
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