Re: [PEDA] question about connectors and PCB manufacturers

2002-12-19 Thread Anand Kulkarni
I've been able to explain well ... One more concern : I plan to have 16 such connector-cable pairs on my board ... do you anticipate any problems with this arrangement ? please do reply , thanks very much best regards Anand Kulkarni -- On Thu, 19 Dec 2002 11:32:43 Bagotronix Tec

[PEDA] question about connectors and PCB manufacturers

2002-12-19 Thread Anand Kulkarni
vertically aligned holes. Again the holes have to be perfectly aligned. Also , the pads have to be prefectly aligned. Is this "alignment" something that I can expect the PCB manufacturer to easily achieve ? Please do reply with your suggestions, thanks very much, reg

[PEDA] what do these acronyms mean ?

2002-11-20 Thread Anand Kulkarni
Hi, I think this may appear silly to a lot of people but I don't know the meaning of these abbreviations that I came across on a Plastic Leaded Chip Carrier (PLCC) part description page on the XILINX website . The package being PLCC-44. 1) PLCS 2) BSC please do reply thanks very much regards

[PEDA] question about new footprint in PROTEL

2002-11-19 Thread Anand Kulkarni
Hi everybody, Is the "new component wizard " the only way to go about creating a new component footprint in PROTEL or is there a way by which you can do it yourself (without using the wizard)? please do reply, thanks and regards Anan

[PEDA] question about ground and power planes to be used on VIRTEX FPGA board ...

2002-11-19 Thread Anand Kulkarni
und and power planes ? I'd really appreciate any suggestions... thanks and regards Anand Kulkarni * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.

[PEDA] general question about connectors : thru-hole versus surface mount

2002-11-05 Thread Anand Kulkarni
n one of the internal signal layers ((( and the terminating resistor must be placed somewhere in between the FPGA I/O pin and the connector pin ))) , where can I put the terminating resistor ? What is generally done in such a situation ? please do reply with your suggestions, thanks very much

[PEDA] (No Subject)

2002-11-05 Thread Anand Kulkarni
ne of the internal signal layers ((( and the terminating resistor must be placed somewhere in between the FPGA I/O pin and the connector pin ))) , where can I put the terminating resistor ? What is generally done in such a situation ? please do reply with your suggestions, thanks very much

[PEDA] autorouting question !

2002-10-12 Thread Anand Kulkarni
hen I proceed to AUTOROUTING I get a message that says : "One or more connections cannot be routed due to design rule violations" now what design rule violations are these ? Even after I've turned off all rules ? anybody with any suggestions ? please reply thanks very m

[PEDA] trouble with change layer [* key ] during manual routing

2002-10-10 Thread Anand Kulkarni
pplication. Anybody have a clue about what might be causing this. please do reply with you suggestions thanks very much Anand Kulkarni Watch a championship game with Elway or McGwire. Enter Now at http://champions

Re: [PEDA] question about layer synchronization between PCB and footprint library

2002-10-09 Thread Anand Kulkarni
there a simpler way of doing what I am trying to do ? I hope you are able to help me; I'd appreciate any suggestions , thanks very much Anand Kulkarni -- On Wed, 9 Oct 2002 16:35:41 Tony Karavidas wrote: >The xilinx FPGA has to be mounted to the outside of the board, ri

[PEDA] question about layer synchronization between PCB and footprint library

2002-10-09 Thread Anand Kulkarni
;d greatly appreciate any suggestions thanks and regards Anand Kulkarni Watch a championship game with Elway or McGwire. Enter Now at http://champions.lycos.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post

[PEDA] Question about track placement

2002-09-26 Thread Anand Kulkarni
assign a net to it. But then do I have to do this for each and every segment of that long track. I think there is a better way of doing what I want to do. I'd greatly appreciate any suggestions, please do reply, thanks and regards, Anand Kul

[PEDA] question about protel hanging on Update PCB !!!

2002-09-25 Thread Anand Kulkarni
r the second time.Perhaps some body has already faced this problem or may be I am doing something wrong. please do reply, thanks very much , Anand Kulkarni Tired of all the SPAM in your inbox? Switch to LYCOS MAIL PLUS http://www.mail.

[PEDA] (No Subject)

2002-08-26 Thread Anand Kulkarni
something similar) done before fabrication of the board ? please do reply, thanks and regards, Anand Kulkarni ___ Communicate with others using Lycos Mail for FREE! http://mail.lycos.com

[PEDA] (No Subject)

2002-07-30 Thread Anand Kulkarni
Devices and 2) Protel DXP & Xilinx Interface and the link is http://www.protel.com/resources/tutorials/index.html hope someone helps Anand Kulkarni _ Supercharge your e-mail with a 25MB Inbox, POP3 Access, No Ads and NoTaglines --> LYC