[PEDA] Antwort: router settings
Hi Mike, I have no problem with posting the reply I received from Altium to the group. I don't know why this is being made personal, anyway, it's helpful. Maybe Abd's comment gives the reason for it. But, as I learnt from this mail, there are some articles in the knowledge base I did not check before. Altium support, quote: In general you can find the reason that the Autorouter will not initialize in our Knowledge Base article #1694 (see below). If you have followed these guidelines and are still experiencing problems getting the Autorouter to start please email a copy of your file to us at [EMAIL PROTECTED] *** Item - 1694 Logged: 30-Mar-1998 Revised:12-Oct-2001 Item categories: Autorouting Products affected: Protel 98 (All Versions);99 (All Versions);99 SE (All Versions); Operating systems affected: Windows 95;98;NT; Query: Why won't my board autoroute? Details: Sometimes when attempting to route a PCB file in Advanced Route, it can remain in the Initializing shape based route pass, or stop after Initializing. Answer: Use the following points to help identify why the board will not route; 1. Check that the PCB outline has been placed on the Keep Out Layer and not a Mechanical Layer. (For example, make sure that the Keep Out Layer is used instead of Mechanical Layer 1 as these 2 layers are the same color). 2. Insure that there is some outline on the Keep Out Layer. It has been found that the outline need not be completely closed, i.e. the corners do not need to touch. Arcs are not supported in board outline on the Keepout Layer. They are ignored. This is the reason why a board outline defined by a full arc will not initialize and start routing. In the case where tracks and arcs make up the board outline, the arcs get ignored and in effect a straight line is used to close up the gap of where the arc was placed. Generally, in place of the arc there is a straight line assumed from and to the nearby tracks on the Keep out layer. 3. Enable all the layers that are needed for routing the PCB in the Design Rule » Routing Layers setup. When setting up the routing layers you will need to keep in mind that the present autorouter requires either the top or bottom layer to be enabled in the Routing Layers setup. Otherwise you will receive the error message Design Rule Error: no pads defined on any layers. Pressing OK will close down this error and it will appear to want to start autorouting by prompting you to change the routing grid to 0mil. The end result is that the autorouter will be unable to initialize. 4. Avoid using net names with hyphens, spaces; characters other than the alphabet and numbers. 5. Maintain net names less than 10 characters (pre P99SE only). 6. Maintain pad designator names to 4 characters or less (pre P99SE only). 7. In Route 98, the router requires all parts of the board to be within a 32x32 inch region from the absolute workspace origin (not the set-able current origin). Note that the coordinates on the Status bar display the distance from the set-able current origin, so if you are not sure reset the origin. To reset the origin select Edit » Origin » Reset from the menus. In Protel 99/99SE, the autorouter workspace is the same as the PCB workspace of 100x100 inch. 8. Avoid placing any polygons prior to routing. This includes split planes. 9. Polygons that are placed on the top or bottom overlay, or mechanical layers can prevent the autorouter from initializing and routing the PCB. This includes polygons that have been included in a footprint. You will need to edit the footprint and remove the polygon. 10. Locate and remove polygons that are not visible. See Item 2434 for more details. 11. Avoid placing components on a grid smaller than 1mil. It is recommended that components be aligned to a 5mil grid. On high density PCBs, too many components, tracks and other primitives placed on fractional grids (that is less than 1mil grid) can cause the autorouter to find too many contentions. A message similar to One or too many contentions have been found.. The only remedy to this situation is to place components and any routed tracks on at least 1mil grid. 12. Avoid placing tracks, arcs, etc on the multilayer. The router fails to start when it finds primitives other than pads/vias on the multilayer. 13. Check the PCB against the maximum capabilities of the autorouter listed in Item 665. This includes the number of components, pins, etc. * You can access our Knowledge Base at http://www.protel.com/kb/default.asp. There are a number of articles that focus on the Protel Autorouter and its use. End quote. Regards, Gisbert Auge N.A.T. GmbH Mike Ingle
Re: [PEDA] Database Repair
Re: [PEDA] Multiple Subcircuits
Re: [PEDA] Multiple Subcircuits
I found it easy to do it in PCB. Just layout one cell, then cut paste the cell's tracks vias to the next cell, the nets will rename themselves as long as you have a good netlist. Of course, PCAD was easier to do this. Sean James PCB Designer Telecast Fiber Systems, Inc. 102 Grove Street Worcester, MA 01605 (TEL) 508.754.4858 x33 (FAX) 413.541.6170 - Original Message - From: Dave Babcock [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, November 27, 2001 6:53 AM Subject: [PEDA] Multiple Subcircuits Hello! I have a PCB I am designing that I want to duplicate a subcircuit 64 times. I want to be able to layout the subcircuit once in PCB and then make an array of this subcircuit. Can I do this from the schematic or in the PCB? Any help is appreciated Dave Babcock Cardinal Components Wayne, NJ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Pin gate swapping
Re: [PEDA] connector footprint
I all ready have the footprint I need, but thanks for the offer! Tim -Original Message- From: Brian Guralnick [mailto:[EMAIL PROTECTED]] Sent: Monday, November 26, 2001 5:16 PM To: Protel EDA Forum Subject: Re: [PEDA] connector footprint I have for the Right Angle Mini-Din5 - used for audio s-video. Brian Guralnick - Original Message - From: Tim Fifield [EMAIL PROTECTED] To: Protel EDA Form [EMAIL PROTECTED] Sent: Monday, November 26, 2001 11:44 AM Subject: [PEDA] connector footprint | Does anybody have a 99SE footprint for a Standard Circular DIN 5 Pin | Receptacle, Right angle PCB mount? | | Specifically, the part is SDS-50J from CUI Stack. www.cuistack.com | | | Tim Fifield | | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Vias trace length
Re: [PEDA] Multiple Subcircuits
At 10:38 PM 11/27/01 +1000, robi artwork wrote: PCB-Circuit - Duplication can only be done within the PCB-Package. You simply select, copy paste. If you ask me - don't do it Your board manufacture should have proper software to do these things - and - he also knows the panel size and the router bit he's using to separate the individual pcb's, when penalizing. Panelizing, unless they are planning to charge extra :-) Robi misunderstood the question, which is about a subcircuit, not panelized identtical boards. Ths original question from Dave Babcock: I have a PCB I am designing that I want to duplicate a subcircuit 64 times. I want to be able to layout the subcircuit once in PCB and then make an array of this subcircuit. Can I do this from the schematic or in the PCB? Any help is appreciated There are a number of ways to do this. The only other response which has been made as I write this described how to duplicate the track but not the components themselves. You could simply select the components from one section and copy and paste them, using Paste Array. The problem is that the components will be renamed when copied, and the new names will not be what you want, probably. I recommend using partnames that can be readily edited to unique names for each section, both in PCB and in Schematic. For example, assume that a section has no more than ten of each type of part class designator, i.e., R,C,U, etc. You could name two resistors in the first section R010 and R011, in the second R020 and R021, etc., up to R640 and R641. You want to keep the designators short to make it easy to keep them readable. If you consider that desireable. Make your first section on the schematic, synchronize it to the PCB, and arrange the parts for it and route them. Get it right at this point, it will be a big pain to change it later, every change will be multiplied by 64! Once you have your section, carefully planned so that when multiplied up it is going to fit, and use the paste array tools to multiply it by 64, *keeping the component reference designators the same*. Unselect it and then select each section in turn, globally editing selected components to give them the section's designator prefix and then dEselect All. (With the designator scheme I gave, I would name the original parts RXX0, RXX1, etc. Then I would edit each section to substitute the section number for XX.) It would be possible to write a utility which would automate this process. With 64 sections, I'd be tempted (I haven't done this for a while, and I would not be surprised if someone will pop in with the information that the utility exists, either in the Protel system or externally, that will handle the designator renaming problem automatically. I don't have time to check at the moment...) Now, your original schematic has the XX parts. Using a similar process in the Schematic, multiply up your section schematic and edit each section to give it the same reference designators as you used on the PCB. There are some tools, including the automatic annotation functions, which may ease this process. Update the PCB from the Schematic. Then dEselect All and select all the copper (track, vias, free pads, arcs, fills) in your first section. Copy it to each section, setting a reference point on a component pad easy to identify. (You might also be able to do an array paste on the copper as well, I haven't done it that way.) The copper will normally take on the proper nets, unless you have made an error in copying either the schematic or the PCB sections. Delete the stepping reference pads on the mech layer if you used them and have not already deleted them. Done. I haven't done a big array for a while, so, as I mentioned, I will not be at all surprised to find that it has become easier. However, the process as I described it took perhaps half as long to describe as it would have taken to do it for 64 sections, not including the time to design the individual section. The time will not increase with an increased number of parts, only with an increased number of sections, because of the renaming time. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Routines
Re: [PEDA] Multiple Subcircuits
Hey guys: Can't you panelize the PCB in CAMtastic? Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Abd ul-Rahman Lomax [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, November 27, 2001 10:26 AM Subject: Re: [PEDA] Multiple Subcircuits At 10:38 PM 11/27/01 +1000, robi artwork wrote: PCB-Circuit - Duplication can only be done within the PCB-Package. You simply select, copy paste. If you ask me - don't do it Your board manufacture should have proper software to do these things - and - he also knows the panel size and the router bit he's using to separate the individual pcb's, when penalizing. Panelizing, unless they are planning to charge extra :-) Robi misunderstood the question, which is about a subcircuit, not panelized identtical boards. Ths original question from Dave Babcock: I have a PCB I am designing that I want to duplicate a subcircuit 64 times. I want to be able to layout the subcircuit once in PCB and then make an array of this subcircuit. Can I do this from the schematic or in the PCB? Any help is appreciated There are a number of ways to do this. The only other response which has been made as I write this described how to duplicate the track but not the components themselves. You could simply select the components from one section and copy and paste them, using Paste Array. The problem is that the components will be renamed when copied, and the new names will not be what you want, probably. I recommend using partnames that can be readily edited to unique names for each section, both in PCB and in Schematic. For example, assume that a section has no more than ten of each type of part class designator, i.e., R,C,U, etc. You could name two resistors in the first section R010 and R011, in the second R020 and R021, etc., up to R640 and R641. You want to keep the designators short to make it easy to keep them readable. If you consider that desireable. Make your first section on the schematic, synchronize it to the PCB, and arrange the parts for it and route them. Get it right at this point, it will be a big pain to change it later, every change will be multiplied by 64! Once you have your section, carefully planned so that when multiplied up it is going to fit, and use the paste array tools to multiply it by 64, *keeping the component reference designators the same*. Unselect it and then select each section in turn, globally editing selected components to give them the section's designator prefix and then dEselect All. (With the designator scheme I gave, I would name the original parts RXX0, RXX1, etc. Then I would edit each section to substitute the section number for XX.) It would be possible to write a utility which would automate this process. With 64 sections, I'd be tempted (I haven't done this for a while, and I would not be surprised if someone will pop in with the information that the utility exists, either in the Protel system or externally, that will handle the designator renaming problem automatically. I don't have time to check at the moment...) Now, your original schematic has the XX parts. Using a similar process in the Schematic, multiply up your section schematic and edit each section to give it the same reference designators as you used on the PCB. There are some tools, including the automatic annotation functions, which may ease this process. Update the PCB from the Schematic. Then dEselect All and select all the copper (track, vias, free pads, arcs, fills) in your first section. Copy it to each section, setting a reference point on a component pad easy to identify. (You might also be able to do an array paste on the copper as well, I haven't done it that way.) The copper will normally take on the proper nets, unless you have made an error in copying either the schematic or the PCB sections. Delete the stepping reference pads on the mech layer if you used them and have not already deleted them. Done. I haven't done a big array for a while, so, as I mentioned, I will not be at all surprised to find that it has become easier. However, the process as I described it took perhaps half as long to describe as it would have taken to do it for 64 sections, not including the time to design the individual section. The time will not increase with an increased number of parts, only with an increased number of sections, because of the renaming time. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: *
Re: [PEDA] Vias trace length
Is there any way to get Protel to add vias to an overall trace length? Ex. A via going from top to bottom thru an .062 board would add .062 to a total trace length (PCAD/ACCEL does this). Sean, I don't think .062 inch for any digital signal under 500 mhz makes any difference. The actual capacitance of the via will pose more of a problem than the trace length. Actual measurements made by Bill Brooks www.ultracad.com and contributing editor to PCD magazine shows no relevant impedance changes with vias placed in a trace. There are little hic-cups in the impedance but it really doesn't change much. I wish protel would give me a calculation of the capacitance with the via included. A trace length is irrelevant unless it approaches a critical length for the signal, but loss can become a bigger factor. Question; Why don't you use Acell PCAD?personally I think it sucks Mike Reagan EDSI Frederick MD * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Schematic driven PCB Layout
I want to use the PCBLayoutDirective, so that I can set up design rules from the schematic. I've never used it before, but I've figured out how to use them, and transfer them to the PCB, but why won't Protel let me edit the track, or via width to less than 1mm...I can't have 1mm tracks everywhere. Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic driven PCB Layout
Still playing with this, I discovered that it works if your PCB is set to imperial, but not metric. It seems that the schematic editor can only use imperial measurements..well it seems like that to me. Anyone know how to change this, as I generally use metric!! Steve I want to use the PCBLayoutDirective, so that I can set up design rules from the schematic. I've never used it before, but I've figured out how to use them, and transfer them to the PCB, but why won't Protel let me edit the track, or via width to less than 1mm...I can't have 1mm tracks everywhere. Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Layer Specific Keep out.
Is it possible to have a layer specific keep out? I want a GND trace connecting two components, however, there is a GND polygon between the two components as well. I do not want the trace to touch the polygon. Is there a way to do this without drawing the polygon around the track? Tim * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Specific Keep out.
The simple answer to your question is yes, draw a trace on the layer, double click on the trace and then check the keepout box in the trace properties dialog box. The complex answer may receive some criticism; however, I like to take the simplistic approach to board design, either signals are the same or they are not. If the GND signal IS the same as the polygon, let them touch; If the GND signal IS NOT the same, then rename one of them! I prefer to have multiple GND signals (GND, AGND, GNDXYZ, ...) that connect at a common point (or as I otherwise may specify) rather than have a single GND running the gamut of the board that I then have to coax to behave as I desire. The program knows only what you tell it, not what you mean! David W. Gulley Destiny Designs Tim Fifield wrote: Is it possible to have a layer specific keep out? I want a GND trace connecting two components, however, there is a GND polygon between the two components as well. I do not want the trace to touch the polygon. Is there a way to do this without drawing the polygon around the track? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Vias trace length
My design is 2.5Ghz, so via length is critical. Sean James PCB Designer Telecast Fiber Systems, Inc. 102 Grove Street Worcester, MA 01605 (TEL) 508.754.4858 x33 (FAX) 413.541.6170 - Original Message - From: Mike Reagan [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, November 27, 2001 12:39 PM Subject: Re: [PEDA] Vias trace length Is there any way to get Protel to add vias to an overall trace length? Ex. A via going from top to bottom thru an .062 board would add .062 to a total trace length (PCAD/ACCEL does this). Sean, I don't think .062 inch for any digital signal under 500 mhz makes any difference. The actual capacitance of the via will pose more of a problem than the trace length. Actual measurements made by Bill Brooks www.ultracad.com and contributing editor to PCD magazine shows no relevant impedance changes with vias placed in a trace. There are little hic-cups in the impedance but it really doesn't change much. I wish protel would give me a calculation of the capacitance with the via included. A trace length is irrelevant unless it approaches a critical length for the signal, but loss can become a bigger factor. Question; Why don't you use Acell PCAD?personally I think it sucks Mike Reagan EDSI Frederick MD * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel Crashes
I too use a Compaq, although not the same as yours, and get maybe 2-5 lock-ups per week. I don't think they are Protel (Altium, whatever) related. I think they may be memory leaks or hardware related. Today, as a matter of fact I've downloaded a program called Memokit from MacAfee, suppose to improve memory leaks and memory performance and all that good stuff. I'll try to keep you posted. - Original Message - From: Jeff Adolphs [EMAIL PROTECTED] To: Protel EDA Forum (E-mail) [EMAIL PROTECTED] Sent: Monday, November 26, 2001 3:19 PM Subject: [PEDA] Protel Crashes Hello! I have had extended RAM removed from my computer thinking the RAM was bad. Computer is Compaq Ipaq, now with 64 meg of RAM, W2K. Day One: no computer crashes. Day Two: three Protel 99SE crashes. All three gave an error window starting with something like: Access violation at address 00444C65 in module 'Client99... All three crashes were in a span of 5 1/2 hours (10:15 AM EST, 11:15 AM EST, and 3:00 PM EST). Question: Could the 3 Protel 99SE crashes be from running with only 64 meg of RAM, Protel needs reloaded from numerous crashes with bad extended RAM, or other hardware problems suspected? Any guesses? Thank You! Jeff * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Vias trace length
At 12:39 PM 11/27/01 -0500, Mike Reagan wrote: Is there any way to get Protel to add vias to an overall trace length? Ex. A via going from top to bottom thru an .062 board would add .062 to a total trace length (PCAD/ACCEL does this). I don't think that Protel will do this (though I would not consider it beyond the realm of possibilities, particularly with the Signal Integrity tool -- but I don't know). However, you can readily count the number of vias in a net by any of various means. For example, select them with a global edit keyed on net; the global edit warning dialog will report the number of vias being changed, which is one less than the total number. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Specific Keep out.
At 02:31 PM 11/27/01 -0400, Tim Fifield wrote: Is it possible to have a layer specific keep out? I want a GND trace connecting two components, however, there is a GND polygon between the two components as well. I do not want the trace to touch the polygon. Is there a way to do this without drawing the polygon around the track? Two possible ways. I haven't used it much, but you can set the polygon to *not* pour over same net. You can also draw a thin track around the trace and give it the keepout attribute. (In the track edit dialog, not by putting it on the keepout layer). This will cause the polygon to keep away from the track even if it would otherwise pour over it. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Vias trace length
Sean. Cant say that I have ever attempted to pass 2.5 Ghz thru a via. We design our boards so the high speed stuff never passes thru vias. If you need to use them for High Speed then I would recommend using blind and buried vias since they inhibit much less capacitive and inductive properties. Unfortunately, the effects of the vias has been mainly guess work by RF engineers. ( I know I am going to receive some heat for this) I recommend reading the article that Doug Brooks wrote ( I said Bill Brooks before) about the effects of vias on transmission lines. His data was measured from actual board designs using a TDR. But his measurements were not at 2.5 Ghz. Mike Reagan EDSI Frederick MD - Original Message - From: Sean James [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, November 27, 2001 2:41 PM Subject: Re: [PEDA] Vias trace length My design is 2.5Ghz, so via length is critical. Sean James PCB Designer Telecast Fiber Systems, Inc. 102 Grove Street Worcester, MA 01605 (TEL) 508.754.4858 x33 (FAX) 413.541.6170 - Original Message - From: Mike Reagan [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, November 27, 2001 12:39 PM Subject: Re: [PEDA] Vias trace length Is there any way to get Protel to add vias to an overall trace length? Ex. A via going from top to bottom thru an .062 board would add .062 to a total trace length (PCAD/ACCEL does this). Sean, I don't think .062 inch for any digital signal under 500 mhz makes any difference. The actual capacitance of the via will pose more of a problem than the trace length. Actual measurements made by Bill Brooks www.ultracad.com and contributing editor to PCD magazine shows no relevant impedance changes with vias placed in a trace. There are little hic-cups in the impedance but it really doesn't change much. I wish protel would give me a calculation of the capacitance with the via included. A trace length is irrelevant unless it approaches a critical length for the signal, but loss can become a bigger factor. Question; Why don't you use Acell PCAD?personally I think it sucks Mike Reagan EDSI Frederick MD * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel Crashes
Jeff Adolphs wrote: Thanks to all for all the advise!! My latest theroy is that the extended RAM module was indeed bad. AutoCAD 2000 is running good without the RAM module. I am assuming current Protel projects may have had the Databases corrupted (when the bad RAM card was in place) and why I continue to get Protel crashes (although I haven't worked on Protel since using Database repair). At this point I have been able to get work done in all software programs. Time will tell whether I have other issues involved and I will keep the info from the group in mind. Whew! Having worked on a number of mini-mainframe systems over the years (when they were king) and having gotten used to having the computer stop rather than blundering on destroying data in hidden ways, this is really intolerable! It is totally apalling that modern computers don't even have parity in most cases, no less ECC memory. I guess there are server-grade motherboards that do have these features. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Routines
There are a few here: http://groups.yahoo.com/group/protel-users/files/ -Original Message- From: Sean James [mailto:[EMAIL PROTECTED]] Sent: Wednesday, 28 November 2001 2:53 AM To: Protel EDA Forum Subject: [PEDA] Routines Is there an archive or FTP site that has home-grown routines for Protel? Sean James PCB Designer Telecast Fiber Systems, Inc. 102 Grove Street Worcester, MA 01605 (TEL) 508.754.4858 x33 (FAX) 413.541.6170 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Corrupted Protel 99 SE SP6 Installation
At 04:08 PM 27/11/01 -0800, you wrote: I am unable to open a Database file with Protel 99 SE with SP6. When I try to open one, the program gives me the New Design Database dialog. This installation on my computer used to work. I have tried removing and reinstalling Protel 99 SE and Service Pack 6 without success. I disabled my virus checking software during the install. I am running Windows 2000 with SP2. Are there any hidden registry settings I need to be aware of? Any hints would be appreciated. Thanks, Douglas Douglas - this has come up before and I think there is one or more KB article(s) on the Protel www site on this problem. I have seen the p KB item 1985 is one candidate - do you use apostrophe's in any folder/file names? Also, I am not sure but I seem to recall that the MDAC problem can have this or similar effect. Search for MDAC on the Protel KB. Basic issue is that the MS database drivers have been overwritten by some other program/installer. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Vias trace length
If you want to take the guesswork out of microwave (or in general above Gigahertz ) circuits, download Sonnet Lite (free license tied to machine hard drive) or Microwave Office (30day trial) . They both do 3d EM simulations using a method of moments (finite element analisys ) of planar structures such as microstrips, striplines, circuit traces, vias etc up to the 100 GHz range with accurate results since they compute current flow distributions rather than rely on approximate models. Best Regards, Matt Tudor, MSEE- RF Design Consulting Gigahertz Electronics http://www.gigahertzelectronics.com -Original Message- From: Mike Reagan [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Date: Tuesday, November 27, 2001 4:35 PM Subject: Re: [PEDA] Vias trace length Sean. Cant say that I have ever attempted to pass 2.5 Ghz thru a via. We design our boards so the high speed stuff never passes thru vias. If you need to use them for High Speed then I would recommend using blind and buried vias since they inhibit much less capacitive and inductive properties. Unfortunately, the effects of the vias has been mainly guess work by RF engineers. ( I know I am going to receive some heat for this) I recommend reading the article that Doug Brooks wrote ( I said Bill Brooks before) about the effects of vias on transmission lines. His data was measured from actual board designs using a TDR. But his measurements were not at 2.5 Ghz. Mike Reagan EDSI Frederick MD - Original Message - From: Sean James [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, November 27, 2001 2:41 PM Subject: Re: [PEDA] Vias trace length My design is 2.5Ghz, so via length is critical. Sean James PCB Designer Telecast Fiber Systems, Inc. 102 Grove Street Worcester, MA 01605 (TEL) 508.754.4858 x33 (FAX) 413.541.6170 - Original Message - From: Mike Reagan [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, November 27, 2001 12:39 PM Subject: Re: [PEDA] Vias trace length Is there any way to get Protel to add vias to an overall trace length? Ex. A via going from top to bottom thru an .062 board would add .062 to a total trace length (PCAD/ACCEL does this). Sean, I don't think .062 inch for any digital signal under 500 mhz makes any difference. The actual capacitance of the via will pose more of a problem than the trace length. Actual measurements made by Bill Brooks www.ultracad.com and contributing editor to PCD magazine shows no relevant impedance changes with vias placed in a trace. There are little hic-cups in the impedance but it really doesn't change much. I wish protel would give me a calculation of the capacitance with the via included. A trace length is irrelevant unless it approaches a critical length for the signal, but loss can become a bigger factor. Question; Why don't you use Acell PCAD?personally I think it sucks Mike Reagan EDSI Frederick MD * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel Crashes
Motherboards and BIOS settings support both ECC and non-ECC memory in most cases . It's up to whoever assembles the system to decide what to use. Best Regards, Matt Tudor, MSEE- RF Design Consulting Gigahertz Electronics http://www.gigahertzelectronics.com -Original Message- From: Jon Elson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Date: Tuesday, November 27, 2001 5:59 PM Subject: Re: [PEDA] Protel Crashes Jeff Adolphs wrote: Thanks to all for all the advise!! My latest theroy is that the extended RAM module was indeed bad. AutoCAD 2000 is running good without the RAM module. I am assuming current Protel projects may have had the Databases corrupted (when the bad RAM card was in place) and why I continue to get Protel crashes (although I haven't worked on Protel since using Database repair). At this point I have been able to get work done in all software programs. Time will tell whether I have other issues involved and I will keep the info from the group in mind. Whew! Having worked on a number of mini-mainframe systems over the years (when they were king) and having gotten used to having the computer stop rather than blundering on destroying data in hidden ways, this is really intolerable! It is totally apalling that modern computers don't even have parity in most cases, no less ECC memory. I guess there are server-grade motherboards that do have these features. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] cannot get simulation sources!?
Re: [PEDA] Import Project
At 04:42 PM 28/11/01 +1300, you wrote: Yes I know what import means What is happening is when I try to import project from right click menu I get the open database dialog box appear - therefore I can open a database but cant inport a project. Wayne Trow I did think you may have known what import was - that is why I apologised if I cast a slur your way. I think I would suspect the MDAC problem - see the Protel KB, searching on MDAC and give that a go. You don't have apostrophes in any part of the path you are using do you. There is a KB article on this as well - though it does sound like different to the problem you are seeing. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Specific Keep out.
-Ursprungliche Nachricht- Von: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Gesendet: Dienstag, 27. November 2001 21:29 An: Protel EDA Forum Betreff: Re: [PEDA] Layer Specific Keep out. At 02:31 PM 11/27/01 -0400, Tim Fifield wrote: Is it possible to have a layer specific keep out? I want a GND trace connecting two components, however, there is a GND polygon between the two components as well. I do not want the trace to touch the polygon. Is there a way to do this without drawing the polygon around the track? Two possible ways. I haven't used it much, but you can set the polygon to *not* pour over same net. You can also draw a thin track around the trace and give it the keepout attribute. (In the track edit dialog, not by putting it on the keepout layer). This will cause the polygon to keep away from the track even if it would otherwise pour over it. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA This works fine, but to add a trace with the keep- out attribute, I had to set it for each track segment. Strange enough, the global edit feature for this attribute is not allowed. I tried an old command ( Shortcut mOVE bRAKE ) to add bending points. Have you got an idea to make this better. Georg * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Specific Keep out.
..snip.. This works fine, but to add a trace with the keep- out attribute, I had to set it for each track segment. Strange enough, the global edit feature for this attribute is not allowed. I tried an old command ( Shortcut mOVE bRAKE ) to add bending points. Have you got an idea to make this better. Georg Use the Place-Keepout command - should save a bit of time. And yes, the seemingly arbitrary decisions that Protel marketing/programmers make can be exasperating - we have said it before - every component attribute should be globally settable (with the exception of the read-only fields when changing a sch symbol of course). Testpoints are the same - I got so sick of this limitation that I wrote a server to allow some semblance of global actions for testpoints. One could be done for keepouts as well I s'pose. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
