Re: [PEDA] Board warpage?

2004-07-22 Thread Igor Gmitrovic
Maybe it could be called 'Balanced Copper Coverage' rather then 'Thickness'? Or 'Track 
Density'? 'Thickness' is rather ambiguous in this case. My goal is always to take off 
as little Copper as possible. It prevents warping and improves EMC performance. It is 
good for the environment as well, especially in places where they pour the chemicals 
directly into the drain.

Igor

-Original Message-
From: Brian Guralnick [mailto:[EMAIL PROTECTED]
Sent: Thursday, 22 July 2004 10:54 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Board warpage?


The solution is Balanced Copper Thickness throughout your design.

Tom H 

Using a dummy polygon plane on each layer usually does a fine job, but, don't expect 
repair de-soldering to be easy with so much copper sinking the heat away from your 
application point.

_
Brian Guralnick


  - Original Message - 
  From: Tom Hausherr 
  To: 'Protel EDA Forum' 
  Sent: Wednesday, July 21, 2004 1:53 PM
  Subject: Re: [PEDA] Board warpage?


  Harry,

  I've seen every kind of layer stack-up imaginable.

  Board warpage is mainly caused by the uneven distribution of Copper
  Thickness. 

  If you have one plane that is out of order and call out 70um Copper
  Thickness (2OZ) your board will warp when the heat is applied either through
  fabrication lamination our plugging your assembled board into a voltage
  source.

  The solution is Balanced Copper Thickness throughout your design.

  Tom H 


  -Original Message-
  From: Harry Selfridge [mailto:[EMAIL PROTECTED]
  Sent: Wednesday, July 21, 2004 10:28 AM
  To: Protel EDA Forum
  Subject: Re: [PEDA] Board warpage?

  It isn't an odd number of PAIRS that causes problems - it is an odd number 
  of LAYERS.  There are some advanced fab techniques that can reliably 
  produce boards with odd number of planes or odd number of signal layers; 
  however, there are very few fabs I would trust to do it.  You can sometimes 
  get away with odd number stackups, but it will eventually bite you in the
  butt.

  Six layers is a common balanced stackup - provided there are an even number 
  of planes, and even number of signal layers with reasonably distributed
  copper.

  At 01:56 AM 7/21/04, you wrote:
  SNIP
  Some say that an odd number of layer pairs can cause problems, indeed we 
  had problems with 6 layers at first, though we now use 6 layers to great 
  success.  Problems with that were caused by bad process control, not the 
  design (though the manufacturer tried to blame design at the time!!)
  SNIP 






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Re: [PEDA] was Shortcuts in 99SE ?

2004-07-22 Thread John A. Ross [RSDTV]
 -Original Message-
 From: Dennis Saputelli [mailto:[EMAIL PROTECTED] 
 Sent: Thursday, July 22, 2004 4:46 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] was Shortcuts in 99SE ?
 
 
 at the risk of beating a dead horse ...
 
 i don't recall any mention in this list over the years 
 regarding the file description you can enter in the DDB for a 
 given internal file
 
 don't know how i missed this and am finding it very useful
 
 has anyone else seen this, use it, don't care about it or whatever ?

Dennis

I seen it, but I do not use it as I never found any way to print it along with the SCH 
so I prefer
to keep the data which I would have used this field for in the actual SCH.

I guess its like the summary information in the properties page of any windows file, 
right
clickpropertiessummary where there is the ability to add information to a file also, 
but not
everyone uses it :-)

John 




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Re: [PEDA] Board warpage?

2004-07-22 Thread Robison Michael R CNIN
I want to thank everybody who took the time to post on this
subject.  The posts have given me a foundation for making a
decision on whether to allow the cards to be heated to 
remove warpage.

Thanks, Michael Robison



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Re: [PEDA] Board warpage?

2004-07-22 Thread Tom Hausherr
Igor,

I agree, but when it comes to Planes you do not have a choice on Copper
Coverage and it's the Plane Layers that will cause the most damage if they
have unbalanced copper thickness coupled with unbalanced construction. 

I agree with your point on Minimal Copper Traces. That's why I do not use
the Specctra Batch Autorouter anymore. It seems as though it dumps twice
as much copper on the trace layers (and twice the number of vias). I would
rather use an Interactive Manual router (and Specctra has one) to reduce
trace length and via count.

Tom

Tom Hausherr
PCB Libraries
CEO, Director of Technology
858.592.4826 Phone
847.745.0450 Fax
E-Mail: [EMAIL PROTECTED]
Website: http://www.PCBLibraries.com  http://www.PCBYellowPages.com


-Original Message-
From: Igor Gmitrovic [mailto:[EMAIL PROTECTED] 
Sent: Wednesday, July 21, 2004 10:54 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Board warpage?

Maybe it could be called 'Balanced Copper Coverage' rather then 'Thickness'?
Or 'Track Density'? 'Thickness' is rather ambiguous in this case. My goal is
always to take off as little Copper as possible. It prevents warping and
improves EMC performance. It is good for the environment as well, especially
in places where they pour the chemicals directly into the drain.

Igor

-Original Message-
From: Brian Guralnick [mailto:[EMAIL PROTECTED]
Sent: Thursday, 22 July 2004 10:54 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Board warpage?


The solution is Balanced Copper Thickness throughout your design.

Tom H 

Using a dummy polygon plane on each layer usually does a fine job, but,
don't expect repair de-soldering to be easy with so much copper sinking the
heat away from your application point.

_
Brian Guralnick


  - Original Message - 
  From: Tom Hausherr 
  To: 'Protel EDA Forum' 
  Sent: Wednesday, July 21, 2004 1:53 PM
  Subject: Re: [PEDA] Board warpage?


  Harry,

  I've seen every kind of layer stack-up imaginable.

  Board warpage is mainly caused by the uneven distribution of Copper
  Thickness. 

  If you have one plane that is out of order and call out 70um Copper
  Thickness (2OZ) your board will warp when the heat is applied either
through
  fabrication lamination our plugging your assembled board into a voltage
  source.

  The solution is Balanced Copper Thickness throughout your design.

  Tom H 


  -Original Message-
  From: Harry Selfridge [mailto:[EMAIL PROTECTED]
  Sent: Wednesday, July 21, 2004 10:28 AM
  To: Protel EDA Forum
  Subject: Re: [PEDA] Board warpage?

  It isn't an odd number of PAIRS that causes problems - it is an odd number

  of LAYERS.  There are some advanced fab techniques that can reliably 
  produce boards with odd number of planes or odd number of signal layers; 
  however, there are very few fabs I would trust to do it.  You can
sometimes 
  get away with odd number stackups, but it will eventually bite you in the
  butt.

  Six layers is a common balanced stackup - provided there are an even
number 
  of planes, and even number of signal layers with reasonably distributed
  copper.

  At 01:56 AM 7/21/04, you wrote:
  SNIP
  Some say that an odd number of layer pairs can cause problems, indeed we 
  had problems with 6 layers at first, though we now use 6 layers to great 
  success.  Problems with that were caused by bad process control, not the 
  design (though the manufacturer tried to blame design at the time!!)
  SNIP 







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[PEDA] bug?

2004-07-22 Thread bob stephens
OK,

Here's an odd one. When I go to set design rules - or Autoroute Setup - in
2004, the parameter field is right on top of and obscured by the descriptive
text that should be next to it. For example under Clearance, the numerical
field is covered up by the words minimum clearance.

Also, the design rules don't get saved with the board, so I have to remember
to re enter them each time which is a definite PITA. I don't recall seeing
either of these problems in DXP or previous versions.

Any ideas?


Bob


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Re: [PEDA] Mouse Driver

2004-07-22 Thread JaMi Smith
Mouse . . .

Mouse . . .

Did someone say Mouse . . .

Steve,

I've always had good luck with Logitech drivers (and eliminated almost all (99.999%)
of my unexplained crashes), and personally like the feel of their Mice.

Many of their newer Mice have many additional buttons, and the nice thing here,
even though it doesn't say so on the outside of the package that they come in, all
of the buttons are programmable.

This means that you can take some of these additional buttons such as the ones
mounted on the sides that are stated to be for things like Back and Forward on
your internet browser, and reprogram them as PgUp and PgDn, which give you your
zoom in and zoom out in Protel 99 SE (yeah, it is not quite like the AutoCad
scroll in and scroll out, but it does work quite well none the less).

Don't forget that most scroll wheel Mice also have a button built into the scroll
wheel which you can also press as well as scroll, and sometimes you can re-define
this middle button (scroll button) as either PgUp or PgDn all by itself (I
know you can in Logitech Mouseware).

Unfortunately, zooming in and out the way that you describe is usually a function of
the application software itself, and unfortunately that specific function simply
does not exist in Protel 99 SE , and since we never got enough support for SP7 . . .

Although . . .

Someone mentioned a utility that does something along those lines here in this forum
not to long ago, so you might just check the archives . . .

While a longshot, you might be able to find that some video card actually
incorporates and supports such a function all on it's own simply as a part of the
hardware . . .

As a final note, such a capability would probably make for an interesting server
for someone who likes to diddle around with the SDK and would appreciate the
accolades of his (or her) fellow Protel 99 SE users (however it should zoom in or
out in very fine steps, and not just emulate pressing PgUp or PgDn 57 times, and
of course use my preferred method of centering with each zoom (don't anyone get
too upset - that last part really was a joke (see :-) ) ) . . .

Take it easy on all that Mousing around . . .

Happy 99ing (still seems the best way to go . . . ) . . .

JaMi


- Original Message -
From: [EMAIL PROTECTED]
To: [EMAIL PROTECTED]
Sent: Wednesday, July 21, 2004 11:41 AM
Subject: [PEDA] Mouse Driver


 At risk of reopening the mouse wars of yesteryear, I need to ask what's the
 best driver to install to use a Microsoft Intellipoint (Dell branded) mouse
 with Protel 99SE. I had a pretty decent setup and should have left well enough
 alone, but I tried to install a newer mouse with dual scroll wheels etc, and
 that didn't work out. I can't seem to get back to the configuration I had
 before using either the v4.1 driver I thought I was using nor the freshly
 downloaded (from microsoft.com) v5.0 drivers.

 What I'd really like, and what I thought I was getting when I bought the
 mouse, was the ability to use the scroll whele for zoom. With the way Protel
 zooms, that's all I need, and I'd never scroll at all. Just roll the wheel one way
 to zoom out till the area of interest is in view, move the mouse pointer over
 there, and roll the wheel the other way to zoom back in. Who needs scroll
 bars?

 Steve Hendrix





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Re: [PEDA] Mini DIN footprint

2004-07-22 Thread Tom Reineking
We use a circular mini-DIN 9 pin right angle connector in many of our 
products.  As an aside, it is a very robust connector due to the metal 
cross bar that prevents pins from bending regardless of how hard one 
tries to insert the plug in the wrong orientation.  Anyhow, the pins are 
supposed to be compatible with lower pin count mini-DINs.  That said, 
electromechanical drawings, footprints, and pin numbering should always 
be suspect.  I have seldom found any of it good.  Our pinout agrees with 
the manufacturer's, shock, and here it is as viewed from the component 
side (MH = mounting hole):

Plug
MH
MH MH
3  1  2   6
  7  4  5  8  9
I hope that this helps.
Cheers,
Tom
DUTTON Phil wrote:
I've been caught in the past with mini-DIN data sheets.
The data sheet showed numbering for the 'locations' of the pins rather than the pin 
numbers. Also be careful of the view that they show.
This is the numbering that I ended up with for right angle connectors (board edge 
uppermost)
3 1 2 4
5 6
and
3 1 2 5
6 4 7 8
regards,
Phil.
-Original Message-
From: Jason Morgan [mailto:[EMAIL PROTECTED]
Sent: Wednesday, 21 July 2004 6:05 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Mini DIN footprint
Sounds to me, like many things, each vendor has their own standard ;)
Honestly, I've no idea if mini-DIN has a numbering standard (though the name, DIN 
means Deutsches Insitut f r Normung, a German standards org)
What I normally do is use the numbering (or naming) that either makes most sense in my 
application or matches the chosen vendor for the component.
I've found quite often that a seemingly identical component from two manufacturers can 
me subtly mechanically different.
Choose one part from one manufacturer and specify that in the drawing.
It would be worse to use the 'standard' in the drawing then have a difference from the 
supplier, you can bet somebody some time will wire up the plug wrong, following the 
text on it.
j.
-Original Message-
From: Peder K. Hellegaard [mailto:[EMAIL PROTECTED]
Sent: 21 July 2004 06:34
To: [EMAIL PROTECTED]
Subject: [PEDA] Mini DIN footprint
Hi everyone.
Anybody who knows if there is any official standard pin numbering for the
MIN DIN sockets ?
I ask due to the fact that I have seen 3 different ways of numbering, from 3
different vendors.
Have a nice day
Peder


 



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Re: [PEDA] bug?

2004-07-22 Thread Mike Reagan
Bob

So far this answer worked for me when 2004 started to act funneee.
Delete the folder C:\Documents and Settings\yourname\Application
Data\Altium.  Then start 2004 again.  Colby at Tech support at Altium
steered me this way.  Colby is a great asset to Altium

Mike Reagan



-Original Message-
From: bob stephens [mailto:[EMAIL PROTECTED]
Sent: Thursday, July 22, 2004 9:40 AM
To: [EMAIL PROTECTED]
Subject: [PEDA] bug?


OK,

Here's an odd one. When I go to set design rules - or Autoroute Setup - in
2004, the parameter field is right on top of and obscured by the descriptive
text that should be next to it. For example under Clearance, the numerical
field is covered up by the words minimum clearance.

Also, the design rules don't get saved with the board, so I have to remember
to re enter them each time which is a definite PITA. I don't recall seeing
either of these problems in DXP or previous versions.

Any ideas?


Bob


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Re: [PEDA] Autorouting Techniques

2004-07-22 Thread Duane Foster
Thanks for the white paper Mike.

I have been curious to try the Electra autorouter ( mainly because of your 
enthusiastic plugs ), and so I read your white paper and got the demo.

I routed a small double sided board with SMD on both sides.  I was able to get 100% 
routed in 99SE using 10/10 and 12mil spacing SMD-track.  99SE router will not do my 
desired 14mil SMD-via spacing, so i manually adjusted offending vias and cleaned up.

I am trying Electra on the same layout and initially getting 94% completion and no 
adherance to any special clearance rules.

I tried using your DO file and it seems ROUTE 5 is inadequate.  Am i misunderstanding 
your intention?

I tried the basic.do file with an addition of rule pcb (clearance 12 (type 
smd_wire). I did not see any adherance to this special rule in the resulting routing.

I have tried using small grids and assigning layers to 'any' direction, with some 
improvement.

I would be encouraged with Electra if I could get 100% routing with adherance to my 
spacing rules.  Any ideas or suggestions?  Or does Electra shine on multi-layer stuff 
and this simple 2 layer board is under the Electra radar?

Duane Foster

 -Original Message-
 From: edsi [mailto:[EMAIL PROTECTED]
 Sent: Wednesday, July 21, 2004 10:40 AM
 To: Protel EDA Forum
 Subject: [PEDA] Autorouting Techniques
 
 
 Hello All,
 
 Please feel free to  visit www.konekt.com  and read my white 
 paper  on how to use the Electra Autorouter with Protel  99SE 
 and  DXP products.  I have been posting for some time now 
 that this router is one of the best products available.  I 
 was asked by  the ConnectEDA staff  to write a paper for all 
 you users that are afraid to try autorouters.   I have not 
 accepted any payment for this effort , my only interest is 
 have better design tools available and to open a new dialog 
 for Protel users.   
 
 Enjoy the article 
 
 Mike Reagan
 EDSI 
 Frederick MD



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Re: [PEDA] LED Footprints

2004-07-22 Thread Joe Sapienza
Roger,

There are many different footprints for LEDs. You need to use the one that
you plan on mounting. Or make one using the datasheet.

Joe






- Original Message - 
From: Roger Pizzatto Nunes [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Thursday, July 22, 2004 4:35 PM
Subject: [PEDA] LED Footprints


Hi,

Which is the footprint name of a normal LED? Which librarie on Protel DXP
has this type of footprint?

Thank you

Roger

  - Original Message - 
  From: Duane Foster
  To: Protel EDA Forum
  Sent: Thursday, July 22, 2004 5:18 PM
  Subject: Re: [PEDA] Autorouting Techniques


  Thanks for the white paper Mike.

  I have been curious to try the Electra autorouter ( mainly because of your
enthusiastic plugs ), and so I read your white paper and got the demo.

  I routed a small double sided board with SMD on both sides.  I was able to
get 100% routed in 99SE using 10/10 and 12mil spacing SMD-track.  99SE
router will not do my desired 14mil SMD-via spacing, so i manually adjusted
offending vias and cleaned up.

  I am trying Electra on the same layout and initially getting 94%
completion and no adherance to any special clearance rules.

  I tried using your DO file and it seems ROUTE 5 is inadequate.  Am i
misunderstanding your intention?

  I tried the basic.do file with an addition of rule pcb (clearance 12
(type smd_wire). I did not see any adherance to this special rule in the
resulting routing.

  I have tried using small grids and assigning layers to 'any' direction,
with some improvement.

  I would be encouraged with Electra if I could get 100% routing with
adherance to my spacing rules.  Any ideas or suggestions?  Or does Electra
shine on multi-layer stuff and this simple 2 layer board is under the
Electra radar?

  Duane Foster

   -Original Message-
   From: edsi [mailto:[EMAIL PROTECTED]
   Sent: Wednesday, July 21, 2004 10:40 AM
   To: Protel EDA Forum
   Subject: [PEDA] Autorouting Techniques
  
  
   Hello All,
  
   Please feel free to  visit www.konekt.com  and read my white
   paper  on how to use the Electra Autorouter with Protel  99SE
   and  DXP products.  I have been posting for some time now
   that this router is one of the best products available.  I
   was asked by  the ConnectEDA staff  to write a paper for all
   you users that are afraid to try autorouters.   I have not
   accepted any payment for this effort , my only interest is
   have better design tools available and to open a new dialog
   for Protel users.
  
   Enjoy the article
  
   Mike Reagan
   EDSI
   Frederick MD



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Re: [PEDA] bug?

2004-07-22 Thread bob stephens
Thanks Mike - and Colby. That solved the design rules not being saved
problem. Still have the overwritten text issue though.

Bob

-Original Message-
From: Mike Reagan [mailto:[EMAIL PROTECTED] 
Sent: Thursday, July 22, 2004 11:10 AM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] bug?

Bob

So far this answer worked for me when 2004 started to act funneee.
Delete the folder C:\Documents and Settings\yourname\Application
Data\Altium.  Then start 2004 again.  Colby at Tech support at Altium
steered me this way.  Colby is a great asset to Altium

Mike Reagan



-Original Message-
From: bob stephens [mailto:[EMAIL PROTECTED]
Sent: Thursday, July 22, 2004 9:40 AM
To: [EMAIL PROTECTED]
Subject: [PEDA] bug?


OK,

Here's an odd one. When I go to set design rules - or Autoroute Setup - in
2004, the parameter field is right on top of and obscured by the descriptive
text that should be next to it. For example under Clearance, the numerical
field is covered up by the words minimum clearance.

Also, the design rules don't get saved with the board, so I have to remember
to re enter them each time which is a definite PITA. I don't recall seeing
either of these problems in DXP or previous versions.

Any ideas?


Bob


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Re: [PEDA] Autorouting Techniques

2004-07-22 Thread Mike Reagan
This is a multi-part message in MIME format.
HI Duane

Before I can give an answer to all of your questionI need to know did
you follow my step by step instructions for fanning out?   I typically can
route any design ( large ones with several thousand components )  in 5
passes.   The secret is the routing channels must be kept open.  Secondly,
what is are you calling the basic do   is this the do file Protel
generates?  (DXP only).   
I would stay away from assigning directives  like any direction  this will
only complicate things by not steering the router to work for you.  Two
layer designs work as easily as multilayer as long as you have open
channels.  That is key.   On very populated tight designs I discount the
component side as a routing layer because the components are in the way.

Electra will route 100 percent, as long as your rules make sense. Take a
closer look at your rules and make sure they make sense. ie can a 10 mil
line fit inside a 8 mil gap   Let me know how I can help.  And thanks
for reading it.

Mike Reagan 


-Original Message-
From: Duane Foster [mailto:[EMAIL PROTECTED]
Sent: Thursday, July 22, 2004 4:18 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Autorouting Techniques


Thanks for the white paper Mike.

I have been curious to try the Electra autorouter ( mainly because of your
enthusiastic plugs ), and so I read your white paper and got the demo.

I routed a small double sided board with SMD on both sides.  I was able to
get 100% routed in 99SE using 10/10 and 12mil spacing SMD-track.  99SE
router will not do my desired 14mil SMD-via spacing, so i manually adjusted
offending vias and cleaned up.

I am trying Electra on the same layout and initially getting 94% completion
and no adherance to any special clearance rules.

I tried using your DO file and it seems ROUTE 5 is inadequate.  Am i
misunderstanding your intention?

I tried the basic.do file with an addition of rule pcb (clearance 12 (type
smd_wire). I did not see any adherance to this special rule in the
resulting routing.

I have tried using small grids and assigning layers to 'any' direction, with
some improvement.

I would be encouraged with Electra if I could get 100% routing with
adherance to my spacing rules.  Any ideas or suggestions?  Or does Electra
shine on multi-layer stuff and this simple 2 layer board is under the
Electra radar?

Duane Foster

 -Original Message-
 From: edsi [mailto:[EMAIL PROTECTED]
 Sent: Wednesday, July 21, 2004 10:40 AM
 To: Protel EDA Forum
 Subject: [PEDA] Autorouting Techniques
 
 
 Hello All,
 
 Please feel free to  visit www.konekt.com  and read my white 
 paper  on how to use the Electra Autorouter with Protel  99SE 
 and  DXP products.  I have been posting for some time now 
 that this router is one of the best products available.  I 
 was asked by  the ConnectEDA staff  to write a paper for all 
 you users that are afraid to try autorouters.   I have not 
 accepted any payment for this effort , my only interest is 
 have better design tools available and to open a new dialog 
 for Protel users.   
 
 Enjoy the article 
 
 Mike Reagan
 EDSI 
 Frederick MD




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Re: [PEDA] Autorouting Techniques

2004-07-22 Thread Duane Foster
thanks for your help  see below for pointed response

 -Original Message-
 From: Mike Reagan [mailto:[EMAIL PROTECTED]
 Sent: Thursday, July 22, 2004 3:08 PM
 To: 'Protel EDA Forum'
 Subject: Re: [PEDA] Autorouting Techniques
 
 
 HI Duane
 
 Before I can give an answer to all of your questionI need 
 to know did
 you follow my step by step instructions for fanning out?   I 
 typically can
 route any design ( large ones with several thousand components )  in 5
 passes.   The secret is the routing channels must be kept 
 open.  

i did not do any fan out.. i tried this on the premise that it is a simple board which 
99SE could autoroute..  this board has some 0805s and 14 pin SOICs.. are you 
recommending that i fan out the SOICs?



 Secondly,
 what is are you calling the basic do   is this the do file Protel
 generates?  (DXP only).

i am referring to a file which was installed by Electra (Basic.do).
 

  
 I would stay away from assigning directives  like any 
 direction  this will
 only complicate things by not steering the router to work for 
 you.  Two
 layer designs work as easily as multilayer as long as you 
 have open
 channels.  That is key.   On very populated tight designs I 
 discount the
 component side as a routing layer because the components are 
 in the way.

i have components on both sides?!  

Perhaps it will route if i work on the component layout.  But i still would like the 
router to follow a 12mil track-SMDpad rule and a 14mil via-SMDpad rule.
Can you illuminate how to implement these special spacing rules?  



 
 Electra will route 100 percent, as long as your rules make 
 sense. Take a
 closer look at your rules and make sure they make sense. ie 
 can a 10 mil
 line fit inside a 8 mil gap   Let me know how I can help. 
  And thanks
 for reading it.
 
 Mike Reagan 
 
 
 -Original Message-
 From: Duane Foster [mailto:[EMAIL PROTECTED]
 Sent: Thursday, July 22, 2004 4:18 PM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Autorouting Techniques
 
 
 Thanks for the white paper Mike.
 
 I have been curious to try the Electra autorouter ( mainly 
 because of your
 enthusiastic plugs ), and so I read your white paper and got the demo.
 
 I routed a small double sided board with SMD on both sides.  
 I was able to
 get 100% routed in 99SE using 10/10 and 12mil spacing SMD-track.  99SE
 router will not do my desired 14mil SMD-via spacing, so i 
 manually adjusted
 offending vias and cleaned up.
 
 I am trying Electra on the same layout and initially getting 
 94% completion
 and no adherance to any special clearance rules.
 
 I tried using your DO file and it seems ROUTE 5 is inadequate.  Am i
 misunderstanding your intention?
 
 I tried the basic.do file with an addition of rule pcb 
 (clearance 12 (type
 smd_wire). I did not see any adherance to this special rule in the
 resulting routing.
 
 I have tried using small grids and assigning layers to 'any' 
 direction, with
 some improvement.
 
 I would be encouraged with Electra if I could get 100% routing with
 adherance to my spacing rules.  Any ideas or suggestions?  Or 
 does Electra
 shine on multi-layer stuff and this simple 2 layer board is under the
 Electra radar?
 
 Duane Foster
 
  -Original Message-
  From: edsi [mailto:[EMAIL PROTECTED]
  Sent: Wednesday, July 21, 2004 10:40 AM
  To: Protel EDA Forum
  Subject: [PEDA] Autorouting Techniques
  
  
  Hello All,
  
  Please feel free to  visit www.konekt.com  and read my white 
  paper  on how to use the Electra Autorouter with Protel  99SE 
  and  DXP products.  I have been posting for some time now 
  that this router is one of the best products available.  I 
  was asked by  the ConnectEDA staff  to write a paper for all 
  you users that are afraid to try autorouters.   I have not 
  accepted any payment for this effort , my only interest is 
  have better design tools available and to open a new dialog 
  for Protel users.   
  
  Enjoy the article 
  
  Mike Reagan
  EDSI 
  Frederick MD




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Re: [PEDA] LED Footprints

2004-07-22 Thread Brian Guralnick
If you are talking about the standard T1/4, my compact library has the standard 
vertical mount  90 degree angle horizontal mount, including SOT-23 style LEDs.

http://www.proteluser.com/download/Pcb_99SE_add-on/BriansStuff/

The brians_public.txt describes the contents of the brians_public.zip
file.

_
Brian Guralnick


  - Original Message - 
  From: Joe Sapienza 
  To: Protel EDA Forum 
  Sent: Thursday, July 22, 2004 4:38 PM
  Subject: Re: [PEDA] LED Footprints


  Roger,

  There are many different footprints for LEDs. You need to use the one that
  you plan on mounting. Or make one using the datasheet.

  Joe






  - Original Message - 
  From: Roger Pizzatto Nunes [EMAIL PROTECTED]
  To: Protel EDA Forum [EMAIL PROTECTED]
  Sent: Thursday, July 22, 2004 4:35 PM
  Subject: [PEDA] LED Footprints


  Hi,

  Which is the footprint name of a normal LED? Which librarie on Protel DXP
  has this type of footprint?

  Thank you

  Roger

- Original Message - 
From: Duane Foster
To: Protel EDA Forum
Sent: Thursday, July 22, 2004 5:18 PM
Subject: Re: [PEDA] Autorouting Techniques


Thanks for the white paper Mike.

I have been curious to try the Electra autorouter ( mainly because of your
  enthusiastic plugs ), and so I read your white paper and got the demo.

I routed a small double sided board with SMD on both sides.  I was able to
  get 100% routed in 99SE using 10/10 and 12mil spacing SMD-track.  99SE
  router will not do my desired 14mil SMD-via spacing, so i manually adjusted
  offending vias and cleaned up.

I am trying Electra on the same layout and initially getting 94%
  completion and no adherance to any special clearance rules.

I tried using your DO file and it seems ROUTE 5 is inadequate.  Am i
  misunderstanding your intention?

I tried the basic.do file with an addition of rule pcb (clearance 12
  (type smd_wire). I did not see any adherance to this special rule in the
  resulting routing.

I have tried using small grids and assigning layers to 'any' direction,
  with some improvement.

I would be encouraged with Electra if I could get 100% routing with
  adherance to my spacing rules.  Any ideas or suggestions?  Or does Electra
  shine on multi-layer stuff and this simple 2 layer board is under the
  Electra radar?

Duane Foster

 -Original Message-
 From: edsi [mailto:[EMAIL PROTECTED]
 Sent: Wednesday, July 21, 2004 10:40 AM
 To: Protel EDA Forum
 Subject: [PEDA] Autorouting Techniques


 Hello All,

 Please feel free to  visit www.konekt.com  and read my white
 paper  on how to use the Electra Autorouter with Protel  99SE
 and  DXP products.  I have been posting for some time now
 that this router is one of the best products available.  I
 was asked by  the ConnectEDA staff  to write a paper for all
 you users that are afraid to try autorouters.   I have not
 accepted any payment for this effort , my only interest is
 have better design tools available and to open a new dialog
 for Protel users.

 Enjoy the article

 Mike Reagan
 EDSI
 Frederick MD



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Re: [PEDA] Autorouting Techniques

2004-07-22 Thread Mike Reagan
This is a multi-part message in MIME format.
Duane

The purpose of the article was to explore interactive routingthe
interactive part and most boring part of this is manually fanning out.  FAN
out everything,   boring and time consuming I know. but the rewards are no
post clean up and very clean routes

Just say No to the basic.do   FAN Out as I suggested, take my word for it.

If you have components on both sides and routing channels are not open, it
doesn't matter if you manually attempt to route .routing channels must
be open


For your question.  But i still would like the router to follow a 12mil
track-SMDpad rule and a 14mil via-SMDpad ruleWhat are you calling
track-SMDare you referring to the clearance to the smd pad?   Trace
widths can be controlled in Protel using net classes or identifying
individual net names in the width rules set up.   Open the DSN file using
wordpad as I suggested, and do Control F to fine  the net you assigned a
rule to. If the net rule is not changed then the design rules are not set up
in Protel.  The DSN interface is excellent to ELECTRA and Spectra.If the
design rules are set up, and there is ample clearance to push a 12 mil line
thru, ELECTRA will route it in a microsecond.  If it is not routing in
microseconds after you type in route, then the rules are in conflict.  It is
that simple correct rules, yeilds efficient routing

Mike 






-Original Message-
From: Duane Foster [mailto:[EMAIL PROTECTED]
Sent: Thursday, July 22, 2004 6:37 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Autorouting Techniques


thanks for your help  see below for pointed response

 -Original Message-
 From: Mike Reagan [mailto:[EMAIL PROTECTED]
 Sent: Thursday, July 22, 2004 3:08 PM
 To: 'Protel EDA Forum'
 Subject: Re: [PEDA] Autorouting Techniques
 
 
 HI Duane
 
 Before I can give an answer to all of your questionI need 
 to know did
 you follow my step by step instructions for fanning out?   I 
 typically can
 route any design ( large ones with several thousand components )  in 5
 passes.   The secret is the routing channels must be kept 
 open.  

i did not do any fan out.. i tried this on the premise that it is a simple
board which 99SE could autoroute..  this board has some 0805s and 14 pin
SOICs.. are you recommending that i fan out the SOICs?



 Secondly,
 what is are you calling the basic do   is this the do file Protel
 generates?  (DXP only).

i am referring to a file which was installed by Electra (Basic.do).
 

  
 I would stay away from assigning directives  like any 
 direction  this will
 only complicate things by not steering the router to work for 
 you.  Two
 layer designs work as easily as multilayer as long as you 
 have open
 channels.  That is key.   On very populated tight designs I 
 discount the
 component side as a routing layer because the components are 
 in the way.

i have components on both sides?!  

Perhaps it will route if i work on the component layout.  But i still would
like the router to follow a 12mil track-SMDpad rule and a 14mil via-SMDpad
rule.
Can you illuminate how to implement these special spacing rules?  



 
 Electra will route 100 percent, as long as your rules make 
 sense. Take a
 closer look at your rules and make sure they make sense. ie 
 can a 10 mil
 line fit inside a 8 mil gap   Let me know how I can help. 
  And thanks
 for reading it.
 
 Mike Reagan 
 
 
 -Original Message-
 From: Duane Foster [mailto:[EMAIL PROTECTED]
 Sent: Thursday, July 22, 2004 4:18 PM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Autorouting Techniques
 
 
 Thanks for the white paper Mike.
 
 I have been curious to try the Electra autorouter ( mainly 
 because of your
 enthusiastic plugs ), and so I read your white paper and got the demo.
 
 I routed a small double sided board with SMD on both sides.  
 I was able to
 get 100% routed in 99SE using 10/10 and 12mil spacing SMD-track.  99SE
 router will not do my desired 14mil SMD-via spacing, so i 
 manually adjusted
 offending vias and cleaned up.
 
 I am trying Electra on the same layout and initially getting 
 94% completion
 and no adherance to any special clearance rules.
 
 I tried using your DO file and it seems ROUTE 5 is inadequate.  Am i
 misunderstanding your intention?
 
 I tried the basic.do file with an addition of rule pcb 
 (clearance 12 (type
 smd_wire). I did not see any adherance to this special rule in the
 resulting routing.
 
 I have tried using small grids and assigning layers to 'any' 
 direction, with
 some improvement.
 
 I would be encouraged with Electra if I could get 100% routing with
 adherance to my spacing rules.  Any ideas or suggestions?  Or 
 does Electra
 shine on multi-layer stuff and this simple 2 layer board is under the
 Electra radar?
 
 Duane Foster
 
  -Original Message-
  From: edsi [mailto:[EMAIL PROTECTED]
  Sent: Wednesday, July 21, 2004 10:40 AM
  To: Protel EDA Forum
  Subject: [PEDA] 

[PEDA] SP6 not printing

2004-07-22 Thread John Girvan
Win2k Pro (SP2), 99SE, error when printing.

hey there,

we recently put SP6 on one of our machines here as we were\are running SP5.
was a new-ish machine and everything was running smoothly...

when printing a schematic we now get an 'access violation' error (ignore or
quit) and cannot print the schematic on this machine. after this u have to
close down protel and re-open and it gets ugly with access violation errors
in windows that will not go away unless u kill the client99se task.

got me stuffed!

any help appreciated.


thanks,


jjg.


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Re: [PEDA] LED Footprints

2004-07-22 Thread Roger Pizzatto Nunes
Thank you Brian.

Roger

- Original Message - 
  From: Brian Guralnick 
  To: Protel EDA Forum 
  Sent: Thursday, July 22, 2004 8:04 PM
  Subject: Re: [PEDA] LED Footprints


  If you are talking about the standard T1/4, my compact library has the standard 
vertical mount  90 degree angle horizontal mount, including SOT-23 style LEDs.

  http://www.proteluser.com/download/Pcb_99SE_add-on/BriansStuff/

  The brians_public.txt describes the contents of the brians_public.zip
  file.

  _
  Brian Guralnick


- Original Message - 
From: Joe Sapienza 
To: Protel EDA Forum 
Sent: Thursday, July 22, 2004 4:38 PM
Subject: Re: [PEDA] LED Footprints


Roger,

There are many different footprints for LEDs. You need to use the one that
you plan on mounting. Or make one using the datasheet.

Joe






- Original Message - 
From: Roger Pizzatto Nunes [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Thursday, July 22, 2004 4:35 PM
Subject: [PEDA] LED Footprints


Hi,

Which is the footprint name of a normal LED? Which librarie on Protel DXP
has this type of footprint?

Thank you

Roger

  - Original Message - 
  From: Duane Foster
  To: Protel EDA Forum
  Sent: Thursday, July 22, 2004 5:18 PM
  Subject: Re: [PEDA] Autorouting Techniques


  Thanks for the white paper Mike.

  I have been curious to try the Electra autorouter ( mainly because of your
enthusiastic plugs ), and so I read your white paper and got the demo.

  I routed a small double sided board with SMD on both sides.  I was able to
get 100% routed in 99SE using 10/10 and 12mil spacing SMD-track.  99SE
router will not do my desired 14mil SMD-via spacing, so i manually adjusted
offending vias and cleaned up.

  I am trying Electra on the same layout and initially getting 94%
completion and no adherance to any special clearance rules.

  I tried using your DO file and it seems ROUTE 5 is inadequate.  Am i
misunderstanding your intention?

  I tried the basic.do file with an addition of rule pcb (clearance 12
(type smd_wire). I did not see any adherance to this special rule in the
resulting routing.

  I have tried using small grids and assigning layers to 'any' direction,
with some improvement.

  I would be encouraged with Electra if I could get 100% routing with
adherance to my spacing rules.  Any ideas or suggestions?  Or does Electra
shine on multi-layer stuff and this simple 2 layer board is under the
Electra radar?

  Duane Foster

   -Original Message-
   From: edsi [mailto:[EMAIL PROTECTED]
   Sent: Wednesday, July 21, 2004 10:40 AM
   To: Protel EDA Forum
   Subject: [PEDA] Autorouting Techniques
  
  
   Hello All,
  
   Please feel free to  visit www.konekt.com  and read my white
   paper  on how to use the Electra Autorouter with Protel  99SE
   and  DXP products.  I have been posting for some time now
   that this router is one of the best products available.  I
   was asked by  the ConnectEDA staff  to write a paper for all
   you users that are afraid to try autorouters.   I have not
   accepted any payment for this effort , my only interest is
   have better design tools available and to open a new dialog
   for Protel users.
  
   Enjoy the article
  
   Mike Reagan
   EDSI
   Frederick MD



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Re: [PEDA] Autorouting Techniques

2004-07-22 Thread Stephen Noftall
Hi everyone;
I have a quick question on the autorouters: Which autorouter(s) will 
route traces nicely while taking into consideration a net length 
constraint? For example, to route high speed DDR ram signals, typically 
64 traces all have to be routed within 0.1 of each other. I have never 
seen an autorouter be able to do this. Is it even possible now with the 
new technologies?

Thanks
Stephen

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Re: [PEDA] SP6 not printing

2004-07-22 Thread Harry Lemmens
G'Day All,

  I have a similar issue with Protel SP6 for 99SE coupled with Win2k
SP4. installation of both caused my machine to become very unstable, throwing
the access violation at many places with 99SE. (Mainly in the simulator though,
However, leaving the machine for a while was also popping the same problem.)   I
did discover that turning off the auto-backup facility in 99SE seemed to
virtually eliminate this issue. (Although ... the simulator will still fall over
at the slightest provocation!)

So, perhaps turning off Auto-backup will help resolve your current dilemma?

If someone else has a better suggestion, I certainly would like to know, as I do
occasionally find the simulator useful. (Even though it is a pig of a thing to
use, especially regarding the addition of spice models)

Cheers
Harry


-Original Message-
From: John Girvan [mailto:[EMAIL PROTECTED]
Sent: Friday, July 23, 2004 9:53 AM
To: 'Protel EDA Forum'
Subject: [PEDA] SP6 not printing

Win2k Pro (SP2), 99SE, error when printing.

hey there,

we recently put SP6 on one of our machines here as we were\are running SP5.
was a new-ish machine and everything was running smoothly...

when printing a schematic we now get an 'access violation' error (ignore or
quit) and cannot print the schematic on this machine. after this u have to
close down protel and re-open and it gets ugly with access violation errors
in windows that will not go away unless u kill the client99se task.

got me stuffed!

any help appreciated.


thanks,


jjg.





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Re: [PEDA] Autorouting Techniques

2004-07-22 Thread Duane Foster
I have set a global clearance of 10mil and would like the router to follow a 12mil 
track to SMDpad clearance rule and a 14mil via to SMDpad clearance rule.  I have these 
additional clearance rules set in 99SE, but they do not transfer to the DSN file.

thanks
duane

 -Original Message-
 From: Mike Reagan [mailto:[EMAIL PROTECTED]
 Sent: Thursday, July 22, 2004 4:05 PM
 To: 'Protel EDA Forum'
 Subject: Re: [PEDA] Autorouting Techniques
 
 
 Duane
 
 The purpose of the article was to explore interactive routingthe
 interactive part and most boring part of this is manually 
 fanning out.  FAN
 out everything,   boring and time consuming I know. but the 
 rewards are no
 post clean up and very clean routes
 
 Just say No to the basic.do   FAN Out as I suggested, take my 
 word for it.
 
 If you have components on both sides and routing channels are 
 not open, it
 doesn't matter if you manually attempt to route .routing 
 channels must
 be open
 
 
 For your question.  But i still would like the router to 
 follow a 12mil
 track-SMDpad rule and a 14mil via-SMDpad ruleWhat are you calling
 track-SMDare you referring to the clearance to the smd 
 pad?   Trace
 widths can be controlled in Protel using net classes or identifying
 individual net names in the width rules set up.   Open the 
 DSN file using
 wordpad as I suggested, and do Control F to fine  the net you 
 assigned a
 rule to. If the net rule is not changed then the design rules 
 are not set up
 in Protel.  The DSN interface is excellent to ELECTRA and 
 Spectra.If the
 design rules are set up, and there is ample clearance to push 
 a 12 mil line
 thru, ELECTRA will route it in a microsecond.  If it is not routing in
 microseconds after you type in route, then the rules are in 
 conflict.  It is
 that simple correct rules, yeilds efficient routing
 
 Mike 
 
 
 
 
 
 
 -Original Message-
 From: Duane Foster [mailto:[EMAIL PROTECTED]
 Sent: Thursday, July 22, 2004 6:37 PM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Autorouting Techniques
 
 
 thanks for your help  see below for pointed response
 
  -Original Message-
  From: Mike Reagan [mailto:[EMAIL PROTECTED]
  Sent: Thursday, July 22, 2004 3:08 PM
  To: 'Protel EDA Forum'
  Subject: Re: [PEDA] Autorouting Techniques
  
  
  HI Duane
  
  Before I can give an answer to all of your questionI need 
  to know did
  you follow my step by step instructions for fanning out?   I 
  typically can
  route any design ( large ones with several thousand 
 components )  in 5
  passes.   The secret is the routing channels must be kept 
  open.  
 
 i did not do any fan out.. i tried this on the premise that 
 it is a simple
 board which 99SE could autoroute..  this board has some 0805s 
 and 14 pin
 SOICs.. are you recommending that i fan out the SOICs?
 
 
 
  Secondly,
  what is are you calling the basic do   is this the do file Protel
  generates?  (DXP only).
 
 i am referring to a file which was installed by Electra (Basic.do).
  
 
   
  I would stay away from assigning directives  like any 
  direction  this will
  only complicate things by not steering the router to work for 
  you.  Two
  layer designs work as easily as multilayer as long as you 
  have open
  channels.  That is key.   On very populated tight designs I 
  discount the
  component side as a routing layer because the components are 
  in the way.
 
 i have components on both sides?!  
 
 Perhaps it will route if i work on the component layout.  But 
 i still would
 like the router to follow a 12mil track-SMDpad rule and a 
 14mil via-SMDpad
 rule.
 Can you illuminate how to implement these special spacing rules?  
 
 
 
  
  Electra will route 100 percent, as long as your rules make 
  sense. Take a
  closer look at your rules and make sure they make sense. ie 
  can a 10 mil
  line fit inside a 8 mil gap   Let me know how I can help. 
   And thanks
  for reading it.
  
  Mike Reagan 
  
  
  -Original Message-
  From: Duane Foster [mailto:[EMAIL PROTECTED]
  Sent: Thursday, July 22, 2004 4:18 PM
  To: Protel EDA Forum
  Subject: Re: [PEDA] Autorouting Techniques
  
  
  Thanks for the white paper Mike.
  
  I have been curious to try the Electra autorouter ( mainly 
  because of your
  enthusiastic plugs ), and so I read your white paper and 
 got the demo.
  
  I routed a small double sided board with SMD on both sides.  
  I was able to
  get 100% routed in 99SE using 10/10 and 12mil spacing 
 SMD-track.  99SE
  router will not do my desired 14mil SMD-via spacing, so i 
  manually adjusted
  offending vias and cleaned up.
  
  I am trying Electra on the same layout and initially getting 
  94% completion
  and no adherance to any special clearance rules.
  
  I tried using your DO file and it seems ROUTE 5 is inadequate.  Am i
  misunderstanding your intention?
  
  I tried the basic.do file with an addition of rule pcb 
  (clearance 12 (type
  smd_wire). I 

Re: [PEDA] stopping second instance of 99SE

2004-07-22 Thread Dennis Saputelli
great ! thanks

i will try and report tomorrow

and yes they should have taken care of this for us

Dennis Saputelli


Harry Lemmens wrote:
 
 Supposedly, this app will allow you to control this aspect of windows. I have
 not tried it myself. http://www.softaward.com/732.html
 
 Actually, it should have been written into the application itself (That is, to
 detect, and dis-allow a second instance of itself to be launched!) Done
 correctly, it would have opened the DDB in the already active session.
 
 Cheers
 Harry
 
 -Original Message-
 From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
 Sent: Friday, July 23, 2004 11:11 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] stopping second instance of 99SE
 
 is there any utility out there that will stop a second instance of
 a program from running when you double click a data file with
 a file associated which would start that program ?
 
 sure would love that, seems like it would be feasible from the
 small amount i know about this stuff
 
 this desire is due to the all too frequent mishap of double
 clicking a DDB instead of or during dragging it to the title bar
 
 after 2 copies are running i have found it a MUST to quit
 them both and restart 99SE, else something goes screwy with the
 loaded libraries
 
 i'm sure i posted this some time ago but thought i would try
 again
 
 Dennis Saputelli
 
 --
 ___
 Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107
 2851 21st StreetFax: 415-647-3003
 San Francisco, CA 94110 www.integratedcontrolsinc.com

-- 
___
Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107 
2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com




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Re: [PEDA] SP6 not printing

2004-07-22 Thread Clive . Broome


Do you get the same problem when logged onto the machine as administrator?







John Girvan [EMAIL PROTECTED] on 07/23/2004 09:53:04 AM

Please respond to Protel EDA Forum [EMAIL PROTECTED]

To:   'Protel EDA Forum' [EMAIL PROTECTED]
cc:(bcc: Clive Broome/sdc)

Subject:  [PEDA] SP6 not printing



Win2k Pro (SP2), 99SE, error when printing.

hey there,

we recently put SP6 on one of our machines here as we were\are running SP5.
was a new-ish machine and everything was running smoothly...

when printing a schematic we now get an 'access violation' error (ignore or
quit) and cannot print the schematic on this machine. after this u have to
close down protel and re-open and it gets ugly with access violation errors
in windows that will not go away unless u kill the client99se task.

got me stuffed!

any help appreciated.


thanks,


jjg.











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*
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Re: [PEDA] stopping second instance of 99SE

2004-07-22 Thread Dennis Saputelli
oh well, thanks anyway Harry

but unless i missed something in my exhaustive :} 3 minute trial
of CONTROL LAUNCHER here is what i see:

the launcher they provide will not start a second copy of the
launched program if the default setting of 'one copy only'
is set and you use their program launch button

but if you dbl click on a DDB in 'explorer' a second copy is 
started up as usual

i would think that it would be possible for a program to
intercept the file association program 'launching' process and 
prevent that but as for now the search goes on
(maybe i am the only one who wants this)

BTW
and on a vaguely related topic
has anyone tried ExplorerPlus ? 
http://www.novatix.com/
as i am always in search of a file manager to replace 
the hated (at least by me) Windows Explorer
i have found this prog and am so far impressed enough that i 
actually shelled out the big bucks ($40) after the free trial run

Dennis Saputelli


Harry Lemmens wrote:
 
 Supposedly, this app will allow you to control this aspect of windows. I have
 not tried it myself. http://www.softaward.com/732.html
 
 Actually, it should have been written into the application itself (That is, to
 detect, and dis-allow a second instance of itself to be launched!) Done
 correctly, it would have opened the DDB in the already active session.
 
 Cheers
 Harry
 
 -Original Message-
 From: Dennis Saputelli [mailto:[EMAIL PROTECTED]
 Sent: Friday, July 23, 2004 11:11 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] stopping second instance of 99SE
 
 is there any utility out there that will stop a second instance of
 a program from running when you double click a data file with
 a file associated which would start that program ?
 
 sure would love that, seems like it would be feasible from the
 small amount i know about this stuff
 
 this desire is due to the all too frequent mishap of double
 clicking a DDB instead of or during dragging it to the title bar
 
 after 2 copies are running i have found it a MUST to quit
 them both and restart 99SE, else something goes screwy with the
 loaded libraries
 
 i'm sure i posted this some time ago but thought i would try
 again
 
 Dennis Saputelli
 
 --

-- 
___
Integrated Controls, Inc.   Tel: 415-647-0480  EXT 107 
2851 21st StreetFax: 415-647-3003
San Francisco, CA 94110 www.integratedcontrolsinc.com




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