Re: [PEDA] first BGA layout
Ralph,
This is just an aside and not an explanation to your problem. I laid
out a board with 3 BGAs are 0.75 mm and one 256 pin BGA at 1 mm
spacing. Using .004 tracks with .004 spacing I was able to route the
whole board on two signal layers with two power layers and no special
vias, meaning all were through hole, .018 pad .010 hole. It did take
some time and careful planing but at a huge PCB cost savings. Any time
you go over 4 layers and start using fancy vias the cost accelerates
geometrically. I your case that may not be an issue but in mine I had
no choice. Don't forget to use gold flash for the BGAs (for the whole
board is easier) to reduce manufacturing problems with soldering BGAs.
Cheers,
Tom
Ralph Effinger wrote:
I am haveing trouble laying put an 8 layer board. I have a schematic,
board with chips, resistor,caps and one 256 bga. The bga has a 1mm
pitch. I have setup the layer stack mang. and the desing rules the best
I know how,{this is my first bga}. I layed out the board using blind or
buried vias. I am using protell 99se. after auto routing the board, the
vias all go from the top layer to the bottom not useing any blind or
buried vias. I,ve looked at the tutorials and book, and can find
nothing to help me. thank you!
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Re: [PEDA] first BGA layout
Not a chance. I am using 99SE and have done simple, circuit wise,
boards in the past but I didn't trust it to do partial routing. There
is also lots of analog present. I made a probe card last year for a
452, or so, pin BGA with 3mil/3mil track/spacing and used the
autorouter. It was a 5 sided board with a 96 pin connector at each
side, therefore it had an odd shape. The autorouter did pretty well. I
had to reroute about 40 tracks and there were a ton of vias. I decided
to take the time with my current board since I will have to make changes
later and an autorouted board makes that difficult unless one reroutes
the board.
Cheers,
Tom
Tom Robinson wrote:
Hi Tom:
Did you autoroute this board?
tr :)
-Original Message-
From: Tom Reineking [mailto:[EMAIL PROTECTED]
Sent: Monday, July 26, 2004 1:48 PM
To: Protel EDA Forum
Subject: Re: [PEDA] first BGA layout
Ralph,
This is just an aside and not an explanation to your problem. I laid
out a board with 3 BGAs are 0.75 mm and one 256 pin BGA at 1 mm
spacing. Using .004 tracks with .004 spacing I was able to route the
whole board on two signal layers with two power layers and no special
vias, meaning all were through hole, .018 pad .010 hole. It did take
some time and careful planing but at a huge PCB cost savings. Any time
you go over 4 layers and start using fancy vias the cost accelerates
geometrically. I your case that may not be an issue but in mine I had
no choice. Don't forget to use gold flash for the BGAs (for the whole
board is easier) to reduce manufacturing problems with soldering BGAs.
Cheers,
Tom
Ralph Effinger wrote:
I am haveing trouble laying put an 8 layer board. I have a schematic,
board with chips, resistor,caps and one 256 bga. The bga has a 1mm
pitch. I have setup the layer stack mang. and the desing rules the best
I know how,{this is my first bga}. I layed out the board using blind or
buried vias. I am using protell 99se. after auto routing the board, the
vias all go from the top layer to the bottom not useing any blind or
buried vias. I,ve looked at the tutorials and book, and can find
nothing to help me. thank you!
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Re: [PEDA] Mini DIN footprint
We use a circular mini-DIN 9 pin right angle connector in many of our products. As an aside, it is a very robust connector due to the metal cross bar that prevents pins from bending regardless of how hard one tries to insert the plug in the wrong orientation. Anyhow, the pins are supposed to be compatible with lower pin count mini-DINs. That said, electromechanical drawings, footprints, and pin numbering should always be suspect. I have seldom found any of it good. Our pinout agrees with the manufacturer's, shock, and here it is as viewed from the component side (MH = mounting hole): Plug MH MH MH 3 1 2 6 7 4 5 8 9 I hope that this helps. Cheers, Tom DUTTON Phil wrote: I've been caught in the past with mini-DIN data sheets. The data sheet showed numbering for the 'locations' of the pins rather than the pin numbers. Also be careful of the view that they show. This is the numbering that I ended up with for right angle connectors (board edge uppermost) 3 1 2 4 5 6 and 3 1 2 5 6 4 7 8 regards, Phil. -Original Message- From: Jason Morgan [mailto:[EMAIL PROTECTED] Sent: Wednesday, 21 July 2004 6:05 PM To: Protel EDA Forum Subject: Re: [PEDA] Mini DIN footprint Sounds to me, like many things, each vendor has their own standard ;) Honestly, I've no idea if mini-DIN has a numbering standard (though the name, DIN means Deutsches Insitut f r Normung, a German standards org) What I normally do is use the numbering (or naming) that either makes most sense in my application or matches the chosen vendor for the component. I've found quite often that a seemingly identical component from two manufacturers can me subtly mechanically different. Choose one part from one manufacturer and specify that in the drawing. It would be worse to use the 'standard' in the drawing then have a difference from the supplier, you can bet somebody some time will wire up the plug wrong, following the text on it. j. -Original Message- From: Peder K. Hellegaard [mailto:[EMAIL PROTECTED] Sent: 21 July 2004 06:34 To: [EMAIL PROTECTED] Subject: [PEDA] Mini DIN footprint Hi everyone. Anybody who knows if there is any official standard pin numbering for the MIN DIN sockets ? I ask due to the fact that I have seen 3 different ways of numbering, from 3 different vendors. Have a nice day Peder * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Test points
Thanks Ian for the information. I was concerned about the grid also. I'll add the testpoint component to the schematics which will give me more flexibility. Thanks again. Tom Ian Wilson wrote: On 08:06 AM 3/06/2004, Tom Reineking said: .. 4 hours later ... Just got my post back and I did find an answer to the report part concerning nets without testpoints. The design rule Testpoint Usage does generate violations for those nets and therefore a report can be generated. There is also a document on the Protel web site in the learning guides under 99SE that explains the process. At this time I still haven't figured out the tenting issue. Tom I stopped using the automatic test point feature very quickly as it is based on a grid rather than a clearance. I ended up placing testpoint components on every net in the Sch (that I wanted to be probable, which in some case is all). These TP components have a footprint that consists only of a 1mm round surface pad. These can then be positioned exactly as required - even on top of vias if necessary. You can set rules that ensure a suitable probe clearance which is more important these days than them being on a grid. There is no way of globally setting the testpoint status of a group of selected pads in P99SE using the normal global dialog. There is a server you can download to do this though: http://www.considered.com.au/Protel01.htm see the SetSelectionAsTestPoints server. I am not sure but there may be another server around that does it as well. P99SE has a number of these arbitrary attributes that can not be globally changed. Tom Reineking wrote: I have a fairly complex BGA design that requires via tenting, at least on the component side. The PCB assembly will not go through wave solder, so no problem with the solder side. There are two problems I have run into. The first is tenting on one side. I checked the KB and only DXP and up appear to have this feature. But you realize that this is nothing of any use to PCB designers, there is *no* productivity gain to be had here. :-) I see in the via properties that tenting is enabled and a bottom testpoint is checked, but the bottom is still tented. Apparently 99SE doesn't use the testpoint selection to override the tenting selection. Is this true? Yes this is true. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Test points
I have a fairly complex BGA design that requires via tenting, at least on the component side. The PCB assembly will not go through wave solder, so no problem with the solder side. There are two problems I have run into. The first is tenting on one side. I checked the KB and only DXP and up appear to have this feature. I see in the via properties that tenting is enabled and a bottom testpoint is checked, but the bottom is still tented. Apparently 99SE doesn't use the testpoint selection to override the tenting selection. Is this true? Hopefully I'm missing some detail. The second problem I encountered has to do with Find and Set Testpoints, under PCB Tools, which reports that 46 nets out of the total could not find testpoints, but it doesn't tell me which ones so that I can fix them. I checked the report file in the CAM outputs but that only lists the successful testpoints. Any clues? Thanks for your help, Tom * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Test points
.. 4 hours later ... Just got my post back and I did find an answer to the report part concerning nets without testpoints. The design rule Testpoint Usage does generate violations for those nets and therefore a report can be generated. There is also a document on the Protel web site in the learning guides under 99SE that explains the process. At this time I still haven't figured out the tenting issue. Tom Tom Reineking wrote: I have a fairly complex BGA design that requires via tenting, at least on the component side. The PCB assembly will not go through wave solder, so no problem with the solder side. There are two problems I have run into. The first is tenting on one side. I checked the KB and only DXP and up appear to have this feature. I see in the via properties that tenting is enabled and a bottom testpoint is checked, but the bottom is still tented. Apparently 99SE doesn't use the testpoint selection to override the tenting selection. Is this true? Hopefully I'm missing some detail. The second problem I encountered has to do with Find and Set Testpoints, under PCB Tools, which reports that 46 nets out of the total could not find testpoints, but it doesn't tell me which ones so that I can fix them. I checked the report file in the CAM outputs but that only lists the successful testpoints. Any clues? Thanks for your help, Tom * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] logo in template does not show
Just my 2 cents ... We keep our logo *.wmf file on our network in one location so that it doesn't matter which computer you are using, the logo always appears. Just specify the complete path and that should do it. Although if the DDB is sent elsewhere then keeping it in the DDB should work. Haven't tried that. Tom Laurie Biddulph wrote: The problem is that the logo must be in the same folder as the DDB file(s). You will find that if you keep a common folder of all your DDB files along with the logo that it will load every time. If you then go and open a DDB in a different folder ten the next time Protel opens it will have been pointed to the new folder and as the logo is not there it will give the message you gave. This is one of the bugs in Protel that despite having been told where the logo is in your `Preferences' it still ends up looking in the current folder for the file. So either keep a common folder for all your DDB files (thats the way I do it) or put a copy of your logo in every folder where you have a DDB. This works with the Preferences fine. If you need to open/create a new DDB (even if it is only temporary) then make sure you create/place it in this common folder Best Regards Laurie Biddulph http://www.elby-designs.com - Original Message - From: Leo Potjewijd To: [EMAIL PROTECTED] Sent: Wednesday, May 12, 2004 2:09 AM Subject: [PEDA] logo in template does not show While experimenting with templates in P99SEsp6 I find that an included logo (BMP image) does not always show up. If the Ddb with the templates is open, all is well. If I close that Ddb and keep the design open the logo still shows, but when I open the design the next day (and keep the templates Ddb closed) the logo is replaced with the text Logo IE.bmp file not found. The rest of the template shows up just fine. I have imported the BMP file into the design Ddb: no success. Design-Template-Update produces a 'file format not recognised' error. When I use Design-Template-SetTemplateFilename and reselect the template from the templates Ddb the logo shows up again, even on sheets and Ddbs that are opened afterwards. Closing the templates Ddb makes no difference. The handbook is not really clear on this subject, nor is the online help so I suspect I missed something essential. Can any of you guys point me in the correct direction? Any input is greatly appreceated. Leo Potjewijd hardware designer Integrated Engineering B.V. [EMAIL PROTECTED] +31 20 4620700 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] File Format Not Recognized
It was probably exported in the PCAD 2000 format. Look at the .sch file with a text editor. The first few lines will tell you what's up. I had this problem once. I could not undo it successfully. Hope this helps. Tom [EMAIL PROTECTED] wrote: Hi, I'm having trouble opening schematics. A small window titled Design Explorer pops up with the message File Format Not Recognized when I try to open a newly created schematic. I press OK and the schematic appears to open just fine. I have no difficulties opening existing schematics in older databases; however, I get the same error if I try to create a new schematic. I don't have this problem creating/opening PCB documents. Any ideas? Thank you, Steve Allen Manufacturing Services, Inc. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber accuracy
Thanks Steve, That solved the problem. I checked the gerbers and, sure enough, the arcs were converted to straight lines that then violated the clearance settings. Amazing. Cheers, Tom Steve Wiseman wrote: 17/01/2004 00:37:59, Tom Reineking [EMAIL PROTECTED] wrote: I'm sure that I'm missing some basic understanding concerning gerber accuracy. Any clues? Thank you for any suggestions. Yep - use 'track', not 'arc' to generate the teardrops. For some reason, the arcs get turned back into straight lines, and you get the clearance violations you've noticed... thousands of them. Hope that helps, Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Gerber accuracy
Hi all, I just finished a PCB that used 4 mil tracks and 4 mil spacing imposed by the BGAs. I used teardrops for all pads and the 4 mil clearance was maintained. Using freeDFM checker at Advanced Circuits, I found many clearance errors, especially associated with teardrops. There were also a few pad to pad problems similar to the others. I found the error locations in 99SE PCB but the clearances were correct. I then checked Camtastic and found that there were clearance issues as reported. Typically the error was between 0.5 mil and .002 mil. I know that doesn't sound like much but 0.5 mil is significant down at 4 mil. Round off errors should be much smaller I'm guessing. I tried 2:4 and 2:5 gerber formats, same results. I'm sure that I'm missing some basic understanding concerning gerber accuracy. Any clues? Thank you for any suggestions. Cheers, Tom * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel 99SE on WinXP?
We run 99SE sp6 on Win XP and have not experienced any difficulty per station. We did have one issue with one of our designers on a hub network whereby every time he launched 99SE it froze the rest of us. We upgraded his station to DXP and the problem was solved. However, 99SE is not guaranteed to work with XP. Tom Website Visitor wrote: Does anyone have any experience running Protel 99SE on WinXP? I'm curious whether it will work at all. Thanks, Vince [EMAIL PROTECTED] Posted from Association web site by: Vince Bafetti * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Prototype Assembly House
Ivan, When soldering fine pitch parts, we use lots of liquid flux and then simply drag a tinned iron across the pins. The best solder joints around and the flux eliminates bridging. Don't over do the solder on the iron tip. Takes a few tries to develop tricks, but I have never failed yet. Of course you then have to rinse off the flux. I use isopropyl and clean compressed air. Haven't figured out BGAs by hand yet, but it will have to happen soon. Paste and an hot air knife??? Cheers, Tom Bagotronix Tech Support wrote: I can solder 0.5mm (19.685 mil) SMT IC's by hand no problem. BGAs are a different story... I can do that too. And my hand can slip, causing a solder bridge to an adjacent pin. It's a PITA to clear away that solder bridge from those small pins. Oh, how I long for DIP and 50mil SMT packages. I figured it out - it is possible to put an ethernet chip into a 28-pin package (with an 8-bit wide uP interface). So why doesn't anyone do it? They have 100+ pins. Phooey! Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Tim Fifield [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, September 03, 2003 3:09 PM Subject: Re: [PEDA] Prototype Assembly House I can solder 0.5mm (19.685 mil) SMT IC's by hand no problem. BGAs are a different story... * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Prototype Assembly House
Hi Yuriy, We've had very good luck with quality and quick turn around with Advanced Circuits, www.4pcd.com. I haven't done much with price comparison, though. Good luck. Tom Yuriy Khapochkin wrote: Could anybody recommend good place in US/Canada for ordering small prototype quantity (up to 10 pieces) PCB assembly? Personal experience especially welcome. Regards, Yuriy Khapochkin. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
Just one note on split planes. High speed signals crossing splits in either power or ground (they're the same for AC), there will be a reflection due to the sharp impedance change. Of course the effect will vary depending on trace length and split length and locations of nearby bypass caps. In general you should avoid that situation as it will increase the EMI and reduce the signal integrity. Tom Julian Higginson wrote: From: JaMi Smith [mailto:[EMAIL PROTECTED]] While there may be some way somewhere to make Protel ignore those dogbones and vias, DRC wise, I don't think that there is a way to do it easily short of putting them on the schematic, possibly as test points, so that each of them actually becomes a real "net" it the netlist. You could turn off some of your Design Rules, but that would really just be asking for more trouble. yeah there is a way: Don't use synchronisation in the ddb, use NETLIST GENERATION and NETLIST LOADING. In the netlist generation in schematic, you can tell it to include unnamed single pin nets. You will then get nets assigned to all your unused pins on your BGA. I would also suggest that you definitely look into using separate complete layers for power and ground under your BGA as opposed to trying to juggle split planes. Jeez. How many layers does he have spare for power planes?? my BGA needed 3 of the buggers. Split planes are the only way to go. Just be really careful not to bridge them with a through hole pin like I did... Julian (who got his BGA board not reporting errors, and the BGA part of it is fine) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Periodic hanging
Hi all - This is my first listing and hopefully my issue has been posted before. I'm using P99se/sp6 on WinXP prof. ver2002 along with a company wide network connection. Periodically, like every 3-5 minutes, Protel hangs and the task manager states not responding. It does return after about 2 minutes. Everything else works though; it's not hogging all of the CPU time. It is not associated with any particular activity. It will happen all by its lonesome. I tried closing down everything except Protel, edited the Client99se.ini to make broadcast access code and receive access code both true (hint from protel.support.na), with no improvement. A co-worker is facing the same problem and noticed that unplugging his network cable stopped the hanging, but that has obvious problems. I also disable the autosave feature but with no effect. This problem seems to have started recently but I haven't found a connection with some change in our system. I'm not sure what else to add. Any clues? Thank you for your help. Cheers, Tom * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
