Re: [PEDA] Polygon Repour in 99SE

Abd ul-Rahman Lomax wrote: There may be a better way, but as I recall, moving the entire design will force an update of all polygons. So select all, pick it up at the origin and move it over an inch, and then back if you must. It *may* work if the move leaves the design in the same place,

Re: [PEDA] Component Rotation

At 16:15 24.10.01 +0100, you wrote: I've already given up, and done it the standard way. I tried drawing it at 45 degrees as a library symbol, but the pins still had to be at 90 degrees. You can make zero-lenght pin and draw the pins with lines. Should work. Edi Im Hof I was just designing a

Re: [PEDA] Component Rotation

I thought about doing that..after I already designed it using standard symbols. -Original Message- From: Edi Im Hof [mailto:[EMAIL PROTECTED]] Sent: 25 October 2001 09:51 To: Protel EDA Forum Subject: Re: [PEDA] Component Rotation At 16:15 24.10.01 +0100, you wrote: I've

[PEDA] pcb lib default settings

Re: [PEDA] Urgent help needed

All, Do you find these components (in the negative quadrant) in the gerber or pick and place outputs? jmc Ian Wilson wrote: At 10:09 AM 25/10/01 +1000, you wrote: Ian, it's actually pretty easy to loose parts. We recently have had a situation where a group of components have been

[PEDA] elusive traces

hello, i've gone thru and hand-routed a 10-layer board from my protel schematic and bad artwork of the original layers. as suggested, i set the design rules for un-routed traces and it pointed out a few to me. here's what i ran into: i went to correct one of the unrun traces. it appeared

[PEDA] layer color problem

hello, i noticed that layer 2 and 6 traces are exactly the same color. so i went to tools/preferences/colors/signal layers and the topLayer and 3 midLayers are there but the midLayer 4, 5, and 6 beyond that are grayed out. HOWEVER, if i scroll all the way to the bottom, beyond the midlayer27,

Re: [PEDA] elusive traces

Hi, I could be wrong, but it sounds like the actual elusive traces are on another layer that is *not* visible. When you go to route or select a net, traces on some of the non-visible layers will temporarily appear to fix, turn on those layers and delete as appropriate.. do not

Re: [PEDA] pcb lib default settings

Michael Johnen wrote: Hi all, how can i permanently change the defaultsettings for example components, track and other stuff in the PCB LIB. it is changed under Tools, preferences, defaults. changing is possible, i can save it and load it back, but it is not loaded by starting

[PEDA] Via Nets

Though I have permenent checked in the via default menu, when placing vias, the net name always resets to no net. Is this normal behavior? or is it a bug? Jim -- Jim Muehlberg Electrical Engineer LO/IF Group National Radio Astronomy Observatory P.O. Box O 1003 Lopezville Rd. Socorro, NM

Re: [PEDA] Urgent help needed

I have had a library update cause a part to go haywire when the origin of the library part was way off from the center of the part. This was due to the library being imported from another package if I remember correctly. I have had a component move off the viewable area, and found a way to fix

Re: [PEDA] Polygon Repour in 99SE

At 08:31 AM 10/25/01 +1000, Ian Wilson wrote: http://groups.yahoo.com/group/protel-users/files/CitelTools%28RePourAllPolys %29.zip But you may need to be a member of the protel-users group to get access to it. Jason Morgan of Citel wrote it and gave permission for it to be lodged on the

[PEDA] Accessory lists for Protel users

(repeated from another thread for archive subject clarity] At 08:31 AM 10/25/01 +1000, Ian Wilson wrote: http://groups.yahoo.com/group/protel-users/files/CitelTools%28RePourAllPolys %29.zip But you may need to be a member of the protel-users group to get access to it. Jason Morgan of Citel

Re: [PEDA] Via Nets

At 08:47 AM 10/25/01 -0600, Jim Muehlberg wrote: Though I have permenent checked in the via default menu, when placing vias, the net name always resets to no net. Is this normal behavior? or is it a bug? It is normal behavior. I just explained it in another post, and also how to conveniently

Re: [PEDA] pcb lib default settings

[PEDA] Annoying track behaviour

When I'm placing tracks on a mechanical layer and change the width of the track (using TAB) the look ahead segment of the track changes to one of the signal layers. It is not possible to change the layer back by using +, - or * (they cycle through the signal layers only). So I have to stop

Re: [PEDA] Annoying track behaviour

Tom, I had the same problem, what you need to do is use place line instead. Darren Moore When I'm placing tracks on a mechanical layer and change the width of the track (using TAB) the look ahead segment of the track changes to one of the signal layers. It is not possible to change

Re: [PEDA] Annoying track behaviour

Thanks Darren, just what I wanted. (I had noticed the tool button for that function before but was not sure what it was for). Only one problem; why does the line constraints dialogue box (TAB when placing line) use mils for the line width when I'm working with metric units? It's not a major

[PEDA] schematic port references

I am having difficulties controlling the placement of the port references, mainly they are overlapping the port name which defeates the purpose of having them there. Note this is only in the printing of the schematic though. I was wondering if this had something to do with the scaling of the

Re: [PEDA] schematic port references

I too had several problems with incorrect printing (especially overbars on pinnames). Since I checked the Display Printer Fonts box in the Tools-Preferences-Graphical Editing Tab and changed Intercharacter spacing to 6 and Character Width Scale to 100% in the Setup Printer Dialog I get correct