subject:"\[PEDA\] PCB Rules question"

Re: [PEDA] PCB Rules question

2002-08-30 Thread Schmitt Michael


Tanks for the Infos that no one has a solution for that, so i guess protel
cannot handle this 


Like Dennis already said, we also have mech1 for the real board outline and
the keepout just to make the router happy and control some stuff the way it
is layouted.

> -Original Message-
> From: Kulajew Waldemar [mailto:[EMAIL PROTECTED]]
>   Funny how many of us are fighting with the Same 
> Problems. (not so funny when you realize that Michael Schmitt 
> and me are probably working on PCBs for the same devices ;)

**

well i am not working for IVO, that is in fact part of the Baumer Group like
us too. I am developing the wireless identification systems and not only the
layouts, instead of encoders, counters, displays ... so i think not the same
devices ...

Regards.

Dipl.-Ing. (FH) Michael Schmitt 
Baumer Ident GmbH 
Entwicklung / Development Department 
Hertzstr. 10 
D-69469 Weinheim 
Deutschland / Germany 
Tel. +49 (0) 6201 9957 - 30 
Fax. +49 (0) 6201 9957 - 99 
E-Mail : [EMAIL PROTECTED] 
Web:  





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Re: [PEDA] PCB Rules question

2002-08-29 Thread Kulajew Waldemar


Hello everyone,

Funny how many of us are fighting with the Same Problems. (not so funny when 
you realize that Michael Schmitt and me are probably working on PCBs for the same 
devices ;)
Like Brad (Mr. Valander) I have tried a lot of Rules to vermeiden this DRC-error. And 
like him I did not find any. 
So I decided to manage it like Mr Sapunelli (Dennis) mentioned it and bent the keepout 
around the Pads but kept it near enough to avoid Polygons from coming near the booard 
outline.
One more sign from me: if I have some pads near to eachother on the boardout I "cut" 
them with drills to avoid shorts arising during the milling of the board edge.


Best regards 
 
Waldemar Kulajew 
Entwicklung Drehgeber/Sensorik
Development Encoders/Sensors 

Fritz Kuebler GmbH 
Schubertstrasse 47 
78054 Villingen-Schwenningen 
Germany 
 


>  -Original Message-
>  From: Schmitt Michael [mailto:[EMAIL PROTECTED]]
>  Sent: Thursday, August 29, 2002 3:23 PM
>  To: Protel EDA Forum (E-Mail)
>  Subject: [PEDA] PCB Rules question
>  
>  
>  Now to something completly different ...
>  
>  I use Protel 99SE SP6 and i want to create / modify my 
>  design rules so that
>  there will be no drc errors if a pad and / or a track is 
>  touching the keep
>  out.
>  
>  Imagine a pad placed inside the pcb-outline and keepout's 
>  but the outter
>  diameter of that pad is not inside the keepout as the outer 
>  diameter is
>  bigger than the relative distance of the pad to the keepout.
>  
>  the reason is that a have to place pads at the edge of the 
>  pcb that there is
>  no gap between the pad / track an the keepout (the outline 
>  of the pcb) so
>  the copper will be directly at the end of a pcb side ... yes 
>  i know that
>  there should be normaly a gap of about 20-25mil but in this 
>  case i realy
>  need the pads and tracks be placed at the edged ..
>  
>  i have tried to setup some design rules like
>  
>  Clearance Rule
>  A: Object Kind (Via; TH-Pad; Tracks/Arcs)
>  B: Object Kind (KeepOuts)
>  Any Net
>  Minimum Clearance 0mil
>  
>  but all i enter in these dialog box still produces DRC erros 
>  as if it is in
>  general not allowed to place anything directly with no gap 
>  to a keepout.
>  
>  well of course i could ignore these messages, but i prefer a 
>  final pcb
>  without any drc error messages.
>  
>  any ideas ?
>  
>  Dipl.-Ing. (FH) Michael Schmitt 
>  Baumer Ident GmbH 
>  Entwicklung / Development Department 
>  Hertzstr. 10 
>  D-69469 Weinheim 
>  Deutschland / Germany 
>  Tel. +49 (0) 6201 9957 - 30 
>  Fax. +49 (0) 6201 9957 - 99 
>  E-Mail : [EMAIL PROTECTED] 
>  Web: <http://www.baumerident.com/>  


* Tracking #: 2E65C283B9F3DE4489E93EA61D08A9119970E41A
*


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Re: [PEDA] PCB Rules question

2002-08-29 Thread Brad Velander


Michael,
sorry, that rule doesn't work in the case of keepouts (general, or
layer specific). I use almost that exact rule already and you are right that
the deletion of the general board-board clearance rule presents a risk. Any
no net item can short to another net if the board-board clearance is
deleted. Solution, don't delete the general board-board rule just disable it
and then selectively turn it on to check for problems.

I have tried writing all sorts of rules to allow for pads touching a
keepout, tracks/nets touching the keepout, via pads overlapping each other
by a controlled amount, minimal laminate between via drill holes, all to no
avail. I have tried using net classes, pad classes, pad specifications. They
all fail the minute that your item touches the keepout. A "0" mil rule does
not seem to do anything, if it touches then there is a violation as long as
the condition is covered by any form of rule.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com
Norsat's Microwave Products Division has now achieved ISO 9001:2000
certification 



> -Original Message-
> From: Michael Reagan [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, August 29, 2002 11:06 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] PCB Rules question
> 
> 
> I know, I know, I know, how to do it
> 
> Create a class of nets to include all your nets, Delete the 
> default board/
> board  clearance rule, add a clearance rule ( your net 
> classname ) to ( your
> net class name)
> 
> It works but I wouldnt use it,  I was tinkering with this 
> several months ago
> while doing BGAs and had intentional  shorts all on the same 
> board. I forgot
> why it was dangerous, but I dont use it
> 
> Try it
> 
> Mike Reagan
> 
> 
> > -Original Message-
> > From: Brad Velander [mailto:[EMAIL PROTECTED]]
> > Sent: Thursday, August 29, 2002 11:48 AM
> > To: 'Protel EDA Forum'
> > Subject: Re: [PEDA] PCB Rules question
> >
> >
> > Michael,
> > I have some very similar needs but have never found a way to
> > accomplish this task. I have had the same results as you 
> have described. I
> > look forward to reading any results that have come to a different
> > conclusion.
> > In my case I have tried the exact same thing with layer specific
> > keepouts. In a similar vein I have also searched for a manner of
> > setting via
> > holes such that they have a minimum laminate material left 
> between them
> > after drilling, seems anything to test vias in the rules only
> > tests the via
> > metal pad and to a 0mil space or touching. Anything closer 
> then touching
> > pads cannot be defined.
> >
> > Sincerely,
> > Brad Velander.
> >
> > Lead PCB Designer
> > Norsat International Inc.
> > Microwave Products
> > Tel   (604) 292-9089 (direct line)
> > Fax  (604) 292-9010
> > email: [EMAIL PROTECTED]
> > http://www.norsat.com
> > Norsat's Microwave Products Division has now achieved ISO 9001:2000
> > certification


* Tracking #: 5673900B70464C4AB715EFFF24B52B4E2F939D47
*


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Re: [PEDA] PCB Rules question

2002-08-29 Thread Michael Reagan


I know, I know, I know, how to do it

Create a class of nets to include all your nets, Delete the default board/
board  clearance rule, add a clearance rule ( your net classname ) to ( your
net class name)

It works but I wouldnt use it,  I was tinkering with this several months ago
while doing BGAs and had intentional  shorts all on the same board. I forgot
why it was dangerous, but I dont use it

Try it

Mike Reagan


> -Original Message-
> From: Brad Velander [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, August 29, 2002 11:48 AM
> To: 'Protel EDA Forum'
> Subject: Re: [PEDA] PCB Rules question
>
>
> Michael,
>   I have some very similar needs but have never found a way to
> accomplish this task. I have had the same results as you have described. I
> look forward to reading any results that have come to a different
> conclusion.
>   In my case I have tried the exact same thing with layer specific
> keepouts. In a similar vein I have also searched for a manner of
> setting via
> holes such that they have a minimum laminate material left between them
> after drilling, seems anything to test vias in the rules only
> tests the via
> metal pad and to a 0mil space or touching. Anything closer then touching
> pads cannot be defined.
>
> Sincerely,
> Brad Velander.
>
> Lead PCB Designer
> Norsat International Inc.
> Microwave Products
> Tel   (604) 292-9089 (direct line)
> Fax  (604) 292-9010
> email: [EMAIL PROTECTED]
> http://www.norsat.com
> Norsat's Microwave Products Division has now achieved ISO 9001:2000
> certification
>
>
>
> > -Original Message-
> > From: Schmitt Michael [mailto:[EMAIL PROTECTED]]
> > Sent: Thursday, August 29, 2002 6:23 AM
> > To: Protel EDA Forum (E-Mail)
> > Subject: [PEDA] PCB Rules question
> >
> >
> > Now to something completly different ...
> >
> > I use Protel 99SE SP6 and i want to create / modify my design
> > rules so that
> > there will be no drc errors if a pad and / or a track is
> > touching the keep
> > out.
> >
> > Imagine a pad placed inside the pcb-outline and keepout's but
> > the outter
> > diameter of that pad is not inside the keepout as the outer
> > diameter is
> > bigger than the relative distance of the pad to the keepout.
> >
> > the reason is that a have to place pads at the edge of the
> > pcb that there is
> > no gap between the pad / track an the keepout (the outline of
> > the pcb) so
> > the copper will be directly at the end of a pcb side ... yes
> > i know that
> > there should be normaly a gap of about 20-25mil but in this
> > case i realy
> > need the pads and tracks be placed at the edged ..
> >
> > i have tried to setup some design rules like
> >
> > Clearance Rule
> > A: Object Kind (Via; TH-Pad; Tracks/Arcs)
> > B: Object Kind (KeepOuts)
> > Any Net
> > Minimum Clearance 0mil
> >
> > but all i enter in these dialog box still produces DRC erros
> > as if it is in
> > general not allowed to place anything directly with no gap to
> > a keepout.
> >
> > well of course i could ignore these messages, but i prefer a final pcb
> > without any drc error messages.
> >
> > any ideas ?
> >
> > Dipl.-Ing. (FH) Michael Schmitt
> > Baumer Ident GmbH
> > Entwicklung / Development Department
> > Hertzstr. 10
> > D-69469 Weinheim
> > Deutschland / Germany
> > Tel. +49 (0) 6201 9957 - 30
> > Fax. +49 (0) 6201 9957 - 99
> > E-Mail : [EMAIL PROTECTED]
> > Web: <http://www.baumerident.com/>
> >
> >
>
> 
> * Tracking #: 8D52133DB5934C46ACCBEAAD91ABEDE4C9290AAC
> *
> 
>

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Re: [PEDA] PCB Rules question

2002-08-29 Thread Brad Velander


Michael,
I have some very similar needs but have never found a way to
accomplish this task. I have had the same results as you have described. I
look forward to reading any results that have come to a different
conclusion.
In my case I have tried the exact same thing with layer specific
keepouts. In a similar vein I have also searched for a manner of setting via
holes such that they have a minimum laminate material left between them
after drilling, seems anything to test vias in the rules only tests the via
metal pad and to a 0mil space or touching. Anything closer then touching
pads cannot be defined.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com
Norsat's Microwave Products Division has now achieved ISO 9001:2000
certification 



> -Original Message-
> From: Schmitt Michael [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, August 29, 2002 6:23 AM
> To: Protel EDA Forum (E-Mail)
> Subject: [PEDA] PCB Rules question
> 
> 
> Now to something completly different ...
> 
> I use Protel 99SE SP6 and i want to create / modify my design 
> rules so that
> there will be no drc errors if a pad and / or a track is 
> touching the keep
> out.
> 
> Imagine a pad placed inside the pcb-outline and keepout's but 
> the outter
> diameter of that pad is not inside the keepout as the outer 
> diameter is
> bigger than the relative distance of the pad to the keepout.
> 
> the reason is that a have to place pads at the edge of the 
> pcb that there is
> no gap between the pad / track an the keepout (the outline of 
> the pcb) so
> the copper will be directly at the end of a pcb side ... yes 
> i know that
> there should be normaly a gap of about 20-25mil but in this 
> case i realy
> need the pads and tracks be placed at the edged ..
> 
> i have tried to setup some design rules like
> 
> Clearance Rule
> A: Object Kind (Via; TH-Pad; Tracks/Arcs)
> B: Object Kind (KeepOuts)
> Any Net
> Minimum Clearance 0mil
> 
> but all i enter in these dialog box still produces DRC erros 
> as if it is in
> general not allowed to place anything directly with no gap to 
> a keepout.
> 
> well of course i could ignore these messages, but i prefer a final pcb
> without any drc error messages.
> 
> any ideas ?
> 
> Dipl.-Ing. (FH) Michael Schmitt 
> Baumer Ident GmbH 
> Entwicklung / Development Department 
> Hertzstr. 10 
> D-69469 Weinheim 
> Deutschland / Germany 
> Tel. +49 (0) 6201 9957 - 30 
> Fax. +49 (0) 6201 9957 - 99 
> E-Mail : [EMAIL PROTECTED] 
> Web: <http://www.baumerident.com/> 
> 
> 


* Tracking #: 8D52133DB5934C46ACCBEAAD91ABEDE4C9290AAC
*


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Re: [PEDA] PCB Rules question

2002-08-29 Thread Dennis Saputelli


we run into this all the time
just don't think of the keep out as the board outline
we make the board outline on mech 1 or whatever and then draw the 
keep out layer either on top of the board layer or inside the the board
layer a little bit

in your case you would just bend the keep out layer around the pads by
the appropriate amount

Dennis Saputelli


Schmitt Michael wrote:
> 
> Now to something completly different ...
> 
> I use Protel 99SE SP6 and i want to create / modify my design rules so that
> there will be no drc errors if a pad and / or a track is touching the keep
> out.
> 
> Imagine a pad placed inside the pcb-outline and keepout's but the outter
> diameter of that pad is not inside the keepout as the outer diameter is
> bigger than the relative distance of the pad to the keepout.
> 
> the reason is that a have to place pads at the edge of the pcb that there is
> no gap between the pad / track an the keepout (the outline of the pcb) so
> the copper will be directly at the end of a pcb side ... yes i know that
> there should be normaly a gap of about 20-25mil but in this case i realy
> need the pads and tracks be placed at the edged ..
> 
> i have tried to setup some design rules like
> 
> Clearance Rule
> A: Object Kind (Via; TH-Pad; Tracks/Arcs)
> B: Object Kind (KeepOuts)
> Any Net
> Minimum Clearance 0mil
> 
> but all i enter in these dialog box still produces DRC erros as if it is in
> general not allowed to place anything directly with no gap to a keepout.
> 
> well of course i could ignore these messages, but i prefer a final pcb
> without any drc error messages.
> 
> any ideas ?
> 
> Dipl.-Ing. (FH) Michael Schmitt
> Baumer Ident GmbH
> Entwicklung / Development Department
> Hertzstr. 10
> D-69469 Weinheim
> Deutschland / Germany
> Tel. +49 (0) 6201 9957 - 30
> Fax. +49 (0) 6201 9957 - 99
> E-Mail : [EMAIL PROTECTED]
> Web: 
> 
> 
> * Tracking #: B20D94969EBD90418293584CEC291816420C6E43
> *
> 

-- 
___
www.integratedcontrolsinc.comIntegrated Controls, Inc.
   tel: 415-647-04802851 21st Street  
  fax: 415-647-3003San Francisco, CA 94110

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Re: [PEDA] PCB Rules question

2002-08-29 Thread Brian Sherer


Michael, I've handled this issue by offsetting the Keep Out tracks/arcs
outside the physical edge of the board by a fixed amount, say 10mils.
If the board is to have Polygons or Planes, you may have to create a
temporary set of keepouts to control polygon/plane pours to a wider
clearance; if these polygon control keepouts are made with a unique 
track width, they can be easily selected and moved off-board for later
DRC operation. Note that most board houses will be unhappy with copper 
closer than 10mils to the physical edge of the board, as the outer copper 
can get ripped up during routing. They may be willing to do it, but will 
probably need a special fab note which OKs damage to the copper.

Brian

At 03:23 PM 8/29/02 +0200, you wrote:
>Now to something completly different ...
>
>I use Protel 99SE SP6 and i want to create / modify my design rules so that
>there will be no drc errors if a pad and / or a track is touching the keep
>out.
>
>Imagine a pad placed inside the pcb-outline and keepout's but the outter
>diameter of that pad is not inside the keepout as the outer diameter is
>bigger than the relative distance of the pad to the keepout.
>
>the reason is that a have to place pads at the edge of the pcb that there is
>no gap between the pad / track an the keepout (the outline of the pcb) so
>the copper will be directly at the end of a pcb side ... yes i know that
>there should be normaly a gap of about 20-25mil but in this case i realy
>need the pads and tracks be placed at the edged ..
>
>i have tried to setup some design rules like
>
>Clearance Rule
>A: Object Kind (Via; TH-Pad; Tracks/Arcs)
>B: Object Kind (KeepOuts)
>Any Net
>Minimum Clearance 0mil
>
>but all i enter in these dialog box still produces DRC erros as if it is in
>general not allowed to place anything directly with no gap to a keepout.
>
>well of course i could ignore these messages, but i prefer a final pcb
>without any drc error messages.
>
>any ideas ?
>
>Dipl.-Ing. (FH) Michael Schmitt 
>Baumer Ident GmbH 
>Entwicklung / Development Department 
>Hertzstr. 10 
>D-69469 Weinheim 
>Deutschland / Germany 
>Tel. +49 (0) 6201 9957 - 30 
>Fax. +49 (0) 6201 9957 - 99 
>E-Mail : [EMAIL PROTECTED] 
>Web:  
>
>
>
>* Tracking #: B20D94969EBD90418293584CEC291816420C6E43
>*
>
> 

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[PEDA] PCB Rules question

2002-08-29 Thread Schmitt Michael


Now to something completly different ...

I use Protel 99SE SP6 and i want to create / modify my design rules so that
there will be no drc errors if a pad and / or a track is touching the keep
out.

Imagine a pad placed inside the pcb-outline and keepout's but the outter
diameter of that pad is not inside the keepout as the outer diameter is
bigger than the relative distance of the pad to the keepout.

the reason is that a have to place pads at the edge of the pcb that there is
no gap between the pad / track an the keepout (the outline of the pcb) so
the copper will be directly at the end of a pcb side ... yes i know that
there should be normaly a gap of about 20-25mil but in this case i realy
need the pads and tracks be placed at the edged ..

i have tried to setup some design rules like

Clearance Rule
A: Object Kind (Via; TH-Pad; Tracks/Arcs)
B: Object Kind (KeepOuts)
Any Net
Minimum Clearance 0mil

but all i enter in these dialog box still produces DRC erros as if it is in
general not allowed to place anything directly with no gap to a keepout.

well of course i could ignore these messages, but i prefer a final pcb
without any drc error messages.

any ideas ?

Dipl.-Ing. (FH) Michael Schmitt 
Baumer Ident GmbH 
Entwicklung / Development Department 
Hertzstr. 10 
D-69469 Weinheim 
Deutschland / Germany 
Tel. +49 (0) 6201 9957 - 30 
Fax. +49 (0) 6201 9957 - 99 
E-Mail : [EMAIL PROTECTED] 
Web:  



* Tracking #: B20D94969EBD90418293584CEC291816420C6E43
*


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Re: [PEDA] PCB Rules question

Re: [PEDA] PCB Rules question

Re: [PEDA] PCB Rules question

Re: [PEDA] PCB Rules question

Re: [PEDA] PCB Rules question

Re: [PEDA] PCB Rules question

Re: [PEDA] PCB Rules question

[PEDA] PCB Rules question

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