Michael,
        sorry, that rule doesn't work in the case of keepouts (general, or
layer specific). I use almost that exact rule already and you are right that
the deletion of the general board-board clearance rule presents a risk. Any
no net item can short to another net if the board-board clearance is
deleted. Solution, don't delete the general board-board rule just disable it
and then selectively turn it on to check for problems.

        I have tried writing all sorts of rules to allow for pads touching a
keepout, tracks/nets touching the keepout, via pads overlapping each other
by a controlled amount, minimal laminate between via drill holes, all to no
avail. I have tried using net classes, pad classes, pad specifications. They
all fail the minute that your item touches the keepout. A "0" mil rule does
not seem to do anything, if it touches then there is a violation as long as
the condition is covered by any form of rule.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com
Norsat's Microwave Products Division has now achieved ISO 9001:2000
certification 



> -----Original Message-----
> From: Michael Reagan [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, August 29, 2002 11:06 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] PCB Rules question
> 
> 
> I know, I know, I know, how to do it
> 
> Create a class of nets to include all your nets, Delete the 
> default board/
> board  clearance rule, add a clearance rule ( your net 
> classname ) to ( your
> net class name)
> 
> It works but I wouldnt use it,  I was tinkering with this 
> several months ago
> while doing BGAs and had intentional  shorts all on the same 
> board. I forgot
> why it was dangerous, but I dont use it
> 
> Try it
> 
> Mike Reagan
> 
> 
> > -----Original Message-----
> > From: Brad Velander [mailto:[EMAIL PROTECTED]]
> > Sent: Thursday, August 29, 2002 11:48 AM
> > To: 'Protel EDA Forum'
> > Subject: Re: [PEDA] PCB Rules question
> >
> >
> > Michael,
> >     I have some very similar needs but have never found a way to
> > accomplish this task. I have had the same results as you 
> have described. I
> > look forward to reading any results that have come to a different
> > conclusion.
> >     In my case I have tried the exact same thing with layer specific
> > keepouts. In a similar vein I have also searched for a manner of
> > setting via
> > holes such that they have a minimum laminate material left 
> between them
> > after drilling, seems anything to test vias in the rules only
> > tests the via
> > metal pad and to a 0mil space or touching. Anything closer 
> then touching
> > pads cannot be defined.
> >
> > Sincerely,
> > Brad Velander.
> >
> > Lead PCB Designer
> > Norsat International Inc.
> > Microwave Products
> > Tel   (604) 292-9089 (direct line)
> > Fax  (604) 292-9010
> > email: [EMAIL PROTECTED]
> > http://www.norsat.com
> > Norsat's Microwave Products Division has now achieved ISO 9001:2000
> > certification

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