[PATCH v2 13/37] clk: rockchip: rk3588: Fix ACLK_BUS_ROOT divider encoding

[Jonas Karlman]

The ACLK_BUS_ROOT divider field stores the divisor minus one. Subtract
one when writing the field so the clock uses the intended divisor.

Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.sch...@cherry.de>
---
Changes in v2:
- Split from "rk3588: Fix ACLK_BUS_ROOT rate set during probe"
- Add fixes tag
- Collect r-b tag
---
 drivers/clk/rockchip/clk_rk3588.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3588.c 
b/drivers/clk/rockchip/clk_rk3588.c
index dbb4cd57e250..50e0a27819df 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -1927,7 +1927,7 @@ static void rk3588_clk_init(struct rk3588_clk_priv *priv)
        rk_clrsetreg(&priv->cru->clksel_con[38],
                     ACLK_BUS_ROOT_SEL_MASK |
                     ACLK_BUS_ROOT_DIV_MASK,
-                    div << ACLK_BUS_ROOT_DIV_SHIFT);
+                    (div - 1) << ACLK_BUS_ROOT_DIV_SHIFT);
 
        if (priv->cpll_hz != CPLL_HZ) {
                ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru,
-- 
2.55.0