[casper] VHDL black-boxing (lack of existing documentation)

[James Smith]

Hello all,

I've been trying to move away from such big heavy models, my ultimate goal
being to have VHDL black boxes instead of precompiled ones made from Xilinx
or Casper DSP blocks.

Jack Hickish's HDL Black Box Tutorial (
https://casper.berkeley.edu/wiki/Tutorial_HDL_Black_Box) demonstrates a
very simple example of this, but I wanted something which could be a little
bit more dynamic, e.g. in terms of bit-widths for a given input. I started
with a simple D-flip-flop block, which would automatically size itself
according to what was put in at the input. Eventually I got it right.

This is my VHDL code (important points noted with  - these aren't
obvious from the above tutorial):
#
library IEEE;
use IEEE.std_logic_1164.all;

entity d_flip_flop_nbit is
generic (n_bits: positive); #
port (D : in std_logic_vector(n_bits - 1 downto 0); 
  clk, ce: in std_logic;
  Q : out std_logic_vector(n_bits - 1 downto 0)); 
end d_flip_flop_nbit;

architecture behav of d_flip_flop_nbit is
begin

dffn: process (clk)
begin
if (rising_edge(clk)) then
Q = D;
end if;
end process dffn;

end behav;
#

This is the accompanying config M-file:

%
function d_flip_flop_nbit_config(this_block)
  this_block.setTopLevelLanguage('VHDL');
  this_block.setEntityName('d_flip_flop_nbit');
  this_block.addSimulinkInport('D');
  this_block.addSimulinkOutport('Q');

  % -
  if (this_block.inputTypesKnown)

this_block.addGeneric('n_bits','positive',num2str(this_block.port('D').width));
%

%Sysgen user guide specifies these lines of code but Matlab doesn't
like them. Apparently
%the functions referred don't actually exist. What I have below is a
bit of a hack but it worked.
% q_port = this_block.port('Q');
% q_port.setWidth = this_block.port('D').width;
% q_port.setBinPt(0);
% q_port.makeUnsigned();

q_port = this_block.port('Q');
q_port_string =
strcat('Ufix_',num2str(this_block.port('D').width),'_0'); %
q_port.setType(q_port_string);

  end  % if(inputTypesKnown)
  % -

  % -
   if (this_block.inputRatesKnown)
 setup_as_single_rate(this_block,'clk','ce')
   end  % if(inputRatesKnown)
  % -

uniqueInputRates = unique(this_block.getInputRates);

  this_block.addFile('d_flip_flop_nbit.vhd');

return;
% 

function setup_as_single_rate(block,clkname,cename)
  inputRates = block.inputRates;
  uniqueInputRates = unique(inputRates);
  if (length(uniqueInputRates)==1  uniqueInputRates(1)==Inf)
block.addError('The inputs to this block cannot all be constant.');
return;
  end
  if (uniqueInputRates(end) == Inf)
 hasConstantInput = true;
 uniqueInputRates = uniqueInputRates(1:end-1);
  end
  if (length(uniqueInputRates) ~= 1)
block.addError('The inputs to this block must run at a single rate.');
return;
  end
  theInputRate = uniqueInputRates(1);
  for i = 1:block.numSimulinkOutports
 block.outport(i).setRate(theInputRate);
  end
  block.addClkCEPair(clkname,cename,theInputRate);
  return;
% 
%

I searched fairly extensively through the archive, and I saw no
documentation of this. The Xilinx documentation helped a bit, but
discrepancies between it and what Matlab would actually accept caused me
many headaches. In the end I found the workaround above which seemed to
work, but I'll admit I don't like it very much.

Is anyone else working in this sort of an environment? Is there any reason
that VHDL / Verilog seems to have been abandoned in favour of the
Simulink-based block approach? Would anyone find it helpful if the
tutorials were expanded a bit with this kind of information?

Regards,
James

[casper] Suggested convention for writing registers

[James Smith]

...

Regards,
James Smith

Re: [casper] Suggested convention for writing registers

[James Smith]

Hi Paul,

Thanks for the link. I looked through the code a bit and it doesn't seem as
though the corr library at all. Have I been using the wrong tool for the
job?

Would you be able to point me to which file I should start with to get a
handle on how the casperfpga package works?

Regards,
James


On Fri, Mar 20, 2015 at 9:22 AM, Paul Prozesky paul.proze...@gmail.com
wrote:

 Morning James

 We do this in already in the casperfpga package:
 https://github.com/ska-sa/casperfpga

 It turns out construct is pretty slow, so we just do the conversions and
 shifts manually. I think currently the fpg files that are automatically
 parsed by casperfpga are only generated for ROACH2, but it would be easy to
 add ROACH support.

 Cheers
 Paul




 On 20 March 2015 at 09:08, James Smith jsm...@ska.ac.za wrote:

 Hello all,

 I've given some thought to the topic of writing (and reading) registers
 on the ROACH using the python corr module. Often in a design a single
 register may be sliced into many bits to control various things. The way
 I've normally seen such a register written in python looks something like
 this:

 fpga.write_int('control',19|110|025|12|13)

 My feeling is that this approach is difficult to maintain - inheriting
 code from someone else (or even from one's self 6 months down the line) is
 likely to bring about some confusion in this case, and lead to a fair
 amount of spelunking through the Simulink model in order to figure out what
 bit 9 and bit 10 etc. do. On top of this, it places limitations on changing
 one of the bits later without modifying the other ones - bitwise or
 functions work well enough when you're over-writing zeros, but if there's
 something there already it might not work so well.

 With this in mind, I would like to suggest a convention which I worked
 out. It uses python modules struct and construct to make code a bit
 easier to read.
 (For reference if anyone is unfamiliar:
 struct - https://docs.python.org/2/library/struct.html
 construct - http://construct.readthedocs.org/en/latest/ )

 In the design I'm working on at the moment (a wideband spectrometer), I
 wrote a python module with the following in it:

 # Bitstruct to control the control register on the ROACH
 control_reg_bitstruct = construct.BitStruct('control_reg',
 construct.Padding(4),   #28-31
 construct.BitField('debug_snap_select',3),  #25-27
 construct.Padding(3),   #22-24
 construct.Flag('fine_tvg_en'),  #21
 construct.Flag('adc_tvg'),  #20
 construct.Flag('fd_fs_tvg'),#19
 construct.Flag('packetiser_tvg'),   #18
 construct.Flag('ct_tvg'),   #17
 construct.Flag('tvg_en'),   #16
 construct.Padding(4),   #12-15
 construct.Flag('fancy_en'), #11
 construct.Flag('adc_protect_disable'),  #10
 construct.Flag('gbe_enable'),   #09
 construct.Flag('gbe_rst'),  #08
 construct.Padding(4),   #04-07
 construct.Flag('clr_status'),   #03
 construct.Flag('arm'),  #02
 construct.Flag('man_sync'), #01
 construct.Flag('sys_rst') ) #00

 This BitStruct makes the code a little bit more readable, tells you what
 each bit does, and if you've done this declaration right once, then you
 don't need to worry about whether you'e shifting numbers by the right
 amount of bits. For the BitFields where several bits are passed, I used a
 dictionary to make remembering things (and reading the code) easier as well:

 # Dictionary for selecting the debug_snap_select bit
 debug_snap_select = {
 'coarse_72':   0,
 'fine_128':1,
 'quant_16':2,
 'ct_64':   3,
 'xaui_128':4,
 'gbetx0_128':  5,
 'buffer_72':   6,
 'finepfb_72':  7 }

 So writing to the register for the first time works like this:

 control_reg = avn.control_reg_bitstruct.parse('\x00\x00\x00\x00') #
 Create a blank one to use...
 # Pulse arm and clr_status high, along with setting gbe_enable and
 adc_protect_disable high
 control_reg.gbe_enable = True
 control_reg.adc_protect_disable = True
 control_reg.clr_status = True
 control_reg.arm = True
 fpga.write_int('control', struct.unpack('I',
 avn.control_reg_bitstruct.build(control_reg))[0]) # The [0] is necessary
 because the fpga.write_int function wants an integer datatype, and
 struct.unpack returns a tuple for some reason.
 # Bring arm and clr_status low again.
 control_reg.clr_status = False
 control_reg.arm = False
 fpga.write_int('control',
 struct.unpack('I',avn.control_reg_bitstruct.build(control_reg))[0])

 Then, for example if you're controlling something with a function and you
 need to change only one part of what's

Re: [casper] Suggested convention for writing registers

[James Smith]

Hello Marc,

Thanks for the comments - I've just sat down with Paul and he's mentioned
similar things to what you have.

The only challenge with that is tcpborphserver3 doesn't run on ROACH yet,
only ROACH2 as I understand. I'm going to have a bit of a go at using the
casperfpga library anyway and seeing if I can get it to work with ROACH
using a work-around which Paul suggested. I'll post my findings to the
mailing list next week sometime.

Regards,
James


On Fri, Mar 20, 2015 at 10:01 AM, Marc Welz m...@ska.ac.za wrote:



 On Fri, Mar 20, 2015 at 7:08 AM, James Smith jsm...@ska.ac.za wrote:

 Hello all,

 I've given some thought to the topic of writing (and reading) registers
 on the ROACH using the python corr module. Often in a design a single
 register may be sliced into many bits to control various things. The way
 I've normally seen such a register written in python looks something like
 this:

 fpga.write_int('control',19|110|025|12|13)

 My feeling is that this approach is difficult to maintain - inheriting
 code from someone else (or even from one's self 6 months down the line) is
 likely to bring about some confusion in this case, and lead to a fair
 amount of spelunking through the Simulink model in order to figure out what
 bit 9 and bit 10 etc. do. On top of this, it places limitations on changing
 one of the bits later without modifying the other ones - bitwise or
 functions work well enough when you're over-writing zeros, but if there's
 something there already it might not work so well.


 So it turns out that it is possible to define registers which aren't full
 word sizes long in tcpborphserver itself - and then the powerpc will do the
 shifts for you - this is particularly useful,
 for writes as that then cuts out a network operation (which would be
 needed to fetch the adjacent bits so that they aren't clobbered by the
 write).

 In the fpg file (or on the telnet connection), use optional [:bits] after
 an offset or a length to define the register - it is fine if such a
 register overlaps with something else, as long as the name is unique.

 The downside of all this: It isn't tested at all, as nobody is using it
 yet. And the code to make it work is a bit tricky - search for the
 read/write functions in
 https://github.com/ska-sa/katcp_devel/blob/master/tcpborphserver3/raw.c,
 for example write_cmd

 regards

 marc

[casper] casperfpga on a ROACH 1 - problem with get_system_information

[James Smith]

Hi all,

As per Paul's suggestion, I'm migrating towards using registers and snaps
with bit-fields in them, and casperfpga instead of corr for the computer
side of things. There was a minor problem with the program function, but
I fixed it (I think?) and my pull request is currently waiting for the
powers that be to deal with... https://github.com/ska-sa/casperfpga/pull/8
I'm fairly certain that this didn't break what I'm about to describe
because I've tried rolling back and the same error occurs.

The challenge I'm encountering is as follows: The ROACH is running
tcpborphserver2, which doesn't know what to do with .fpg files, so i have
to do a two-step process to get the image onto the FPGA and have the names
of the registers and the bit fields etc. to be able to use (either in
ipython or in a script):

fpga.program('filename.bof')
fpga.get_system_information('filename.fpg')

The first is the function that I fixed, and it seems to work. The second
line is where the problem comes in. I don't _think_ my fix (see the github
link above for details) has anything to do with it.

Here's the exception that ipython gives me:

In [5]: fpga.get_system_information('c09_2015_May_11_1559.fpg')
---
NotImplementedError   Traceback (most recent call last)
ipython-input-5-d3ea1b8990df in module()
 1 fpga.get_system_information('c09_2015_May_11_1559.fpg')

/usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
get_system_information(self, filename, fpg_info)
480 device_dict = self._read_design_info_from_host()
481 memorymap_dict = self._read_coreinfo_from_host()
-- 482 super(KatcpFpga,
self).get_system_information(fpg_info=(device_dict, memorymap_dict))
483
484 def unhandled_inform(self, msg):

/usr/local/lib/python2.7/dist-packages/casperfpga/casperfpga.pyc in
get_system_information(self, filename, fpg_info)
381 # reset current devices and create new ones from the new
design information
382 self.__reset_device_info()
-- 383 self.__create_memory_devices(device_dict, memorymap_dict)
384 self.__create_other_devices(device_dict)
385

/usr/local/lib/python2.7/dist-packages/casperfpga/casperfpga.pyc in
__create_memory_devices(self, device_dict, memorymap_dict)
308 if not callable(known_device_class):
309 raise TypeError('%s is not a callable Memory
class - that\'s a problem.' % known_device_class)
-- 310 new_device =
known_device_class.from_device_info(self, device_name, device_info,
memorymap_dict)
311 if new_device.name in self.memory_devices.keys():
312 raise NameError('Device called %s of type %s
already exists in devices list.' %

/usr/local/lib/python2.7/dist-packages/casperfpga/katadc.pyc in
from_device_info(cls, parent, device_name, device_info, memorymap_dict)
 34 :return: a KatAdc object
 35 
--- 36 raise NotImplementedError
 37 address, length = -1, -1
 38 for mem_name in memorymap_dict.keys():

NotImplementedError:

Other clues:
- In a previous (simpler) design which just turned on and off LEDs in
response to bitfields in a register, everything worked without a complaint.
In this round I added a katADC and a bitfield_snapshot block.
- If I try to use things in ipython after this exception is thrown, it
seems as though the fpg file was partially parsed - writing to the
registers seems to work (as far as I could tell) but reading from the
snapshot threw another exception and returned nothing.

Any simple ideas as to what the problem might be? Am I committing some
schoolboy error which I haven't noticed? Or is this likely more complex?


Regards,
James

Re: [casper] casperfpga on a ROACH 1 - problem with get_system_information

[James Smith]

Hello again, Casperites,

Further tracking of my challenge, I removed the KatADC from the model and
the problem went away. I'm not sure why that NotImplementedError is raised.

However, even with the KatADC gone, and after loading the system
information, I tried to read from a snapshot block and this is what I got:

In [23]: fpga.snapshots.led_snap_ss.read()
---
KatcpRequestError Traceback (most recent call last)
ipython-input-23-4835bbdb7b15 in module()
 1 fpga.snapshots.led_snap_ss.read()

/usr/local/lib/python2.7/dist-packages/casperfpga/snap.pyc in read(self,
**kwargs)
188 if kkey not in ['circular_capture', 'man_trig',
'man_valid', 'offset', 'timeout', 'arm']:
189 raise RuntimeError('Invalid option for snap read:
%s' % kkey)
*-- 190 rawdata, rawtime = self.read_raw(**kwargs)*
191 # processed =
self._process_data_no_construct(rawdata['data'])
192 processed = self._process_data(rawdata['data'])

/usr/local/lib/python2.7/dist-packages/casperfpga/snap.pyc in
read_raw(self, **kwargs)
212 arm = getkwarg('arm', True)
213 if arm:
*-- 214 self.arm(man_trig=man_trig, man_valid=man_valid,
offset=offset, circular_capture=circular_capture)*
215 # wait
216 done = False

/usr/local/lib/python2.7/dist-packages/casperfpga/snap.pyc in arm(self,
man_trig, man_valid, offset, circular_capture)
150
 (man_trig  1) +
151
 (man_valid  2) +
*-- 152
 (circular_capture  3)))*
153 self.control_registers['control']['register'].write_int((1 +
154
 (man_trig  1) +

/usr/local/lib/python2.7/dist-packages/casperfpga/register.pyc in
write_int(self, uintvalue, blindwrite, word_offset)
 87 Write an unsigned integer to this device using the fpga
client.
 88 
*--- 89 self.parent.write_int(device_name=self.name
http://self.name, integer=uintvalue, blindwrite=blindwrite,
word_offset=word_offset)*
 90
 91 def _write_common(self, **kwargs):

/usr/local/lib/python2.7/dist-packages/casperfpga/casperfpga.pyc in
write_int(self, device_name, integer, blindwrite, word_offset)
243 self.blindwrite(device_name, data, word_offset*4)
244 else:
*-- 245 self.write(device_name, data, word_offset*4)*
246 LOGGER.debug('write_int %8x to register %s at word offset
%d okay%s.'
247  % (integer, device_name, word_offset, '
(blind)' if blindwrite else ''))

/usr/local/lib/python2.7/dist-packages/casperfpga/casperfpga.pyc in
write(self, device_name, data, offset)
193 :return:
194 
*-- 195 self.blindwrite(device_name, data, offset)*
196 new_data = self.read(device_name, len(data), offset)
197 if new_data != data:

/usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
blindwrite(self, device_name, data, offset)
199 assert((offset % 4) == 0), 'You must write 32-bit-bounded
words!'
200 self.katcprequest(name='write',
request_timeout=self._timeout, require_ok=True,
*-- 201   request_args=(device_name, str(offset),
data))*
202
203 def bulkread(self, device_name, size, offset=0):

/usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
katcprequest(self, name, request_timeout, require_ok, request_args)
116 raise KatcpRequestError(
117 'Request %s on host %s failed.\n\tRequest:
%s\n\tReply: %s' %
*-- 118 (request.name http://request.name, self.host,
request, reply))*
119 return reply, informs
120

KatcpRequestError: Request write on host localhost failed.
Request: ?write led_snap_ss_ctrl 0 \0\0\0\0
Reply: !write fail register


Reading and writing other registers works just fine. Telnetting into the
ROACH and trying to write the snap_ss_ctrl register that way also fails, so
it's quite likely that the problem is not with the casperfpga module (the
snapshot one anyway, don't know about the KatADC one).

Could there be a problem with the toolflow perhaps? I checked out from
ska-sa/mlib-devel less than a month ago so it's fairly current. I think.

I'd be glad of any ideas or suggestions to perhaps point me in the right
direction?

Regards,
James


On Wed, May 13, 2015 at 4:19 PM, James Smith jsm...@ska.ac.za wrote:

 Hi all,

 As per Paul's suggestion, I'm migrating towards using registers and snaps
 with bit-fields in them, and casperfpga instead of corr for the computer
 side of things. There was a minor problem with the program function, but
 I fixed it (I think?) and my pull request is currently waiting for the
 powers that be to deal with... https://github.com/ska-sa/casperfpga/pull/8
 I'm fairly certain that this didn't break what I'm about to describe
 because I've tried rolling back

Re: [casper] System Compatibility

[James Smith]

Hi Victor,

We used to use Ubuntu 14.04, and it kind of worked, but it wasn't stable.
Switched to the most recent version of CentOS about a month ago and haven't
had problems since.

Xilinx v14.7, Matlab 2012b.

Regards,
James


On Wed, Jun 24, 2015 at 1:10 AM, Mark Wagner mwag...@ssl.berkeley.edu
wrote:

 Hi Victor,

 A list of supported operating systems is here on page 7:

 http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/irn.pdf

 If you need free, a much safer alternative to Ubuntu (but still
 unsupported) is CentOS 6.5, which is built from RHEL6 source packages.

 Mark



 On Tue, Jun 23, 2015 at 12:48 PM, Victor Cardoso 
 victorcardoso...@hotmail.com wrote:

 Greetings,

 I am working with the ROACH 2 in order to implement the MUSIC project. I
 am having a lot of troubles to compile the Tutorial 1 (Introduction to
 Simulink) due to mismatch between Xilinx ISE 14.5 and my Operating System,
 Ubuntu 10.04.
 I would like to know if it's possible to run this example using Ubuntu.
 Otherwise, I can install Redhat Enterprise Linux 6.3, Matlab 12b and Xilinx
 14.5 to run the codes.

 I look forward hearing from you.

 Best Regards,
 Victor Cardoso.

Re: [casper] Compiling error

[James Smith]

Hi Paul,

Thanks, I have found that script. I can't think of a way to go about
finding out which part it has a problem with though, except possibly
starting several different compiles, removing a component from each, and
seeing which ones pass / fail.

Is this a sound approach?

James


On Mon, Jun 1, 2015 at 10:34 AM, Paul Prozesky paul.proze...@gmail.com
wrote:

 Hi James

 Check the sblock_to_info script in the +design_info (no, the plus isn't a
 mistake, it's a matlab thing) folder in your xps_library folder. Something
 is that script is not happy with one of the blocks in your model file.

 Cheers
 Paul


 On 1 June 2015 at 10:27, James Smith jsm...@ska.ac.za wrote:

 Hi all,

 I'm working on a simple design for a two-stage high-resolution
 spectrometer, which almost gets finished compiling, sysgen seems to finish,
 and then at the end fails with a most uninformative error message:

 ##
 ## Creating EDK files   ##
 ##
 Error using design_info.sblock_to_info (line 18)
 Empty value?

 Anyone else seen this problem before? The sysgen*.log files contain
 basically zero information, and I've grepped for as many combinations of
 the design_info.sblock_to_info string as I can think of, to no avail.

 If anyone has some insight that can point me in the right direction, I'd
 appreciate it. I can send the .slx file to anyone who would like to look at
 it, I didn't think the mailing list would be an appropriate place to attach
 it (about 7 MB).

 Regards,
 James

[casper] Compiling error

[James Smith]

Hi all,

I'm working on a simple design for a two-stage high-resolution
spectrometer, which almost gets finished compiling, sysgen seems to finish,
and then at the end fails with a most uninformative error message:

##
## Creating EDK files   ##
##
Error using design_info.sblock_to_info (line 18)
Empty value?

Anyone else seen this problem before? The sysgen*.log files contain
basically zero information, and I've grepped for as many combinations of
the design_info.sblock_to_info string as I can think of, to no avail.

If anyone has some insight that can point me in the right direction, I'd
appreciate it. I can send the .slx file to anyone who would like to look at
it, I didn't think the mailing list would be an appropriate place to attach
it (about 7 MB).

Regards,
James

Re: [casper] Compiling error

[James Smith]

Hi Paul,

I wasn't sure what debug information I'd be able to get from this script
directly, but I found that it gets called by write_info_table.m in the same
folder.

So at around line 16 in the script I added a try .. catch around the call
to the sblock_to_info function, with e.stack and error(['Error occurred
when processing ', tag, '.'])

Should that tell me a little more info about where the problem occurs? Or
is there another more elegant way to get that information?

Regards,
James


On Mon, Jun 1, 2015 at 10:54 AM, Paul Prozesky paul.proze...@gmail.com
wrote:

 Hi James

 You can see that your error is happening in this section of that script:

 if isempty(strtrim(value)) == 1,
 error('Empty value?');
 end


 So add some debug logging there and rerun the gen_xps_add_design_info
 part of the build.

 Cheers
 Paul





 On 1 June 2015 at 10:39, James Smith jsm...@ska.ac.za wrote:

 Hi Paul,

 Thanks, I have found that script. I can't think of a way to go about
 finding out which part it has a problem with though, except possibly
 starting several different compiles, removing a component from each, and
 seeing which ones pass / fail.

 Is this a sound approach?

 James


 On Mon, Jun 1, 2015 at 10:34 AM, Paul Prozesky paul.proze...@gmail.com
 wrote:

 Hi James

 Check the sblock_to_info script in the +design_info (no, the plus isn't
 a mistake, it's a matlab thing) folder in your xps_library folder.
 Something is that script is not happy with one of the blocks in your model
 file.

 Cheers
 Paul


 On 1 June 2015 at 10:27, James Smith jsm...@ska.ac.za wrote:

 Hi all,

 I'm working on a simple design for a two-stage high-resolution
 spectrometer, which almost gets finished compiling, sysgen seems to finish,
 and then at the end fails with a most uninformative error message:

 ##
 ## Creating EDK files   ##
 ##
 Error using design_info.sblock_to_info (line 18)
 Empty value?

 Anyone else seen this problem before? The sysgen*.log files contain
 basically zero information, and I've grepped for as many combinations of
 the design_info.sblock_to_info string as I can think of, to no avail.

 If anyone has some insight that can point me in the right direction,
 I'd appreciate it. I can send the .slx file to anyone who would like to
 look at it, I didn't think the mailing list would be an appropriate place
 to attach it (about 7 MB).

 Regards,
 James

Re: [casper] Compiling error

[James Smith]

Hi all,

Matt - thanks, that fix seems to have worked. The design gets past this
now, ultimately to fail because it's too big for the device... but that's
another story.

Paul - I don't have that much familiarity with Matlab (I presume the debug
logging to which you're referring is a Matlab feature?). Thanks for that -
I'll fetch the latest changes from Github and see what you've put in. Will
report whether it helps soon.

Regards,
James


On Tue, Jun 2, 2015 at 12:06 PM, Paul Prozesky paul.proze...@gmail.com
wrote:

 Morning James

 I've added some more debugging to the script, so check out the latest
 version.

 Have you used the debug logging before? Try setting:

 casper_log_groups={'all'}

 And rerunning your scripts.

 Cheers
 Paul



 On 1 June 2015 at 15:24, James Smith jsm...@ska.ac.za wrote:

 Hi Paul,

 I wasn't sure what debug information I'd be able to get from this script
 directly, but I found that it gets called by write_info_table.m in the same
 folder.

 So at around line 16 in the script I added a try .. catch around the
 call to the sblock_to_info function, with e.stack and error(['Error
 occurred when processing ', tag, '.'])

 Should that tell me a little more info about where the problem occurs? Or
 is there another more elegant way to get that information?

 Regards,
 James


 On Mon, Jun 1, 2015 at 10:54 AM, Paul Prozesky paul.proze...@gmail.com
 wrote:

 Hi James

 You can see that your error is happening in this section of that script:

 if isempty(strtrim(value)) == 1,
 error('Empty value?');
 end


 So add some debug logging there and rerun the gen_xps_add_design_info
 part of the build.

 Cheers
 Paul





 On 1 June 2015 at 10:39, James Smith jsm...@ska.ac.za wrote:

 Hi Paul,

 Thanks, I have found that script. I can't think of a way to go about
 finding out which part it has a problem with though, except possibly
 starting several different compiles, removing a component from each, and
 seeing which ones pass / fail.

 Is this a sound approach?

 James


 On Mon, Jun 1, 2015 at 10:34 AM, Paul Prozesky paul.proze...@gmail.com
  wrote:

 Hi James

 Check the sblock_to_info script in the +design_info (no, the plus
 isn't a mistake, it's a matlab thing) folder in your xps_library folder.
 Something is that script is not happy with one of the blocks in your model
 file.

 Cheers
 Paul


 On 1 June 2015 at 10:27, James Smith jsm...@ska.ac.za wrote:

 Hi all,

 I'm working on a simple design for a two-stage high-resolution
 spectrometer, which almost gets finished compiling, sysgen seems to 
 finish,
 and then at the end fails with a most uninformative error message:

 ##
 ## Creating EDK files   ##
 ##
 Error using design_info.sblock_to_info (line 18)
 Empty value?

 Anyone else seen this problem before? The sysgen*.log files contain
 basically zero information, and I've grepped for as many combinations of
 the design_info.sblock_to_info string as I can think of, to no avail.

 If anyone has some insight that can point me in the right direction,
 I'd appreciate it. I can send the .slx file to anyone who would like to
 look at it, I didn't think the mailing list would be an appropriate place
 to attach it (about 7 MB).

 Regards,
 James

Re: [casper] casperfpga on a ROACH 1 - problem with get_system_information

[James Smith]

Hi all,

For the information of anyone else who might encounter a similar problem to
what I did - the NotImplementedError means that the device just wasn't
implemented in casperfpga yet. In this case though it didn't really need to
be because the katadc is pretty simple compared with newer meerkatADC (from
what I understood).

This caused the get_sytem_information() function to bomb and not finish
processing the snapshot blocks, which is why they weren't working.

I've made a small change to the code and submitted a pull request, so it
should be fixed for katadc in the future, but if anyone else comes across
similar problems then that might be a good place to start looking for a
solution.

Regards,
James


On Tue, May 19, 2015 at 12:49 PM, James Smith jsm...@ska.ac.za wrote:

 Hello again, Casperites,

 Further tracking of my challenge, I removed the KatADC from the model and
 the problem went away. I'm not sure why that NotImplementedError is raised.

 However, even with the KatADC gone, and after loading the system
 information, I tried to read from a snapshot block and this is what I got:

 In [23]: fpga.snapshots.led_snap_ss.read()
 ---
 KatcpRequestError Traceback (most recent call last)
 ipython-input-23-4835bbdb7b15 in module()
  1 fpga.snapshots.led_snap_ss.read()

 /usr/local/lib/python2.7/dist-packages/casperfpga/snap.pyc in read(self,
 **kwargs)
 188 if kkey not in ['circular_capture', 'man_trig',
 'man_valid', 'offset', 'timeout', 'arm']:
 189 raise RuntimeError('Invalid option for snap read:
 %s' % kkey)
 *-- 190 rawdata, rawtime = self.read_raw(**kwargs)*
 191 # processed =
 self._process_data_no_construct(rawdata['data'])
 192 processed = self._process_data(rawdata['data'])

 /usr/local/lib/python2.7/dist-packages/casperfpga/snap.pyc in
 read_raw(self, **kwargs)
 212 arm = getkwarg('arm', True)
 213 if arm:
 *-- 214 self.arm(man_trig=man_trig, man_valid=man_valid,
 offset=offset, circular_capture=circular_capture)*
 215 # wait
 216 done = False

 /usr/local/lib/python2.7/dist-packages/casperfpga/snap.pyc in arm(self,
 man_trig, man_valid, offset, circular_capture)
 150
  (man_trig  1) +
 151
  (man_valid  2) +
 *-- 152
  (circular_capture  3)))*
 153 self.control_registers['control']['register'].write_int((1
 +
 154
  (man_trig  1) +

 /usr/local/lib/python2.7/dist-packages/casperfpga/register.pyc in
 write_int(self, uintvalue, blindwrite, word_offset)
  87 Write an unsigned integer to this device using the fpga
 client.
  88 
 *--- 89 self.parent.write_int(device_name=self.name
 http://self.name, integer=uintvalue, blindwrite=blindwrite,
 word_offset=word_offset)*
  90
  91 def _write_common(self, **kwargs):

 /usr/local/lib/python2.7/dist-packages/casperfpga/casperfpga.pyc in
 write_int(self, device_name, integer, blindwrite, word_offset)
 243 self.blindwrite(device_name, data, word_offset*4)
 244 else:
 *-- 245 self.write(device_name, data, word_offset*4)*
 246 LOGGER.debug('write_int %8x to register %s at word offset
 %d okay%s.'
 247  % (integer, device_name, word_offset, '
 (blind)' if blindwrite else ''))

 /usr/local/lib/python2.7/dist-packages/casperfpga/casperfpga.pyc in
 write(self, device_name, data, offset)
 193 :return:
 194 
 *-- 195 self.blindwrite(device_name, data, offset)*
 196 new_data = self.read(device_name, len(data), offset)
 197 if new_data != data:

 /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
 blindwrite(self, device_name, data, offset)
 199 assert((offset % 4) == 0), 'You must write 32-bit-bounded
 words!'
 200 self.katcprequest(name='write',
 request_timeout=self._timeout, require_ok=True,
 *-- 201   request_args=(device_name, str(offset),
 data))*
 202
 203 def bulkread(self, device_name, size, offset=0):

 /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
 katcprequest(self, name, request_timeout, require_ok, request_args)
 116 raise KatcpRequestError(
 117 'Request %s on host %s failed.\n\tRequest:
 %s\n\tReply: %s' %
 *-- 118 (request.name http://request.name, self.host,
 request, reply))*
 119 return reply, informs
 120

 KatcpRequestError: Request write on host localhost failed.
 Request: ?write led_snap_ss_ctrl 0 \0\0\0\0
 Reply: !write fail register


 Reading and writing other registers works just fine. Telnetting into the
 ROACH and trying to write the snap_ss_ctrl register that way also fails, so
 it's quite likely that the problem

Re: [casper] Communicating to ROACH 2

[James Smith]

Hello Victor,

Are you planning on using telnet or python? If python, check out the
casperfpga module on ska-sa Github. It's not documented in the tutorials
unfortunately, and it takes a little bit of doing to install, but once
you're there it's very easy to us, especially with ipython.

I've recently gone through a similar process with ROACH 1, so if you don't
come right by tomorrow I (or someone more experienced than I) can give you
some more direction tomorrow...

Regards,
James


On Tue, Jul 28, 2015 at 8:57 PM, Victor Cardoso 
victorcardoso...@hotmail.com wrote:

 Hello everybody,

 I'm writing to ask you some detailed guidance to communicate my linux PC
 to the Roach 2 board.
 I have the Simulink project compiled successfully and I'm able to watch
 the u-boot process on minicom terminal. However, I don't know how to
 proceed at this point.
 May anybody provide basic information about this issue? The pieces of
 information from some tutorials at CASPER website weren't enough for me.

 Thank you in advance,
 Victor Cardoso.

Re: [casper] ROCH 2 communication through Python

[James Smith]

Hello Aniket,

casperfpga is the one you want:
https://github.com/ska-sa/casperfpga

It has a few dependencies to build, but it's much nicer than corr.

Regards,
James


On Tue, Sep 1, 2015 at 11:39 AM, aniket 
wrote:

> Dear CASPER colleagues,
>
> Myself Aniket Hendre working as a Project Engineer-C in Giant Metrewave
> Radio Telescope (GMRT), India.
>
> I am using ROACH 2 for my experiments. I have executed some modular design
> on ROACH 2 successfully.
>
> Now I am facing problem to communicate with ROACH 2 using Python
> environment. I have communicated with ROACH 2 successfully using telnet.
>
> Like for ROACH 1 Corr package any one knows package for ROACH 2 ?
>
> Please guide me regarding the same.
>
> Thanks and Regards,
>
> ANIKET S. HENDRE
> Project Engineer -C,
> Giant Metrewave Radio Telescope,
> The National Centre for Radio Astrophysics,
> Khodad, Pune,
> Maharashtra 410504.
> Tel:- 02132-258365.
> Web: www.ncra.tifr.res.in
>
>

Re: [casper] ROCH 2 communication through Python

[James Smith]

Hello Aniket,

I'm puzzled by your problem, but I have no experience using a ROACH2.
Perhaps the authors of the casperfpga module will be able to give further
debugging suggestions.

Regards,
James


On Wed, Sep 2, 2015 at 12:40 PM, aniket <ani...@gmrt.ncra.tifr.res.in>
wrote:

> On 2015-09-02 12:22, Craig Tong wrote:
>
>> Hi Aniket.
>>
>> As James has said, if you have been making various telnet connections to
>> your Roach2 before running the script it might be worth just rebooting
>> the board before trying the casperFPGA scripts. The tcpborphserver may
>> have crashed due to receiving some commands it didn't like.
>>
>> Kind regards.
>> Craig
>>
>> On 2015-09-02 08:18, aniket wrote:
>>
>>> On 2015-09-02 11:28, James Smith wrote:
>>>
>>>> Hello Aniket,
>>>>
>>>> You seem to have gone about it the right way. That error usually means
>>>> that either your ROACH isn't connected or the tcpborphserver running
>>>> on the ROACH has crashed. Also, check the spelling of your ROACH's
>>>> name.
>>>>
>>>> I myself use ROACH1, not ROACH2 (in fact I had to modify casperfpga
>>>> slightly to work with ROACH), so if you don't come right, reply to the
>>>> group again (you can just do a "reply-all" to my previous mail), and
>>>> some of those more experienced in using ROACH2 may be able to help
>>>> you.
>>>>
>>>> Regards,
>>>> James
>>>>
>>>> On Wed, Sep 2, 2015 at 7:35 AM, aniket <ani...@gmrt.ncra.tifr.res.in>
>>>> wrote:
>>>>
>>>> On 2015-09-01 15:21, James Smith wrote:
>>>>> Hello Aniket,
>>>>>
>>>>> casperfpga is the one you want:
>>>>> https://github.com/ska-sa/casperfpga [1] [2]
>>>>>
>>>>> It has a few dependencies to build, but it's much nicer than corr.
>>>>>
>>>>> Regards,
>>>>> James
>>>>>
>>>>> On Tue, Sep 1, 2015 at 11:39 AM, aniket
>>>>> <ani...@gmrt.ncra.tifr.res.in>
>>>>> wrote:
>>>>>
>>>>> Dear CASPER colleagues,
>>>>>
>>>>> Myself Aniket Hendre working as a Project Engineer-C in Giant
>>>>> Metrewave Radio Telescope (GMRT), India.
>>>>>
>>>>> I am using ROACH 2 for my experiments. I have executed some modular
>>>>> design on ROACH 2 successfully.
>>>>>
>>>>> Now I am facing problem to communicate with ROACH 2 using Python
>>>>> environment. I have communicated with ROACH 2 successfully using
>>>>> telnet.
>>>>>
>>>>> Like for ROACH 1 Corr package any one knows package for ROACH 2 ?
>>>>>
>>>>> Please guide me regarding the same.
>>>>>
>>>>> Thanks and Regards,
>>>>>
>>>>> ANIKET S. HENDRE
>>>>> Project Engineer -C,
>>>>> Giant Metrewave Radio Telescope,
>>>>> The National Centre for Radio Astrophysics,
>>>>> Khodad, Pune,
>>>>> Maharashtra 410504.
>>>>> Tel:- 02132-258365.
>>>>> Web: www.ncra.tifr.res.in [2] [1]
>>>>>
>>>>> Links:
>>>>> --
>>>>> [1] http://www.ncra.tifr.res.in [2]
>>>>> [2] https://github.com/ska-sa/casperfpga [1]
>>>>>
>>>>  Dear James,
>>>>
>>>> Thanks for the replay. I have clone the casperfpga and installed on my
>>>> machine. First I just want check that my ROACH2 has been connected to
>>>> my PC. So from the modular script which is there in casperfpga
>>>> directory I have extracted a required part. But still I am getting
>>>> error. The statement which I am executing in ipython is as follows.
>>>>
>>>> In [8]: #!/usr/bin/env python
>>>>
>>>> In [9]: from casperfpga import katcp_fpga
>>>>
>>>> In [10]: HOSTCLASS = katcp_fpga.KatcpFpga
>>>>
>>>> In [11]: fpga = HOSTCLASS('roach02082A', 7147)
>>>>
>>>> ---
>>>>
>>>> KatcpRequestError Traceback (most recent call
>>>> last)
>>>>  in ()
>>>> > 1 fpga = HOSTCLASS('roach02082A', 7147)
>>>>
>>>> /usr/loca

[casper] Presenting RoachRegisterMonitor GUI

[James Smith]

Hello all,

I've put together a little Qt GUI in python for monitoring what's going on
on a ROACH. It should work on a ROACH2 as well, but I don't have one to
test it.

If anyone would like to use it, it can be found here:
https://github.com/james-smith-za/RoachRegisterMonitor

Maybe someone will find it useful.

Regards,
James

Re: [casper] Spectrum issues

[James Smith]

Something we've had with PFBs and FFTs is that they don't resize properly
if you simply change their length in a design. It may be worth deleting
them and putting new ones.
On 12 Sep 2015 20:03, "Danny Price"  wrote:

> Hi Michael
>
> I always blame the sync gen first! I’d suggest just sending out a single
> pulse to reset the logic, not a heartbeat, at least to begin with, to rule
> this out. Jack’s suggestion that it might be the addressing of the shared
> BRAM is definitely a possibility too.
>
> It’s very easy for the FFT to become broken if you’re using an unstable
> github branch. I’d suggest testing the FFT by itself in its own simulink
> model. You can use the blackbox tutorial setup as a starting point, and
> then add in some test vectors. The easiest test vector is a delta function,
> e.g. [0 0 1 0 0 … 0]. The FFT will take the FT of this, which will be a
> sine wave if you look at the real/imag components separately (take the
> power and you’ll get back a DC signal), where the frequency of the wave
> will depend on where the delta is.
>
> The test procedure in this case is to connect up a scope to the output and
> just look to see if you get a sine wave out, your eye will be able to tell
> if it’s a major bug. Once you’ve got it simulating, blackbox it up and then
> you don’t have to worry.
>
> Also look out for toolflow version mismatches. As Jack (et al) have just
> updated the casper_astro repository, I’d suggest using that:
> https://github.com/casper-astro/mlib_devel
> Make sure to run update_casper_blocks(gcs) on your design. Deleting and
> redrawing the FFT from scratch isn’t a bad idea either.
>
> Once you’ve got it simulating OK, here’s some other general tips for
> spectrometer that I started writing before reading your email properly:
>
> * One of the first things I’d do is play around with the shift schedule. A
> 2^15 point FFT will have 15 stages, and shifting every stage will probably
> shift your signal into oblivion. It doesn’t look to me like you have
> overflows (generally lots of spikes everywhere), but overshifting can also
> be detrimental. Maybe try writing 0b1110 or so, so you shift the
> first N stages only (someone may have a more rigorous approach/strategy?).
>
> * It’s also important to check that your RMS input from the digitizer
> isn’t too high. Even with RFI, having an RMS of 32 or below on an 8-bit ADC
> would be good. A good reference for this is: A. R. Thompson, D. T. Emerson,
> and F. R. Schwab, “Convenient formulas for quantization efficiency,” Radio
> Science, vol. 42, p. 3022, Jun. 2007 (Just read the last paragraph if
> you’re pressed for time!). You can compute the RMS by looking at raw ADC
> samples (use a snapshot block)
>
> * An approach I’ve found useful for debugging is looking at your data in
> terms of bits — i.e. take the log2 of your data. This can help find
> quantization and saturation issues. In the tut3_spectrum.png, all the RFI
> spikes are suspiciously similar heights, which I would guess is due to
> saturation or quantization somewhere along the line.
>
> Cheers
> Danny
>
> On Sep 12, 2015, at 9:34 AM, Michael D'Cruze <
> michael.dcr...@postgrad.manchester.ac.uk> wrote:
>
> Hi everyone,
>
>
> I’m having quite a lot of trouble getting large-ish designs (16k channels)
> to produce spectra. The spectra that are being produced are quite strange.
> I’ve provided links below to a few examples. The first link is the spectrum
> produced by the unmodified tut3 model (except for the ADC and FPGA clocks
> increased to 1024 MHz and 256 MHz, respectively). It’s pretty much as you’d
> expect – a bog-standard L-band spectrum full of RFI. The second link is
> what happens when I try to increase the number of channels to 16k. As you
> can see, I can pull 16k channels from the board, but there are no actual
> data in there, beyond the original 2k channels. All the usual blocks were
> modified to get the model to work at 16k channels: the #PFB and #FFT points
> increased to 32768, the vector length in the VACC increased to 8192, the
> sync_gen block (using for now before changing to a PPS-based system)
> adjusted, and the shared_brams adjusted for longer address length. The
> third link is a zoomed-in image of the same spectrum, just to show that
> there is a partial spectrum in there. The fourth link is what comes out
> when I replace the FFT and PFB blocks with black-boxes… where the
> pre-compiled PFB and FFT blocks have the same settings as in the previous
> spectra….! The inconsistency between compiling with “raw” blocks and
> pre-compiled blocks is another source of concern.
>
>
> https://dl.dropboxusercontent.com/u/38103354/tut3_spectrum.png
>
> https://dl.dropboxusercontent.com/u/38103354/tut3_mod3_correct.png
>
> https://dl.dropboxusercontent.com/u/38103354/tut3_mod3.png
>
> https://dl.dropboxusercontent.com/u/38103354/tut3_mod2.png
>
>
> I can also make my models available if anyone would like. If I were to
> list 

Re: [casper] building 300-receiver channel cross-correlator

[James Smith]

Hello Neil,

CASPER tools could probably do what you're looking for, but I found your
description a bit confusing. You're going to need to clarify somewhat.

Regards,
James


On Fri, Dec 18, 2015 at 4:15 PM, Neil Salmon  wrote:

> Anyone help?
>
>
>
> I’m working in academia and need to build a 300-receiver channel
> single-bit digitiser / cross-correlator with a single frequency channel
> having a bandwidth of 300 MHz, centre frequency ~3 GHz. The single bit
> digitisers sample I giving a total data rate of 180 Gbps and using XOR
> gates to do the cross-correlations, the total computation rate is 54 T XOR
> operations per second. I need to accumulate cross-correlations typically
> for times ranging from 10 ms to a few seconds. The system would comprise an
> array of single bit digitisers linked via a high speed data bus to FPGA
> boards for the cross-correlation/accumulation. I’ve no skills in board
> design but could probably learn VHDL. I don’t have funding to commission a
> design and build but wondered if anyone in this community could advise how
> I should go about building this system at our university.
>
>
>
> Thank you for any help you can provide.
>
>
>
> Neil
> "Before acting on this email or opening any attachments you should read
> the Manchester Metropolitan University email disclaimer available on its
> website http://www.mmu.ac.uk/emaildisclaimer "
>

[casper] 2016 Workshop archive

[James Smith]

Hi all,

Are the presentations from the 2016 workshop going to be made available at
all?

I'd be keen to review some of the things that I saw there.

Regards,
James

Re: [casper] Sysgen compilation error

[James Smith]

Haven't encountered that specific issue before but I see a capital letter
in your path. That may be an issue.
On 11 Feb 2016 12:44, "Mugundhan vijayaraghavan" 
wrote:

> Hello guys,
>
> I'm running matlab/xilinx and mssge tools on a ubuntu 14.04 system. When I
> do casper_xps and start compiling, I get this strange error.
>
> standard exception: XNetlistEngine:
> Exception message could not be parsed:
> com.xilinx.sysgen.netlist.NetlistInternal: couldn't open first pass text
> file at
> /home/mugundhan/casper_designs/tut1/sysgen/sysgen/masterScript3888976111602024584.pl
> line 559'
>
>
> Reported by:
> Unspecified
>
> Has anyone got this before ?
>
> Is there any workaround ?
>
>
> --
> the giver of moksha
>

[casper] KatADC impedance values

[James Smith]

Hi all,

Is there any reason to believe that the input on the KatADC board (or any
ADC board which we might end up using) is not a 50-ohm? How would one go
about determining that? The wiki says nothing about its VSWR or related
information.

Any thoughts would be appreciated.

Regards,
James

Re: [casper] fft_biplex_real_2x

[James Smith]

Hi Rolando,

I can't recall that it does, off the top of my head, but the Casper one can
be set up to use just one input. This is what I've done in the past, I
think.

Regards,
James


On Wed, Jan 20, 2016 at 7:39 AM, Rolando Paz  wrote:

> Hi James and Andrew
>
> Thank for yours advices.
>
> I'm trying to recompile the design of Peter McMahon:
> https://casper.berkeley.edu/wiki/Parspec
>
> I'm using these libraries:
>
> https://github.com/casper-astro/mlib_devel/tree/mlib_devel-2010-09-20
>
> and I use a virtual machine "windows XP SP3", on ubuntu 14.04LTS, Matlab
> R2007b,
> ISE, EDK, SG 10.1, with respective updates, IBOB+QUADC.
>
> With this configuration, I can not compile this new design.
>
> I'll try with Xilinx FFT...
> Is there a Xilinx block version for the PFB too?
>
> Thank you.
>
>
>
> 2016-01-19 23:23 GMT-06:00 Andrew Martens :
>
>> Hi Rolando
>>
>> You may want to look at the Xilinx FFT for your use case. The CASPER FFT
>> is optimised so that minimal resources are used when processing high
>> bandwidths (either many inputs, or inputs captured at high sample rates).
>> In this case you may find that the Xilinx FFT actually uses fewer
>> resources.
>>
>> Regards
>> Andrew
>>
>> On Tue, Jan 19, 2016 at 11:11 PM, Rolando Paz  wrote:
>>
>>> Hi
>>>
>>> Is there any other FFT block that I can use with ADC4x250-8?
>>>
>>> https://casper.berkeley.edu/wiki/ADC4x250-8
>>>
>>> I am using the "fft_biplex_real_2x" block, however I need only one input
>>> of the four that this block has. I placed at zero the others three inputs.
>>>
>>> I need more FPGA resources from IBOB, and I think using another FFT
>>> block may be one solution.
>>>
>>> Best Regards
>>>
>>> RP
>>>
>>
>>
>

Re: [casper] fft_biplex_real_2x

[James Smith]

Hi Rolando,

Have you tried one of the built-in Xilinx FFTs? As far as I know, the
Casper ones really only exist because the Xilinx ones only accept one input
at a time.

If you do use them, they are really efficient with resources.

Regards,
James


On Tue, Jan 19, 2016 at 11:11 PM, Rolando Paz  wrote:

> Hi
>
> Is there any other FFT block that I can use with ADC4x250-8?
>
> https://casper.berkeley.edu/wiki/ADC4x250-8
>
> I am using the "fft_biplex_real_2x" block, however I need only one input
> of the four that this block has. I placed at zero the others three inputs.
>
> I need more FPGA resources from IBOB, and I think using another FFT block
> may be one solution.
>
> Best Regards
>
> RP
>

Re: [casper] fft_biplex_real_2x

[James Smith]

Hi Rolando,

I'll refer you to Xilinx Sysgen's reference documents. You should be able
to get them from their website. They contain all the info you need about
those blocks.

The different FFT versions will depend on your board - I'm not familiar
with the iBOB, so I'm not sure which FPGA it has on it, but the older FPGAs
don't support the newer FFT designs.

You can set it up depending on your needs - speed or space. I'd suggest
doing a few simulations to get a feel for how the various FFTs work. These
don't take too long and will give you a good feel for what's available.

Regards,
James


On Wed, Jan 20, 2016 at 3:40 PM, Rolando Paz <flx...@gmail.com> wrote:

> Hi
>
> In the attached picture you can see the fft xilinx blocks I found.
>
> Which one should I use?
> How should I set this block?
>
>
> 2016-01-20 3:06 GMT-06:00 Ryan Monroe <ryan.m.mon...@gmail.com>:
>
>> I don't use the stock CASPER FFTs anymore, but I'm pretty sure that
>> there's no way to use them for anything less than {2 complex inputs --OR--
>> 4 real inputs}.  If you want less, you can drive an input with a constant
>> '0', but resource-wise, they're the same.  This is because of algorithmic
>> limitations; there is a resource efficiency you gain by doing two complex
>> FFTs at once.
>>
>> This is a time for a streaming Xilinx FFT.
>>
>> --Ryan
>>
>>
>> On 01/19/2016 09:49 PM, James Smith wrote:
>>
>> Hi Rolando,
>>
>> I can't recall that it does, off the top of my head, but the Casper one
>> can be set up to use just one input. This is what I've done in the past, I
>> think.
>>
>> Regards,
>> James
>>
>>
>> On Wed, Jan 20, 2016 at 7:39 AM, Rolando Paz <flx...@gmail.com> wrote:
>>
>>> Hi James and Andrew
>>>
>>> Thank for yours advices.
>>>
>>> I'm trying to recompile the design of Peter McMahon:
>>> https://casper.berkeley.edu/wiki/Parspec
>>>
>>> I'm using these libraries:
>>>
>>> https://github.com/casper-astro/mlib_devel/tree/mlib_devel-2010-09-20
>>>
>>> and I use a virtual machine "windows XP SP3", on ubuntu 14.04LTS, Matlab
>>> R2007b,
>>> ISE, EDK, SG 10.1, with respective updates, IBOB+QUADC.
>>>
>>> With this configuration, I can not compile this new design.
>>>
>>> I'll try with Xilinx FFT...
>>> Is there a Xilinx block version for the PFB too?
>>>
>>> Thank you.
>>>
>>>
>>>
>>> 2016-01-19 23:23 GMT-06:00 Andrew Martens < <and...@ska.ac.za>
>>> and...@ska.ac.za>:
>>>
>>>> Hi Rolando
>>>>
>>>> You may want to look at the Xilinx FFT for your use case. The CASPER
>>>> FFT is optimised so that minimal resources are used when processing high
>>>> bandwidths (either many inputs, or inputs captured at high sample rates).
>>>> In this case you may find that the Xilinx FFT actually uses fewer
>>>> resources.
>>>>
>>>> Regards
>>>> Andrew
>>>>
>>>> On Tue, Jan 19, 2016 at 11:11 PM, Rolando Paz <flx...@gmail.com> wrote:
>>>>
>>>>> Hi
>>>>>
>>>>> Is there any other FFT block that I can use with ADC4x250-8?
>>>>>
>>>>> https://casper.berkeley.edu/wiki/ADC4x250-8
>>>>>
>>>>> I am using the "fft_biplex_real_2x" block, however I need only one
>>>>> input of the four that this block has. I placed at zero the others three
>>>>> inputs.
>>>>>
>>>>> I need more FPGA resources from IBOB, and I think using another FFT
>>>>> block may be one solution.
>>>>>
>>>>> Best Regards
>>>>>
>>>>> RP
>>>>>
>>>>
>>>>
>>>
>>
>>
>

Re: [casper] Sysgen compilation error

[James Smith]

Mugundhan,

The fpg file is intended for ROACH2 and tcpborphserver3 - you can safely
ignore it, but it's useful for some extra features.

If you use the casperfpga library (https://github.com/ska-sa/casperfpga)
instead of the old corr library, then you can successfully program the
ROACH.

The procedure for using it is not 100% the same - you'd use the following
commands:

import casperfpga
fpga = casperfpga.katcp_fpga.KatcpFpga('roachname')
fpga.system_info['program_filename'] = '%s.bof' % gateware #bof needs to be
on the roachfs for this to work
fpga.program()
fpga.get_system_information('%s.fpg' % gateware) % fpg file needs to be in
the current directory

There are some more cool things that you can do with the new casperfpga
library, I can try to summarize them a bit later if you need, but you can
learn a lot by playing around with it.

Regards,
James


On Mon, Feb 15, 2016 at 8:56 AM, Mugundhan vijayaraghavan <
v.vaishnav151...@gmail.com> wrote:

> Hello again,
>
> I have the latest ska-sa mlib devel installed. With this, I'm able to
> compile the model file and the bof files are created. There is also a new
> file with the format .fpg created. During my previous compilation cycle,
> with older mlib-devel, (probably june 2015 version) the .fpg file is not
> created. Secondly, if I burn the bof file created with the new mlib-devel
> using progdev() function, the roach 1 is not getting programmed. Can
> someone guide me as to what am I missing here ? and also, what is the .fpg
> file ? what is it used for ?
>
> Thank you,
>
> Mugundhan
>
> On Thu, Feb 11, 2016 at 8:06 PM, Mugundhan vijayaraghavan <
> v.vaishnav151...@gmail.com> wrote:
>
>> Hello Wesley, James,
>>
>> It was an issue with the shell scripting in ubuntu only. once I changed
>> dash to bash, things started working !
>>
>> Thanks to you guys :)
>>
>> On Thu, Feb 11, 2016 at 4:35 PM, Wesley New <wes...@ska.ac.za> wrote:
>>
>>> This is an issue with dash in ubuntu, if you change your shell from dash
>>> to bash it interprets the perl scripts properly.
>>>
>>> Have you followed these steps when setting up your tools flow?
>>> https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilinx_14.x_and_Matlab_2012b
>>>
>>> Particularly this step:
>>>
>>> The syntax in the Xilinx Perl scripts is not supported under the Ubuntu
>>> default shell Dash. Change the symbolic link sh -> dash to sh -> bash:
>>>
>>>- cd /bin/
>>>- sudo rm sh
>>>- sudo ln -s bash sh
>>>
>>>
>>> Wesley New
>>> South African SKA Project
>>> +2721 506 7300
>>> www.ska.ac.za
>>>
>>>
>>>
>>> On Thu, Feb 11, 2016 at 12:58 PM, James Smith <jsm...@ska.ac.za> wrote:
>>>
>>>> Haven't encountered that specific issue before but I see a capital
>>>> letter in your path. That may be an issue.
>>>> On 11 Feb 2016 12:44, "Mugundhan vijayaraghavan" <
>>>> v.vaishnav151...@gmail.com> wrote:
>>>>
>>>>> Hello guys,
>>>>>
>>>>> I'm running matlab/xilinx and mssge tools on a ubuntu 14.04 system.
>>>>> When I do casper_xps and start compiling, I get this strange error.
>>>>>
>>>>> standard exception: XNetlistEngine:
>>>>> Exception message could not be parsed:
>>>>> com.xilinx.sysgen.netlist.NetlistInternal: couldn't open first pass
>>>>> text file at
>>>>> /home/mugundhan/casper_designs/tut1/sysgen/sysgen/masterScript3888976111602024584.pl
>>>>> line 559'
>>>>>
>>>>>
>>>>> Reported by:
>>>>> Unspecified
>>>>>
>>>>> Has anyone got this before ?
>>>>>
>>>>> Is there any workaround ?
>>>>>
>>>>>
>>>>> --
>>>>> the giver of moksha
>>>>>
>>>>
>>>
>>
>>
>> --
>> the giver of moksha
>>
>
>
>

Re: [casper] Sysgen compilation error

[James Smith]

I should probably mention - clone casperfpga from the "devel" branch, not
"master".


On Mon, Feb 15, 2016 at 9:13 AM, James Smith <jsm...@ska.ac.za> wrote:

> Mugundhan,
>
> The fpg file is intended for ROACH2 and tcpborphserver3 - you can safely
> ignore it, but it's useful for some extra features.
>
> If you use the casperfpga library (https://github.com/ska-sa/casperfpga)
> instead of the old corr library, then you can successfully program the
> ROACH.
>
> The procedure for using it is not 100% the same - you'd use the following
> commands:
>
> import casperfpga
> fpga = casperfpga.katcp_fpga.KatcpFpga('roachname')
> fpga.system_info['program_filename'] = '%s.bof' % gateware #bof needs to
> be on the roachfs for this to work
> fpga.program()
> fpga.get_system_information('%s.fpg' % gateware) % fpg file needs to be in
> the current directory
>
> There are some more cool things that you can do with the new casperfpga
> library, I can try to summarize them a bit later if you need, but you can
> learn a lot by playing around with it.
>
> Regards,
> James
>
>
> On Mon, Feb 15, 2016 at 8:56 AM, Mugundhan vijayaraghavan <
> v.vaishnav151...@gmail.com> wrote:
>
>> Hello again,
>>
>> I have the latest ska-sa mlib devel installed. With this, I'm able to
>> compile the model file and the bof files are created. There is also a new
>> file with the format .fpg created. During my previous compilation cycle,
>> with older mlib-devel, (probably june 2015 version) the .fpg file is not
>> created. Secondly, if I burn the bof file created with the new mlib-devel
>> using progdev() function, the roach 1 is not getting programmed. Can
>> someone guide me as to what am I missing here ? and also, what is the .fpg
>> file ? what is it used for ?
>>
>> Thank you,
>>
>> Mugundhan
>>
>> On Thu, Feb 11, 2016 at 8:06 PM, Mugundhan vijayaraghavan <
>> v.vaishnav151...@gmail.com> wrote:
>>
>>> Hello Wesley, James,
>>>
>>> It was an issue with the shell scripting in ubuntu only. once I changed
>>> dash to bash, things started working !
>>>
>>> Thanks to you guys :)
>>>
>>> On Thu, Feb 11, 2016 at 4:35 PM, Wesley New <wes...@ska.ac.za> wrote:
>>>
>>>> This is an issue with dash in ubuntu, if you change your shell from
>>>> dash to bash it interprets the perl scripts properly.
>>>>
>>>> Have you followed these steps when setting up your tools flow?
>>>> https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilinx_14.x_and_Matlab_2012b
>>>>
>>>> Particularly this step:
>>>>
>>>> The syntax in the Xilinx Perl scripts is not supported under the Ubuntu
>>>> default shell Dash. Change the symbolic link sh -> dash to sh -> bash:
>>>>
>>>>- cd /bin/
>>>>- sudo rm sh
>>>>- sudo ln -s bash sh
>>>>
>>>>
>>>> Wesley New
>>>> South African SKA Project
>>>> +2721 506 7300
>>>> www.ska.ac.za
>>>>
>>>>
>>>>
>>>> On Thu, Feb 11, 2016 at 12:58 PM, James Smith <jsm...@ska.ac.za> wrote:
>>>>
>>>>> Haven't encountered that specific issue before but I see a capital
>>>>> letter in your path. That may be an issue.
>>>>> On 11 Feb 2016 12:44, "Mugundhan vijayaraghavan" <
>>>>> v.vaishnav151...@gmail.com> wrote:
>>>>>
>>>>>> Hello guys,
>>>>>>
>>>>>> I'm running matlab/xilinx and mssge tools on a ubuntu 14.04 system.
>>>>>> When I do casper_xps and start compiling, I get this strange error.
>>>>>>
>>>>>> standard exception: XNetlistEngine:
>>>>>> Exception message could not be parsed:
>>>>>> com.xilinx.sysgen.netlist.NetlistInternal: couldn't open first pass
>>>>>> text file at
>>>>>> /home/mugundhan/casper_designs/tut1/sysgen/sysgen/masterScript3888976111602024584.pl
>>>>>> line 559'
>>>>>>
>>>>>>
>>>>>> Reported by:
>>>>>> Unspecified
>>>>>>
>>>>>> Has anyone got this before ?
>>>>>>
>>>>>> Is there any workaround ?
>>>>>>
>>>>>>
>>>>>> --
>>>>>> the giver of moksha
>>>>>>
>>>>>
>>>>
>>>
>>>
>>> --
>>> the giver of moksha
>>>
>>
>>
>>
>

Re: [casper] Trouble Importing casperfpga Library

[James Smith]

Hello Alec,

I've just cloned the repo fresh and it installed just fine. Looking at the
line in question, it might be using a feature of a slightly newer version
of python. I have python 2.7.6 installed - that would be my first
suggestion. Would it be difficult to update your python version in your
distro?

Regards,
James

On Thu, Jul 21, 2016 at 9:49 PM, Alec Josaitis  wrote:

> Dear Casperites,
>
> I recently started the *Introduction to Simulink Roach2 - Casper *tutorial
> and am having difficulty importing the required “casperfpga" repository
> from GitHub. After cloning the repo (git clone git
> ://github.com/ska-sa/casperfpga ),
> and while running the standard  “sudo python setup.py install” command, I
> reach the “byte-compiling” printout statement of file register.pyc and then
> receive a syntax error:
>
> byte-compiling /usr/lib/python2.6/site-packages/casperfpga/register.py to
> register.pyc
> SyntaxError: ('invalid syntax',
> ('/usr/lib/python2.6/site-packages/casperfpga/register.py', 106, 38,
> 'new_values = {_field: None for _field in self.field_names()}\n’))
>
>
> The rest of the install then continues. If I then open python
> and type “import casperfpga”, this syntax error once again appears. Here is
> the full print-out (which also includes the version of python and Red Hat
> Linux that I’m using):
>
> Python 2.6.6 (r266:84292, May 22 2015, 08:34:51)
> [GCC 4.4.7 20120313 (Red Hat 4.4.7-15)] on linux2
> >>> import casperfpga
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "/usr/lib/python2.6/site-packages/casperfpga/__init__.py", line 7,
> in 
> from dcp_fpga import DcpFpga
>   File "/usr/lib/python2.6/site-packages/casperfpga/dcp_fpga.py", line 3,
> in 
> from casperfpga import CasperFpga
>   File "/usr/lib/python2.6/site-packages/casperfpga/casperfpga.py", line
> 10, in 
> import register
>   File "/usr/lib/python2.6/site-packages/casperfpga/register.py", line 106
> new_values = {_field: None for _field in self.field_names()}
>  ^
> SyntaxError: invalid syntax
>
>
> Now, I doubt there actually is a syntax error because the GitHub repo
> doesn’t have any posted issues, so I then assume this is an issue with my
> own environment.  Do any of you either have suggestions on how I should
> change my environment to properly recognize the casperfpga register.py
> file, or have specific recommendations on how to edit the register.py file?
>
> Best Regards,
> Alec
>

Re: [casper] Help with Xilinx and Simulink

[James Smith]

Hello Heystek,

It would be a bit easier to debug if you posted the terminal session, along
with the commands you ran.

Also, please run "ls -l" in the directory and post that as well. It might
just be that you need to give the file executable permissions.

Regards,
James


On Mon, Aug 15, 2016 at 11:24 AM, Heystek Grobler 
wrote:

> Hi Adam
>
> I modified the startsg file. When I run it I get the error in the terminal
> "Permission denied". When I run the startsg file as sudo I get the error
> "command not found".
>
> I have attached my modified startsg file.
>
> Do you perhaps have any ideas of how to solve it?
>
> Sorry for the inconvenience
>
> Heystek
>
> On Mon, Aug 15, 2016 at 11:10 AM, Adam Isaacson 
> wrote:
>
>> Hi Heystek,
>>
>> Nope, just run the ./startsg and matlab will run the startup.m file for
>> you when it opens. You should already have both the startsg and startup.m
>> files, but I gave you mine as I know it works.
>>
>> Kind Regards,
>>
>> Adam
>>
>> On Mon, Aug 15, 2016 at 10:58 AM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Hi Adam
>>>
>>> I will try these files! Do I run the startup.m file in matlab as well?
>>>
>>> Have a nice day
>>>
>>> Heystek
>>>
>>> On Mon, Aug 15, 2016 at 9:04 AM, Adam Isaacson 
>>> wrote:
>>>
 Hi Heystek,

 No worries. I was in your position just a few months ago :). I have
 attached my matlab startup scripts (startsg and startup.m). These must be
 placed in the "mlib_devel" directory. You will probably have to change the
 paths to where your installs are.

 All you need to do is the following:

 1) Startup matlab R2012b, by running the startsg script. Using the
 Ubuntu terminal, in the "mlib_devel" directory type: "./startsg". This
 should startup matlab. There should be a message saying that "system
 generator currently found installed in matlab default path..."
 2) Type in "simulink" in the command window.
 3) The Simulink Library Browser will open. Browse to where your model
 is located and select the *.slx file.
 4) The model should open. Press "Ctrl + D" to check for any errors.
 There should be no errors.
 5) Type in "casper_xps" in the command window. The casper XPS window
 should pop up. Make sure all boxes are ticked under "ISE Design Flow
 Choice:" and then click on "Run XPS". This will run the system generator as
 part of the process, the Xilinx ISE and generate the relevant bit, fpg
 files.

 I have also attached scripts if you just want to run the programs
 individually - you will need to edit the path to where your installs are.

 Good luck. This should get you going. If the scripts bomb out then it
 is likely that your paths are not correct - check that first.

 Kind Regards,

 Adam

 On Sun, Aug 14, 2016 at 8:26 PM, Heystek Grobler <
 heystekgrob...@gmail.com> wrote:

> Hi Adam
>
> I got ISE to run. It open up die GUI. How do I start the sysgen with
> MATLAB?
>
> Sorry about the queations.
>
> Thank you for your help
>
> Heystek
>
> On Sun, Aug 14, 2016 at 12:06 PM, Heystek Grobler <
> heystekgrob...@gmail.com> wrote:
>
>> Good day Adam
>>
>> I have been working through the documents you send me. I cant open
>> the ISE IDE. As soon as I run the script I get the following error:
>>
>> command not found
>>
>> I am new to Linux and Xilinx.
>>
>> Have a good day
>>
>> Heystek
>>
>> On Mon, Aug 8, 2016 at 3:31 PM, Adam Isaacson 
>> wrote:
>>
>>> Hi Heystek,
>>>
>>> You mentioned that you were using the ROACH2 board. This contains a
>>> Virtex 6 device. Vivado only works with Virtex 7 onwards. I would 
>>> suggest
>>> if you are going to target the ROACH 2 that you use Xilinx ISE 14.7.
>>>
>>> You will need to work with ISE 14.7 and not Vivado.  We have just
>>> begun to use Vivado for our Virtex 7 board e.g  SKARAB. As far as I am
>>> aware, all the the ROACH2 development in SKA-SA has been done using 
>>> Xilinx
>>> ISE 14., as it supports Virtex 6 devices.
>>>
>>> Kind Regards,
>>>
>>> Adam
>>>
>>>
>>>
>>>
>>>
>>> On Mon, Aug 8, 2016 at 3:13 PM, Heystek Grobler <
>>> heystekgrob...@gmail.com> wrote:
>>>
 Good day Adam

 I am using Ubuntu 14.04 LTS with MATLAB 2012B. Im using the Vivado
 suite that came with a Zed-Board (Vivado 2013.4).

 The error I am receiving from MATLAB at startup is:
 Undefined function 'lAddSysgen' for input arguments of type 'char'.
 > In matlabrc at 205

 The errors I get from the system generator is:
 1. Design Error - Default block diagram
 2. Block Error - 

Re: [casper] Help with Xilinx and Simulink

[James Smith]

Hello Heystek,

It's conventional to cd into the directory first, then to run "./startsg"

Please use the "-l" (minus + lowercase L) when you run the ls command -
this allows the user to see a bunch more information. See here for a bit of
an explanation:
http://www.thegeekstuff.com/2009/07/linux-ls-command-examples

One thing I would suggest doing is to clone the mlib-devel directory (git
clone http://../mlib-devel.git) into your home directory and
run it from there, not right into /opt. It's (in general) a bad idea to run
software with super-user privileges if you don't need it.

Regards,
James




On Mon, Aug 15, 2016 at 12:17 PM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hi
>
> *Here is a the terminal session :*
>
> heystek@ubuntu:~$ '/opt/mlib_devel-master/startsg'
> bash: /opt/mlib_devel-master/startsg: Permission denied
> heystek@ubuntu:~$ sudo '/opt/mlib_devel-master/startsg'
> [sudo] password for heystek:
> sudo: /opt/mlib_devel-master/startsg: command not found
> heystek@ubuntu:~$ sudo '/opt/mlib_devel-master/startsg'
> sudo: /opt/mlib_devel-master/startsg: command not found
> heystek@ubuntu:~$ clear
>
> heystek@ubuntu:~$ '/opt/mlib_devel-master/startsg'
> bash: /opt/mlib_devel-master/startsg: Permission denied
> heystek@ubuntu:~$ sudo '/opt/mlib_devel-master/startsg'
> [sudo] password for heystek:
> sudo: /opt/mlib_devel-master/startsg: command not found
> heystek@ubuntu:~$ sudo './opt/mlib_devel-master/startsg'
> sudo: ./opt/mlib_devel-master/startsg: command not found
> heystek@ubuntu:~$ sudo '/opt/mlib_devel-master./startsg'
> sudo: /opt/mlib_devel-master./startsg: command not found
> heystek@ubuntu:~$ gnome-screenshot
> heystek@ubuntu:~$
>
> *when is use the ls command I get the following: *
>
> heystek@ubuntu:~$ cd /opt/mlib_devel-master
> heystek@ubuntu:/opt/mlib_devel-master$ ls
> casper_library  startsg  startsg~  startup.m  xps_base  xps_library
> heystek@ubuntu:/opt/mlib_devel-master$
>
> if this is unclear I attached screenshots of the terminal session.
>
>
> Thank you for your help
>
> Heystek
>
>
>
>
>
>
>
>
>
>
>
> On Mon, Aug 15, 2016 at 11:27 AM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Heystek,
>>
>> It would be a bit easier to debug if you posted the terminal session,
>> along with the commands you ran.
>>
>> Also, please run "ls -l" in the directory and post that as well. It might
>> just be that you need to give the file executable permissions.
>>
>> Regards,
>> James
>>
>>
>> On Mon, Aug 15, 2016 at 11:24 AM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Hi Adam
>>>
>>> I modified the startsg file. When I run it I get the error in the
>>> terminal "Permission denied". When I run the startsg file as sudo I get the
>>> error "command not found".
>>>
>>> I have attached my modified startsg file.
>>>
>>> Do you perhaps have any ideas of how to solve it?
>>>
>>> Sorry for the inconvenience
>>>
>>> Heystek
>>>
>>> On Mon, Aug 15, 2016 at 11:10 AM, Adam Isaacson <aisaac...@ska.ac.za>
>>> wrote:
>>>
>>>> Hi Heystek,
>>>>
>>>> Nope, just run the ./startsg and matlab will run the startup.m file for
>>>> you when it opens. You should already have both the startsg and startup.m
>>>> files, but I gave you mine as I know it works.
>>>>
>>>> Kind Regards,
>>>>
>>>> Adam
>>>>
>>>> On Mon, Aug 15, 2016 at 10:58 AM, Heystek Grobler <
>>>> heystekgrob...@gmail.com> wrote:
>>>>
>>>>> Hi Adam
>>>>>
>>>>> I will try these files! Do I run the startup.m file in matlab as well?
>>>>>
>>>>> Have a nice day
>>>>>
>>>>> Heystek
>>>>>
>>>>> On Mon, Aug 15, 2016 at 9:04 AM, Adam Isaacson <aisaac...@ska.ac.za>
>>>>> wrote:
>>>>>
>>>>>> Hi Heystek,
>>>>>>
>>>>>> No worries. I was in your position just a few months ago :). I have
>>>>>> attached my matlab startup scripts (startsg and startup.m). These must be
>>>>>> placed in the "mlib_devel" directory. You will probably have to change 
>>>>>> the
>>>>>> paths to where your installs are.
>>>>>>
>>>>>> All you need to do is the following:
>>>>>>
&g

Re: [casper] issue of endless compiling

[James Smith]

Hello Shotaro,

What are the specifications of the computer that you're using?

Regards,
James


On Fri, Jul 15, 2016 at 8:07 AM, 江藤 翔太郎 (鹿児島大学)  wrote:

> Dear Casperites,
>
> I am Shotaro, a graduate student at Kagoshima university, working on a new
> spectrometer for Nobeyama 45m telescope using ROACH2 Rev2 boards and ASIAA
> 5GSPS ADCs.
>
> We are using ISE 14.7, MATLAB 8.0.0.783(2012b) and Simulink 8.0 on ubuntu
> 12.04, but we have just encountered a trouble of endless compiling.
> It would not finish at all more than a week. We tried purging the memory
> and rebooting the PC before compiling, but the problem was not solved.
> I have checked where the issue occurs by ticking the compiling options of
> CASPER_XPS one by one and I have found that it occurs at 'Xilinx System
> Generator'.
> This issue occurs only for some models while compiling can finish
> successfully within a few hours for models in the tutorial.
> Since system.ngc or system.par file is not generated in this case, we have
> no idea what is wrong with a model.
>
> I would appreciate it if anybody advise me how to solve this problem.
> Thank you.
>
> Best regards,
> Shotaro
>

Re: [casper] Help with Xilinx and Simulink

[James Smith]

Hello Heystek,

It shouldn't matter between .mdl and .slx. Your error there is a bit more
interesting, I'm not sure how to go about solving it or indeed what
information would be needed.

A bit more context information will probably help the other gurus on this
list to assist you though.

Regards,
James


On Tue, Aug 16, 2016 at 9:02 PM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hi James
>
> I tried the command and it accepted it. The matlab terminal gives the
> following error:
>
> Error using gen_xps_files(362)
>
> Does it make a diffirence if the simulink models are .mdl or .slx?
>
> Thank for your help
>
> Heystek
>
> On Tue, Aug 16, 2016 at 5:40 PM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Heystek,
>>
>> Just to get you an answer quickly, try the following command:
>>
>> chmod 777 -R /home/heystek/Desktop/tut1
>>
>> If that command makes an error message then add sudo.
>> It's funny that you should have permissions issues there, if this doesn't
>> fix things then there might be stranger issues at play.
>>
>> Regards,
>> James
>>
>>
>> On Tue, Aug 16, 2016 at 5:36 PM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Hi James and Adam
>>>
>>> I got it working. The chmod +x startsg command did the trick. I started
>>> with the first casper tutorial, but when the system generator compiles it
>>> the tutorial breaks. It gives two errors.
>>>
>>> 1. Design Error  DefaultBlockDiagram  System Generator   Caught standard
>>> exception
>>> 2. Block ErrorAddSub   System Generator
>>>
>>> The following error log was also generated:
>>>
>>> - Version Log
>>> --
>>> Version Path
>>> System Generator/opt/Xilinx/14.7/ISE_DS/ISE/s
>>> ysgen
>>> Matlab 8.0.0.783 (R2012b)   /usr/local/MATLAB/R2012b
>>> ISE /opt/Xilinx/14.7/ISE_DS/ISE
>>> 
>>> 
>>> Summary of Errors:
>>> Error 0001: caught standard exception
>>>  Block: Unspecified
>>> 
>>> 
>>>
>>> Error 0001:
>>>
>>> Reported by:
>>>   Unspecified
>>>
>>> Details:
>>> standard exception: XNetlistEngine:
>>> Exception message could not be parsed:
>>> com.xilinx.sysgen.netlist.NetlistInternal: couldn't open first
>>> pass text file at
>>> /home/heystek/Desktop/tut1/sysgen/sysgen/masterScript423796839757439882
>>> 5.pl
>>> line 559'
>>>
>>> 
>>> 
>>>
>>> Do you perhaps have an idea how I can fix it?
>>>
>>> Thanks for all the help.
>>>
>>> Have a wonderful day.
>>>
>>> Heystek
>>>
>>>
>>> On Tue, Aug 16, 2016 at 8:07 AM, James Smith <jsm...@ska.ac.za> wrote:
>>>
>>>> Hello Heystek,
>>>>
>>>> This should be a relatively trivial problem to solve:
>>>>
>>>> cd ~ # This is a shortcut for your home directory
>>>> git clone >>> SKA-SA one>
>>>> cd mlib-devel
>>>> ./startsg
>>>>
>>>> If that doesn't work, then do this:
>>>> chmod +x startsg
>>>>
>>>> Then you should be fine.
>>>>
>>>> Regards,
>>>> James
>>>>
>>>>
>>>> On Mon, Aug 15, 2016 at 7:46 PM, Heystek Grobler <
>>>> heystekgrob...@gmail.com> wrote:
>>>>
>>>>> Hi Adam and James
>>>>>
>>>>> I am working on my personal computer. I will ask a IT guy to help me
>>>>> with the privileges and also clone the mlib-devel into the home
>>>>> directory and try to run it again.
>>>>>
>>>>> Thanks for all your help.
>>>>>
>>>>> Heystek
>>>>>
>>>>> On Mon, Aug 15, 2016 at 12:58 PM, Adam Isaacson <aisaac...@ska.ac.za>
>>>>> wrote:
>>>>>
>>>>>> Hi Heystek,
>>>>>>
>>>>>> This issue is not with your script, 

Re: [casper] Help with Xilinx and Simulink

[James Smith]

Hello Heystek,

Just to get you an answer quickly, try the following command:

chmod 777 -R /home/heystek/Desktop/tut1

If that command makes an error message then add sudo.
It's funny that you should have permissions issues there, if this doesn't
fix things then there might be stranger issues at play.

Regards,
James


On Tue, Aug 16, 2016 at 5:36 PM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hi James and Adam
>
> I got it working. The chmod +x startsg command did the trick. I started
> with the first casper tutorial, but when the system generator compiles it
> the tutorial breaks. It gives two errors.
>
> 1. Design Error  DefaultBlockDiagram  System Generator   Caught standard
> exception
> 2. Block ErrorAddSub   System Generator
>
> The following error log was also generated:
>
> - Version Log
> --
> Version Path
> System Generator/opt/Xilinx/14.7/ISE_DS/ISE/sysgen
> Matlab 8.0.0.783 (R2012b)   /usr/local/MATLAB/R2012b
> ISE /opt/Xilinx/14.7/ISE_DS/ISE
> 
> 
> Summary of Errors:
> Error 0001: caught standard exception
>  Block: Unspecified
> 
> 
>
> Error 0001:
>
> Reported by:
>   Unspecified
>
> Details:
> standard exception: XNetlistEngine:
> Exception message could not be parsed:
> com.xilinx.sysgen.netlist.NetlistInternal: couldn't open first
> pass text file at
> /home/heystek/Desktop/tut1/sysgen/sysgen/masterScript423796839757439882
> 5.pl
> line 559'
>
> 
> 
>
> Do you perhaps have an idea how I can fix it?
>
> Thanks for all the help.
>
> Have a wonderful day.
>
> Heystek
>
>
> On Tue, Aug 16, 2016 at 8:07 AM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Heystek,
>>
>> This should be a relatively trivial problem to solve:
>>
>> cd ~ # This is a shortcut for your home directory
>> git clone > SKA-SA one>
>> cd mlib-devel
>> ./startsg
>>
>> If that doesn't work, then do this:
>> chmod +x startsg
>>
>> Then you should be fine.
>>
>> Regards,
>> James
>>
>>
>> On Mon, Aug 15, 2016 at 7:46 PM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Hi Adam and James
>>>
>>> I am working on my personal computer. I will ask a IT guy to help me
>>> with the privileges and also clone the mlib-devel into the home
>>> directory and try to run it again.
>>>
>>> Thanks for all your help.
>>>
>>> Heystek
>>>
>>> On Mon, Aug 15, 2016 at 12:58 PM, Adam Isaacson <aisaac...@ska.ac.za>
>>> wrote:
>>>
>>>> Hi Heystek,
>>>>
>>>> This issue is not with your script, but your linux permissions. I
>>>> suggest you follow what James suggests. The fact that you can't run sudo
>>>> though means that you may need your IT guy to give you sudo rights, but if
>>>> you are working off the university server that may be an issue - as James
>>>> says, you shouldn't need this if you install into your home directory.
>>>>
>>>> Kind Regards,
>>>>
>>>> Adam
>>>>
>>>> On Mon, Aug 15, 2016 at 11:27 AM, James Smith <jsm...@ska.ac.za> wrote:
>>>>
>>>>> Hello Heystek,
>>>>>
>>>>> It would be a bit easier to debug if you posted the terminal session,
>>>>> along with the commands you ran.
>>>>>
>>>>> Also, please run "ls -l" in the directory and post that as well. It
>>>>> might just be that you need to give the file executable permissions.
>>>>>
>>>>> Regards,
>>>>> James
>>>>>
>>>>>
>>>>> On Mon, Aug 15, 2016 at 11:24 AM, Heystek Grobler <
>>>>> heystekgrob...@gmail.com> wrote:
>>>>>
>>>>>> Hi Adam
>>>>>>
>>>>>> I modified the startsg file. When I run it I get the error in the
>>>>>> terminal "Permission denied". When I run the startsg file as sudo I get 
>>>>>> the
>>>>>> error "command not found".
>>>>>>
>>

Re: [casper] Programming a ROACH2

[James Smith]

Hello Heystek,

Before you program the ROACH2, I'd suggest trying fpga.is_connected() and
fpga.est_clk_frequency() to check whether you can actually communicate with
the ROACH2. It might be a network cable that's been unplugged by accident -
that's where I've seen those errors before. The
fpga=casperfpga.katcp_fpga.KatcpFpga('roachname
or ip_address') doesn't actually throw an error if it can't connect to the
ROACH2. This information would at least help you narrow down the
possibilities as to what's wrong (i.e. whether it's the kernel on the
ROACH2).

Disclaimer: I work only on ROACH, but I'm fairly certain the procedure
would be the same.

Regards,
James


On Fri, Sep 30, 2016 at 1:36 PM, Heystek Grobler 
wrote:

> Good day everyone
>
> I am having difficulties programming the ROACH 2 board. I am following the
> instructions of CASPER tutorial one.
>
> I Have compiled the fpg file and is using the following steps from the
> tutorial.
>
> 1. I entered ipython into the terminal
> 2. import casperfpga
> 3. fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address') with
> the ip address of my roach
> 4. fpga.upload_to_ram_and_program('your_fpgfile.fpg') with the location
> of the .fpga file
>
> but at point 4 I get the following error:
>
> RuntimeError  Traceback (most recent call
> last)
>  in ()
> > 1 fpga.upload_to_ram_and_program('/home/heystek/simulink/ai_
> t1/bit_files/ai_t1_2016_Sep_14_2052.fpg')
>
> /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
> upload_to_ram_and_program(self, filename, port, timeout, wait_complete)
> 442 if request_result != '':
> 443 raise RuntimeError('progremote request(%s) on host %s
> failed' %
> --> 444(request_result, self.host))
> 445
> 446 # start the upload thread and join
>
> RuntimeError: progremote request(Request to client 192.168.33.4 failed.)
> on host 192.168.33.4 failed
>
> Am I doing something wrong?
>
> I looked at the mail archives and it sugested that I update the kernel of
> the roach. Is this perhaps the problem? Or am I doing something wrong?
>
> Have a wonderful day.
>
> Heystek
>

Re: [casper] Programming a ROACH2

[James Smith]

Hello Heystek,

If you're still in the Python environment, then PySpead is the one you want.

Regards,
James


On Fri, Oct 7, 2016 at 10:59 AM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Good Day
>
> After a while of troubleshooting I determined the connection with TCP/IP
> into the board was correct. I updated the file system and kernel of the
> ROACH2 and now I can program it.
>
> I only need to install a package called spead in order to use the .bof
> file with tutorial 3 of CASPER.
>
> Where can a download the spead package from? I can only find PySpead and
> Spead2.
>
> Thanks for everyones help
>
> Heystek!
>
> On Fri, Sep 30, 2016 at 5:28 PM, Adam Isaacson <aisaac...@ska.ac.za>
> wrote:
>
>> Hi Heystek,
>>
>> If you want to telnet, which is another way of configuring your board,
>> then you need to state the port. Are you doing the following from the
>> terminal:
>>
>> 1)Telnet to port 7147: "telnet  7147".
>>
>> 2)?progremote fpgfile.fpg
>>
>> You say you can ping your board, so you should be able to connect via
>> casperfpga, as you mentioned above. Did you do what James suggested i.e.
>> try running fpga.is_connected()? if it reports "True" then you are
>> connected and if false then you will need to debug further. Are you sure
>> that the IP you are pinging is your roach2 - may sound like a silly
>> question, but I don't know your setup.
>>
>> Kind Regards,
>>
>> Adam
>>
>>
>> On Fri, Sep 30, 2016 at 3:38 PM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Hi James
>>>
>>> I will try it. Through the terminal I can ping the board, but I cant
>>> open a Telnet connection.
>>>
>>> When I open a ttyUSB connection to the Roach en monitor it, and try to
>>> upload the fga file, the Roach gives the same error "progremote"
>>>
>>> Thats why I'm confused
>>>
>>> Thanks for your help!
>>>
>>> I really appreciate it
>>>
>>> Heystek
>>>
>>>
>>> On Friday, 30 September 2016, James Smith <jsm...@ska.ac.za> wrote:
>>>
>>>> Hello Heystek,
>>>>
>>>> Before you program the ROACH2, I'd suggest trying fpga.is_connected()
>>>> and fpga.est_clk_frequency() to check whether you can actually
>>>> communicate with the ROACH2. It might be a network cable that's been
>>>> unplugged by accident - that's where I've seen those errors before. The
>>>> fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address')
>>>> doesn't actually throw an error if it can't connect to the ROACH2. This
>>>> information would at least help you narrow down the possibilities as to
>>>> what's wrong (i.e. whether it's the kernel on the ROACH2).
>>>>
>>>> Disclaimer: I work only on ROACH, but I'm fairly certain the procedure
>>>> would be the same.
>>>>
>>>> Regards,
>>>> James
>>>>
>>>>
>>>> On Fri, Sep 30, 2016 at 1:36 PM, Heystek Grobler <
>>>> heystekgrob...@gmail.com> wrote:
>>>>
>>>>> Good day everyone
>>>>>
>>>>> I am having difficulties programming the ROACH 2 board. I am following
>>>>> the instructions of CASPER tutorial one.
>>>>>
>>>>> I Have compiled the fpg file and is using the following steps from the
>>>>> tutorial.
>>>>>
>>>>> 1. I entered ipython into the terminal
>>>>> 2. import casperfpga
>>>>> 3. fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address')
>>>>> with the ip address of my roach
>>>>> 4. fpga.upload_to_ram_and_program('your_fpgfile.fpg') with the
>>>>> location of the .fpga file
>>>>>
>>>>> but at point 4 I get the following error:
>>>>>
>>>>> RuntimeError  Traceback (most recent call
>>>>> last)
>>>>>  in ()
>>>>> > 1 fpga.upload_to_ram_and_program('/home/heystek/simulink/ai_t1
>>>>> /bit_files/ai_t1_2016_Sep_14_2052.fpg')
>>>>>
>>>>> /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
>>>>> upload_to_ram_and_program(self, filename, port, timeout,
>>>>> wait_complete)
>>>>> 442 if request_result != '':
>>>>> 443 raise RuntimeError('progremote request(%s) on host
>>>>> %s failed' %
>>>>> --> 444(request_result, self.host))
>>>>> 445
>>>>> 446 # start the upload thread and join
>>>>>
>>>>> RuntimeError: progremote request(Request to client 192.168.33.4
>>>>> failed.) on host 192.168.33.4 failed
>>>>>
>>>>> Am I doing something wrong?
>>>>>
>>>>> I looked at the mail archives and it sugested that I update the kernel
>>>>> of the roach. Is this perhaps the problem? Or am I doing something wrong?
>>>>>
>>>>> Have a wonderful day.
>>>>>
>>>>> Heystek
>>>>>
>>>>
>>>>
>>
>>
>> --
>>
>> Adam Isaacson
>>
>> DBE: FPGA Engineer
>>
>> SKA-SA
>>
>> 3rd Floor
>>
>> The Park
>>
>> Park Road
>>
>> Pinelands
>>
>> 7405
>>
>>
>> Tel: +27215067300 (W)
>>
>> Fax: +27215067375 (W)
>>
>> Cell: +27825639602
>>
>
>

Re: [casper] Programming a ROACH2

[James Smith]

Hello Heystek,

I vaguely recall installing spead from pip as well, as Ryan has done here.
Give that a whirl.

Regards,
James


On Fri, Oct 7, 2016 at 11:06 AM, Ryan Monroe <ryan.m.mon...@gmail.com>
wrote:

> rmonroe@rmonroe-ThinkPad-P50:~$ sudo pip install spead
> [sudo] password for rmonroe:
> The directory '/home/rmonroe/.cache/pip/http' or its parent directory is
> not owned by the current user and the cache has been disabled. Please check
> the permissions and owner of that directory. If executing pip with sudo,
> you may want sudo's -H flag.
> The directory '/home/rmonroe/.cache/pip' or its parent directory is not
> owned by the current user and caching wheels has been disabled. check the
> permissions and owner of that directory. If executing pip with sudo, you
> may want sudo's -H flag.
> Collecting spead
>   Downloading spead-0.5.1.tar.gz (61kB)
> 100% || 71kB 1.5MB/s
> Installing collected packages: spead
>   Running setup.py install for spead ... done
> Successfully installed spead-0.5.1
> rmonroe@rmonroe-ThinkPad-P50:~$ ipython
> Python 2.7.12 (default, Jul  1 2016, 15:12:24)
> Type "copyright", "credits" or "license" for more information.
>
> IPython 2.4.1 -- An enhanced Interactive Python.
> ? -> Introduction and overview of IPython's features.
> %quickref -> Quick reference.
> help  -> Python's own help system.
> object?   -> Details about 'object', use 'object??' for extra details.
>
> In [1]: import spead
>
> In [2]:
>
>
> On 10/07/2016 02:04 AM, Heystek Grobler wrote:
>
> Hi James
>
> I installed the PySpead package but I get the following error when I run
> the tut3.py script:
>
> ImportError: No mode named spead
>
> Do you perhaps have any ideas on how to solve it?
>
> Thank you!!
>
> Heystek
>
> On Fri, Oct 7, 2016 at 11:01 AM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Heystek,
>>
>> If you're still in the Python environment, then PySpead is the one you
>> want.
>>
>> Regards,
>> James
>>
>>
>> On Fri, Oct 7, 2016 at 10:59 AM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Good Day
>>>
>>> After a while of troubleshooting I determined the connection with TCP/IP
>>> into the board was correct. I updated the file system and kernel of the
>>> ROACH2 and now I can program it.
>>>
>>> I only need to install a package called spead in order to use the .bof
>>> file with tutorial 3 of CASPER.
>>>
>>> Where can a download the spead package from? I can only find PySpead and
>>> Spead2.
>>>
>>> Thanks for everyones help
>>>
>>> Heystek!
>>>
>>> On Fri, Sep 30, 2016 at 5:28 PM, Adam Isaacson <aisaac...@ska.ac.za>
>>> wrote:
>>>
>>>> Hi Heystek,
>>>>
>>>> If you want to telnet, which is another way of configuring your board,
>>>> then you need to state the port. Are you doing the following from the
>>>> terminal:
>>>>
>>>> 1)Telnet to port 7147: "telnet  7147".
>>>>
>>>> 2)?progremote fpgfile.fpg
>>>>
>>>> You say you can ping your board, so you should be able to connect via
>>>> casperfpga, as you mentioned above. Did you do what James suggested i.e.
>>>> try running fpga.is_connected()? if it reports "True" then you are
>>>> connected and if false then you will need to debug further. Are you sure
>>>> that the IP you are pinging is your roach2 - may sound like a silly
>>>> question, but I don't know your setup.
>>>>
>>>> Kind Regards,
>>>>
>>>> Adam
>>>>
>>>>
>>>> On Fri, Sep 30, 2016 at 3:38 PM, Heystek Grobler <
>>>> heystekgrob...@gmail.com> wrote:
>>>>
>>>>> Hi James
>>>>>
>>>>> I will try it. Through the terminal I can ping the board, but I cant
>>>>> open a Telnet connection.
>>>>>
>>>>> When I open a ttyUSB connection to the Roach en monitor it, and try to
>>>>> upload the fga file, the Roach gives the same error "progremote"
>>>>>
>>>>> Thats why I'm confused
>>>>>
>>>>> Thanks for your help!
>>>>>
>>>>> I really appreciate it
>>>>>
>>>>> Heystek
>>>>>
>>>>>
>>>>> On Friday

Re: [casper] Programming a ROACH2

[James Smith]

Hello Heystek,

Pip is seeing that you've already got a version of Spead installed, which
might not have worked. You can delete the directory to 'uninstall' it
(Request for comment: is this a safe approach? It's what I've always done
with no problems.)

Before you try that though, perhaps just try importing spead in ipython as
Ryan did. What are the error messages?

Regards,
James


On Fri, Oct 7, 2016 at 11:23 AM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hi James and Ryan
>
> I tried sudo pip install spead and I get the following
>
> Requirment already satisfied (use --upgrade): spead in
> usr/local/lib/python2.7/dist-packages
> cleaning up
>
> Any ideas?
>
> I am a bit lost to be honest.
>
> On Fri, Oct 7, 2016 at 11:09 AM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Heystek,
>>
>> I vaguely recall installing spead from pip as well, as Ryan has done
>> here. Give that a whirl.
>>
>> Regards,
>> James
>>
>>
>> On Fri, Oct 7, 2016 at 11:06 AM, Ryan Monroe <ryan.m.mon...@gmail.com>
>> wrote:
>>
>>> rmonroe@rmonroe-ThinkPad-P50:~$ sudo pip install spead
>>> [sudo] password for rmonroe:
>>> The directory '/home/rmonroe/.cache/pip/http' or its parent directory
>>> is not owned by the current user and the cache has been disabled. Please
>>> check the permissions and owner of that directory. If executing pip with
>>> sudo, you may want sudo's -H flag.
>>> The directory '/home/rmonroe/.cache/pip' or its parent directory is not
>>> owned by the current user and caching wheels has been disabled. check the
>>> permissions and owner of that directory. If executing pip with sudo, you
>>> may want sudo's -H flag.
>>> Collecting spead
>>>   Downloading spead-0.5.1.tar.gz (61kB)
>>> 100% || 71kB 1.5MB/s
>>> Installing collected packages: spead
>>>   Running setup.py install for spead ... done
>>> Successfully installed spead-0.5.1
>>> rmonroe@rmonroe-ThinkPad-P50:~$ ipython
>>> Python 2.7.12 (default, Jul  1 2016, 15:12:24)
>>> Type "copyright", "credits" or "license" for more information.
>>>
>>> IPython 2.4.1 -- An enhanced Interactive Python.
>>> ? -> Introduction and overview of IPython's features.
>>> %quickref -> Quick reference.
>>> help  -> Python's own help system.
>>> object?   -> Details about 'object', use 'object??' for extra details.
>>>
>>> In [1]: import spead
>>>
>>> In [2]:
>>>
>>>
>>> On 10/07/2016 02:04 AM, Heystek Grobler wrote:
>>>
>>> Hi James
>>>
>>> I installed the PySpead package but I get the following error when I run
>>> the tut3.py script:
>>>
>>> ImportError: No mode named spead
>>>
>>> Do you perhaps have any ideas on how to solve it?
>>>
>>> Thank you!!
>>>
>>> Heystek
>>>
>>> On Fri, Oct 7, 2016 at 11:01 AM, James Smith <jsm...@ska.ac.za> wrote:
>>>
>>>> Hello Heystek,
>>>>
>>>> If you're still in the Python environment, then PySpead is the one you
>>>> want.
>>>>
>>>> Regards,
>>>> James
>>>>
>>>>
>>>> On Fri, Oct 7, 2016 at 10:59 AM, Heystek Grobler <
>>>> heystekgrob...@gmail.com> wrote:
>>>>
>>>>> Good Day
>>>>>
>>>>> After a while of troubleshooting I determined the connection with
>>>>> TCP/IP into the board was correct. I updated the file system and kernel of
>>>>> the ROACH2 and now I can program it.
>>>>>
>>>>> I only need to install a package called spead in order to use the .bof
>>>>> file with tutorial 3 of CASPER.
>>>>>
>>>>> Where can a download the spead package from? I can only find PySpead
>>>>> and Spead2.
>>>>>
>>>>> Thanks for everyones help
>>>>>
>>>>> Heystek!
>>>>>
>>>>> On Fri, Sep 30, 2016 at 5:28 PM, Adam Isaacson <aisaac...@ska.ac.za>
>>>>> wrote:
>>>>>
>>>>>> Hi Heystek,
>>>>>>
>>>>>> If you want to telnet, which is another way of configuring your
>>>>>> board, then you need to state the port. Are you doing the following from
>>>>>> the terminal:
>>>>>>

Re: [casper] 回复: Programming a ROACH2

[James Smith]

Hello Heystek,

I'm not sure what you mean by 'live' data. Wesley's mail correctly refers
you to tut 3 which will let you plot your spectrum, but that's somewhat
staggered. Having it display on a continuous basis will take a fair amount
more work and will probably require having a 10 GbE connection to a
computer.

For power vs frequency - each channel represents a nominal centre
frequency, so it's just a matter of scaling your X-axis in terms of
fractions of your ADC bandwidth.

Regards,
James


On Mon, Oct 17, 2016 at 9:52 PM, Heystek Grobler 
wrote:

> Hi Everyone
>
> I got it wot king using the following commands:
>
> ipython --pylab
> import casperfpga, corr,time,numpy,struct,sys,logging,pylab,matplotlib
> fpga = casperfpga.katcp_fpga.KatcpFpga('192.168.33.7')
> fpga.upload_to_ram_and_program('heystek_tut3_2016_Sep_22_1726.fpg')
> fpga.write_int('acc_len',2*(2**28)/2048)
> fpga.write_int('gain',0x)
> fpga.write_int('cnt_rst',1)
> fpga.write_int('cnt_rst',0)
> acc_n = fpga.read_uint('acc_cnt')
> a_0=struct.unpack('>1024l',fpga.read('even',1024*4,0))
> a_1=struct.unpack('>1024l',fpga.read('odd',1024*4,0))
>
> interleave_a=[]
>
> for i in range(1024):
> interleave_a.append(a_0[i])
> interleave_a.append(a_1[i])
>
> fpga.write_int('cnt_rst',1)
> fpga.write_int('cnt_rst',0)
>
> pylab.figure(num=1,figsize=(10,10))
> pylab.plot(interleave_a)
> pylab.title('Integration number %i.'%acc_n)
> pylab.ylabel('Power (arbitrary units)')
> pylab.grid()
> pylab.xlabel('Channel')
> pylab.xlim(0,2048)
> pylab.show()
>
> I don't get the exact same output as the image on the casper site, but I
> think it is due to the integration size, but I get output.
>
> This my seem like stupid questions but I have two questions.
>
> The first is. How can I plot frequency vs power and not channel vs power?
>
> The second question is. I want to hook up an FM antenna to the ADC and see
> if I get "live" data. How to I do that? Do I need to create a .bof file
> somehow? and if so, how do I do it.
>
> Thanks for all for help
>
> Heystek
>
> On Tue, Oct 11, 2016 at 5:20 PM, lij...@xao.ac.cn 
> wrote:
>
>> mybe your katcp is too new(0.6?),try to install 0.5.5
>> if you use pip,just run : sudo pip install katcp==0.5.5
>>
>> 发自我的华为手机
>>
>>
>>  原始邮件 
>> 主题：Re: [casper] Programming a ROACH2
>> 发件人：David MacMahon
>> 收件人：Jason Manley
>> 抄送：Casper Lists ,Ryan Monroe
>>
>>
>> I think the intent of exit_fail() is to try to close the connection,
>> ignore any exceptions raised while trying to close the connection, and then
>> re-raise the original exception that happened before exit_fail was called,
>> but I think the implementation is flawed. Here’s the definition of
>> exit_fail() as it appears on GitHub:
>>
>> def exit_fail():
>> print 'FAILURE DETECTED. Log entries:\n',lh.printMessages()
>> try:
>> fpga.stop()
>> except: pass
>> raise
>> exit()
>>
>> I think this try/except block (with "pass" in the except part) followed
>> by "raise" is completely superfluous. I think it means try to do something
>> and if an exception is raised while trying, ignore it but then re-raise it,
>> which seems exactly the same as not having the try/except block there at
>> all! Not to mention that the exit() call will never be reached. I’m also
>> not a fan of functions that can only be called while an exception is being
>> handled (otherwise the no-arg form of "raise" will bomb out I think).
>>
>> It would probably be preferable to pass the original exception to
>> exit_fail() as an argument so that the original exception can be re-raised.
>> I can make that change when I get back to Berkeley next week (unless
>> someone beats me to it).
>>
>> Sorry for veering so far off topic,
>> Dave
>>
>>
>> > On Oct 11, 2016, at 10:16, Jason Manley wrote:
>> >
>> > Some of the earlier scripts had bad error handling. If anything fails
>> before the host object was successfully created, then you get this error
>> because it tries to close the connection before exiting.
>> >
>> > Jason
>> >
>> > On 11 Oct 2016, at 16:09, David MacMahon wrote:
>> >
>> >>
>> >>> On Oct 11, 2016, at 06:46, Heystek Grobler wrote:
>> >>>
>> >>> Connecting to server 192.168.33.7 on port 7147... FAILURE DETECTED
>> >>
>> >> Editorial comments on error handling in tut3.py aside, I think the
>> fact that "FAILURE DETECTED" follows "Connecting to server…" on the same
>> line (i.e. no newline character inbetween) means that something went wrong
>> when constructing the FpgaClient object which connects to TCP port 7147 of
>> the ROACH2 with IP address 192.168.33.7. This is expecting the ROACH2 to
>> have a tcpborphserver process listening on that port.
>> >>
>> >> What happens when you run:
>> >>
>> >> telnet 198.168.33.7 7147
>> >>
>> >> HTH,
>> >> Dave
>> >>
>> >
>>
>>
>>
>

Re: [casper] 回复: Programming a ROACH2

[James Smith]

Hello Heystek,

Yeah, that will get it done. You'll obviously need to interleave the even
and odd data, but it'll do the job.

Regards,
James



On Tue, Oct 18, 2016 at 11:18 AM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hi James
>
> With ''live data'' I mean my own data from an FM antenna. Wesley suggested
> that I use a snap block. So basically al I need to do is add a snap block
> at the end of the simulation from tut3 that says "evan" and "odd" and plot
> the data that has been captured inside them.
>
> Thank you
>
> Heystek
>
> On Tue, Oct 18, 2016 at 10:31 AM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Heystek,
>>
>> I'm not sure what you mean by 'live' data. Wesley's mail correctly refers
>> you to tut 3 which will let you plot your spectrum, but that's somewhat
>> staggered. Having it display on a continuous basis will take a fair amount
>> more work and will probably require having a 10 GbE connection to a
>> computer.
>>
>> For power vs frequency - each channel represents a nominal centre
>> frequency, so it's just a matter of scaling your X-axis in terms of
>> fractions of your ADC bandwidth.
>>
>> Regards,
>> James
>>
>>
>> On Mon, Oct 17, 2016 at 9:52 PM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Hi Everyone
>>>
>>> I got it wot king using the following commands:
>>>
>>> ipython --pylab
>>> import casperfpga, corr,time,numpy,struct,sys,logging,pylab,matplotlib
>>> fpga = casperfpga.katcp_fpga.KatcpFpga('192.168.33.7')
>>> fpga.upload_to_ram_and_program('heystek_tut3_2016_Sep_22_1726.fpg')
>>> fpga.write_int('acc_len',2*(2**28)/2048)
>>> fpga.write_int('gain',0x)
>>> fpga.write_int('cnt_rst',1)
>>> fpga.write_int('cnt_rst',0)
>>> acc_n = fpga.read_uint('acc_cnt')
>>> a_0=struct.unpack('>1024l',fpga.read('even',1024*4,0))
>>> a_1=struct.unpack('>1024l',fpga.read('odd',1024*4,0))
>>>
>>> interleave_a=[]
>>>
>>> for i in range(1024):
>>> interleave_a.append(a_0[i])
>>> interleave_a.append(a_1[i])
>>>
>>> fpga.write_int('cnt_rst',1)
>>> fpga.write_int('cnt_rst',0)
>>>
>>> pylab.figure(num=1,figsize=(10,10))
>>> pylab.plot(interleave_a)
>>> pylab.title('Integration number %i.'%acc_n)
>>> pylab.ylabel('Power (arbitrary units)')
>>> pylab.grid()
>>> pylab.xlabel('Channel')
>>> pylab.xlim(0,2048)
>>> pylab.show()
>>>
>>> I don't get the exact same output as the image on the casper site, but I
>>> think it is due to the integration size, but I get output.
>>>
>>> This my seem like stupid questions but I have two questions.
>>>
>>> The first is. How can I plot frequency vs power and not channel vs power?
>>>
>>> The second question is. I want to hook up an FM antenna to the ADC and
>>> see if I get "live" data. How to I do that? Do I need to create a .bof file
>>> somehow? and if so, how do I do it.
>>>
>>> Thanks for all for help
>>>
>>> Heystek
>>>
>>> On Tue, Oct 11, 2016 at 5:20 PM, lij...@xao.ac.cn <lij...@xao.ac.cn>
>>> wrote:
>>>
>>>> mybe your katcp is too new(0.6?),try to install 0.5.5
>>>> if you use pip,just run : sudo pip install katcp==0.5.5
>>>>
>>>> 发自我的华为手机
>>>>
>>>>
>>>>  原始邮件 
>>>> 主题：Re: [casper] Programming a ROACH2
>>>> 发件人：David MacMahon
>>>> 收件人：Jason Manley
>>>> 抄送：Casper Lists ,Ryan Monroe
>>>>
>>>>
>>>> I think the intent of exit_fail() is to try to close the connection,
>>>> ignore any exceptions raised while trying to close the connection, and then
>>>> re-raise the original exception that happened before exit_fail was called,
>>>> but I think the implementation is flawed. Here’s the definition of
>>>> exit_fail() as it appears on GitHub:
>>>>
>>>> def exit_fail():
>>>> print 'FAILURE DETECTED. Log entries:\n',lh.printMessages()
>>>> try:
>>>> fpga.stop()
>>>> except: pass
>>>> raise
>>>> exit()
>>>>
>>>> I think this try/except block (with "pass" in the except part) followed
>>>> by "raise" is completely superfluous. I think it means try to do something
>>>> and i

Re: [casper] Programming a ROACH2

[James Smith]

Hello Heystek,

How cognisant are you with Python? Try opening an ipython session and
connecting to your ROACH manually, I think you have been able to do that in
the past.

This error message means that your network can't reach the ROACH for some
reason.

Regards,
James


On Tue, Oct 11, 2016 at 12:46 PM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hi Everyone
>
> After trying all of your suggestions and install a few more packages is
> works. I get the following error now when I run the tut3.py script for tut3.
>
> heystek@heystek-HP-G62-Notebook-PC:~/simulink/heystek_tutorial_3/heystek_tut3$
> ./tut3.py 192.168.33.7 tut3.bofConnecting to server 192.168.33.7 on port
> 7147...  FAILURE DETECTED. Log entries:
> None
> Traceback (most recent call last):
>   File "./tut3.py", line 141, in 
> exit_fail()
>   File "./tut3.py", line 21, in exit_fail
> fpga.stop()
> NameError: global name 'fpga' is not defined
>
>
> Any ideas on how to solve this?
>
> Thank you
>
> Heystek
>
> On Fri, Oct 7, 2016 at 9:05 PM, Ryan Monroe <ryan.m.mon...@gmail.com>
> wrote:
>
>> I would suggest using "pip uninstall spead" instead -- I don't recall
>> ever using it myself, but it appears to be the pip-sanctioned way of
>> removing something.
>>
>> On 10/07/2016 02:24 AM, James Smith wrote:
>>
>> Hello Heystek,
>>
>> Pip is seeing that you've already got a version of Spead installed, which
>> might not have worked. You can delete the directory to 'uninstall' it
>> (Request for comment: is this a safe approach? It's what I've always done
>> with no problems.)
>>
>> Before you try that though, perhaps just try importing spead in ipython
>> as Ryan did. What are the error messages?
>>
>> Regards,
>> James
>>
>>
>> On Fri, Oct 7, 2016 at 11:23 AM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Hi James and Ryan
>>>
>>> I tried sudo pip install spead and I get the following
>>>
>>> Requirment already satisfied (use --upgrade): spead in
>>> usr/local/lib/python2.7/dist-packages
>>> cleaning up
>>>
>>> Any ideas?
>>>
>>> I am a bit lost to be honest.
>>>
>>> On Fri, Oct 7, 2016 at 11:09 AM, James Smith <jsm...@ska.ac.za> wrote:
>>>
>>>> Hello Heystek,
>>>>
>>>> I vaguely recall installing spead from pip as well, as Ryan has done
>>>> here. Give that a whirl.
>>>>
>>>> Regards,
>>>> James
>>>>
>>>>
>>>> On Fri, Oct 7, 2016 at 11:06 AM, Ryan Monroe <ryan.m.mon...@gmail.com>
>>>> wrote:
>>>>
>>>>> rmonroe@rmonroe-ThinkPad-P50:~$ sudo pip install spead
>>>>> [sudo] password for rmonroe:
>>>>> The directory '/home/rmonroe/.cache/pip/http' or its parent directory
>>>>> is not owned by the current user and the cache has been disabled. Please
>>>>> check the permissions and owner of that directory. If executing pip with
>>>>> sudo, you may want sudo's -H flag.
>>>>> The directory '/home/rmonroe/.cache/pip' or its parent directory is
>>>>> not owned by the current user and caching wheels has been disabled. check
>>>>> the permissions and owner of that directory. If executing pip with sudo,
>>>>> you may want sudo's -H flag.
>>>>> Collecting spead
>>>>>   Downloading spead-0.5.1.tar.gz (61kB)
>>>>> 100% || 71kB 1.5MB/s
>>>>> Installing collected packages: spead
>>>>>   Running setup.py install for spead ... done
>>>>> Successfully installed spead-0.5.1
>>>>> rmonroe@rmonroe-ThinkPad-P50:~$ ipython
>>>>> Python 2.7.12 (default, Jul  1 2016, 15:12:24)
>>>>> Type "copyright", "credits" or "license" for more information.
>>>>>
>>>>> IPython 2.4.1 -- An enhanced Interactive Python.
>>>>> ? -> Introduction and overview of IPython's features.
>>>>> %quickref -> Quick reference.
>>>>> help  -> Python's own help system.
>>>>> object?   -> Details about 'object', use 'object??' for extra details.
>>>>>
>>>>> In [1]: import spead
>>>>>
>>>>> In [2]:
>>>>>
>>>>>
>>>>> On 10/07/2016 02:04 AM, Heystek Grobler wrote:
>>>>&g

Re: [casper] Programming a ROACH2

[James Smith]

Hello Heystek,

Having looked at the tut3 which is on the website, it is using the older
corr library, not casperfpga. It also looks as though it's intended for
ROACH and not ROACH2, I'm not sure whether that's an issue. I've never used
a ROACH2.

I was under the impression that it should have been updated for the recent
CASPER workshop. Can someone comment on this?

It might be an interesting exercise to try and use the model files to
compile for ROACH2 then to write your own script, using this one as a
guide. You'd learn a lot about how things work in the process. Not a quick
fix to your problem, I'll admit, but it'll be an education.

Regards,
James


On Tue, Oct 11, 2016 at 1:33 PM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hi James
>
> Through ipython I can connect to the Roach and upload the .fga file. I can
> also ping the roach.The problem comes in using the script with the .bof
> file. I am very new to python but have training in C, C#, Java and Assembly.
>
> I run the script as follows:
> python tut3.py 192.168.33.7
>
>
> On Tue, Oct 11, 2016 at 1:06 PM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Heystek,
>>
>> How cognisant are you with Python? Try opening an ipython session and
>> connecting to your ROACH manually, I think you have been able to do that in
>> the past.
>>
>> This error message means that your network can't reach the ROACH for some
>> reason.
>>
>> Regards,
>> James
>>
>>
>> On Tue, Oct 11, 2016 at 12:46 PM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Hi Everyone
>>>
>>> After trying all of your suggestions and install a few more packages is
>>> works. I get the following error now when I run the tut3.py script for tut3.
>>>
>>> heystek@heystek-HP-G62-Notebook-PC:~/simulink/heystek_tutorial_3/heystek_tut3$
>>> ./tut3.py 192.168.33.7 tut3.bofConnecting to server 192.168.33.7 on port
>>> 7147...  FAILURE DETECTED. Log entries:
>>> None
>>> Traceback (most recent call last):
>>>   File "./tut3.py", line 141, in 
>>> exit_fail()
>>>   File "./tut3.py", line 21, in exit_fail
>>> fpga.stop()
>>> NameError: global name 'fpga' is not defined
>>>
>>>
>>> Any ideas on how to solve this?
>>>
>>> Thank you
>>>
>>> Heystek
>>>
>>> On Fri, Oct 7, 2016 at 9:05 PM, Ryan Monroe <ryan.m.mon...@gmail.com>
>>> wrote:
>>>
>>>> I would suggest using "pip uninstall spead" instead -- I don't recall
>>>> ever using it myself, but it appears to be the pip-sanctioned way of
>>>> removing something.
>>>>
>>>> On 10/07/2016 02:24 AM, James Smith wrote:
>>>>
>>>> Hello Heystek,
>>>>
>>>> Pip is seeing that you've already got a version of Spead installed,
>>>> which might not have worked. You can delete the directory to 'uninstall' it
>>>> (Request for comment: is this a safe approach? It's what I've always done
>>>> with no problems.)
>>>>
>>>> Before you try that though, perhaps just try importing spead in ipython
>>>> as Ryan did. What are the error messages?
>>>>
>>>> Regards,
>>>> James
>>>>
>>>>
>>>> On Fri, Oct 7, 2016 at 11:23 AM, Heystek Grobler <
>>>> heystekgrob...@gmail.com> wrote:
>>>>
>>>>> Hi James and Ryan
>>>>>
>>>>> I tried sudo pip install spead and I get the following
>>>>>
>>>>> Requirment already satisfied (use --upgrade): spead in
>>>>> usr/local/lib/python2.7/dist-packages
>>>>> cleaning up
>>>>>
>>>>> Any ideas?
>>>>>
>>>>> I am a bit lost to be honest.
>>>>>
>>>>> On Fri, Oct 7, 2016 at 11:09 AM, James Smith <jsm...@ska.ac.za> wrote:
>>>>>
>>>>>> Hello Heystek,
>>>>>>
>>>>>> I vaguely recall installing spead from pip as well, as Ryan has done
>>>>>> here. Give that a whirl.
>>>>>>
>>>>>> Regards,
>>>>>> James
>>>>>>
>>>>>>
>>>>>> On Fri, Oct 7, 2016 at 11:06 AM, Ryan Monroe <ryan.m.mon...@gmail.com
>>>>>> > wrote:
>>>>>>
>>>>>>> rmonroe@rmonroe-ThinkPad-P50:~$ sudo pip install spead
>>>&g

Re: [casper] Minimum Clock Frequency (ROACH2)

[James Smith]

Hello Franco,

If you're only using 1 sample at a time, you needn't use a CASPER FFT, the
Xilinx ones do the trick nicely. You can use an asynchronous 1-input PFB if
you want to as well.

You would probably need to rework your down-stream stuff though.

Regards,
James


On Tue, Apr 4, 2017 at 2:48 PM, Franco  wrote:

> Hi Jack,
>
> I though of that, but the thing is, if I only take 1 sample per clock
> cycle, I'm not sure how to use a 8 input FFT and still keep the same number
> of output channels. Maybe I could implement serial-to-parallel block, and
> read the FFT every 8 cycles, but I don't know if that's an adequate (or
> easy to implement) solution.
>
>
> I get not very informative errors when I try to compile models below
> 600MHz (I tried, 100MHz, 200MHz, ... , 500MHz):
>
> Creating block object: xps_adc5g
> Problem with block: test/asiaa_adc5g
> : An optimum PLL solution is not available!
> Backtrace 1: xps_adc5g:177
> Backtrace 2: gen_xps_files:229
> Backtrace 3: run_Callback:155
> Backtrace 4: casper_xps:86
> Backtrace 5: @(hObject,eventdata)casper_xps('run_Callback',hObject,eventd
> ata,guidata(hObject)):0
> Error using gen_xps_files (line 242)
> Error found during Object creation.
>
>
> Thanks,
>
> Franco
>
>
>
> On 03/04/17 23:39, Jack Hickish wrote:
>
> Hi Franco,
>
> I don't know the low frequency limit, but for what it's worth, you could
> always run the adc at 320 MHz and just use 1 of the 8 outputs, which also
> has the benefit of avoiding and inter-core mismatch issues, since you'd
> effectively only be using 1 core. Or run faster and only use every Nth
> sample.
>
> What error do you get when you clock below 600 MHz ADC clock?
>
> Cheers
> Jack
>
> On Mon, 3 Apr 2017, 19:22 Franco,  wrote:
>
>> Hi All,
>>
>> I'm working in an application where I need high frequency resolution
>> (~10kHz). For my model this means I need to run my ADC at ~40MHz (and the
>> FPGA at 5MHz). I'm not using an special memory block, just brams. I'm using
>> ROACH2, and ADC5G (https://casper.berkeley.edu/wiki/ADC1x5000-8). It is
>> possible to run the ADC at such low frequency? What is the minimum
>> acceptable frequency? I tried to find this information in  the ADC
>> datasheet, but I haven't been successful. Also tried compiling simple
>> models at low frequencies, but everything below 600MHz failed.
>>
>> Thanks,
>>
>> Franco
>>
>>
>>
>> --
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>> email to casper+unsubscr...@lists.berkeley.edu.
>> To post to this group, send email to casper@lists.berkeley.edu.
>>
>
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Re: [casper] Matlab - Xilinx Help

[James Smith]

You're going to have to check those environment variables, and see whether
they're actually pointing to their targets.


On Fri, Aug 11, 2017 at 11:29 AM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hi James
>
> I Installed Xilinx under:
>
>  /opt/Xilinx/14.7/ISE_DS
>
> I am not sure to which bin/lin64 matlab is referring because you can find
> them under
>
> /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64
>
> and
>
>
> /opt/Xilinx/14.7/ISE_DS/common/bin/lin64
>
> Thanks for the help
>
> Heystek
>
> On Fri, Aug 11, 2017 at 11:18 AM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Heystek,
>>
>> Where is your Xilinx library installed? See if you can cd to the
>> directory that it refers to?
>>
>> Regards,
>> James
>>
>>
>> On Fri, Aug 11, 2017 at 11:17 AM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Hi Ryan
>>>
>>> Thanks for your help!
>>>
>>> I have added that slash but still get the same error.
>>>
>>> I also had to add the following code to the settibgs64.sh file to get
>>> matlab started:
>>>
>>> if [ -n "$LD_LIBRARY_PATH" ]; then
>>>   LD_LIBRARY_PATH=:${LD_LIBRARY_PATH}:${XILINX_EDK}/lib/lin64;
>>>   export LD_LIBRARY_PATH;
>>>
>>> any other idees?
>>>
>>> Thanks for your help :-)
>>>
>>> Heystek
>>>
>>>
>>>
>>> On Fri, Aug 11, 2017 at 11:02 AM, Ryan Monroe <ryan.m.mon...@gmail.com>
>>> wrote:
>>>
>>>> I just dealt with this problem yesterday!  Somewhere in your startup.m
>>>> file, you should have a line that looks like this:
>>>> xlAddSysgen([getenv('XILINX_PATH'), '/ISE'])
>>>>
>>>> Toss in an extra slash at the end of the path:
>>>> xlAddSysgen([getenv('XILINX_PATH'), '/ISE/'])
>>>>
>>>> Now, I still haven't sorted the REST of the debian/xilinx issues
>>>> that's tomorrows problem :-)
>>>>
>>>>
>>>>
>>>> On 08/11/2017 01:58 AM, Heystek Grobler wrote:
>>>>
>>>> Good day everyone
>>>>
>>>> The last year I have been working on a Ubuntu system with Xilinx and
>>>> Matlab. Currently I am trying to setup a system on a Debian (Jessie) system
>>>> but I get the following error message when staring up matlab:
>>>>
>>>> Cannot access directory lib/lin64. The libraries under the
>>>> path are needed to simulate and netlist designs using blocks
>>>> from Xilinx System Generator for DSP blockset.
>>>>
>>>> Does anyone perhaps know how to solve this?
>>>>
>>>> Thanks for the help
>>>>
>>>> Heystek Grobler
>>>> --
>>>> You received this message because you are subscribed to the Google
>>>> Groups "casper@lists.berkeley.edu" <casper@lists.berkeley.edu> group.
>>>> To unsubscribe from this group and stop receiving emails from it, send
>>>> an email to casper+unsubscr...@lists.berkeley.edu.
>>>> To post to this group, send email to casper@lists.berkeley.edu.
>>>>
>>>>
>>>>
>>> --
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>>
>>
>

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Re: [casper] Matlab - Xilinx Help

[James Smith]

Hello Heystek,

Where is your Xilinx library installed? See if you can cd to the directory
that it refers to?

Regards,
James


On Fri, Aug 11, 2017 at 11:17 AM, Heystek Grobler 
wrote:

> Hi Ryan
>
> Thanks for your help!
>
> I have added that slash but still get the same error.
>
> I also had to add the following code to the settibgs64.sh file to get
> matlab started:
>
> if [ -n "$LD_LIBRARY_PATH" ]; then
>   LD_LIBRARY_PATH=:${LD_LIBRARY_PATH}:${XILINX_EDK}/lib/lin64;
>   export LD_LIBRARY_PATH;
>
> any other idees?
>
> Thanks for your help :-)
>
> Heystek
>
>
>
> On Fri, Aug 11, 2017 at 11:02 AM, Ryan Monroe 
> wrote:
>
>> I just dealt with this problem yesterday!  Somewhere in your startup.m
>> file, you should have a line that looks like this:
>> xlAddSysgen([getenv('XILINX_PATH'), '/ISE'])
>>
>> Toss in an extra slash at the end of the path:
>> xlAddSysgen([getenv('XILINX_PATH'), '/ISE/'])
>>
>> Now, I still haven't sorted the REST of the debian/xilinx issues
>> that's tomorrows problem :-)
>>
>>
>>
>> On 08/11/2017 01:58 AM, Heystek Grobler wrote:
>>
>> Good day everyone
>>
>> The last year I have been working on a Ubuntu system with Xilinx and
>> Matlab. Currently I am trying to setup a system on a Debian (Jessie) system
>> but I get the following error message when staring up matlab:
>>
>> Cannot access directory lib/lin64. The libraries under the
>> path are needed to simulate and netlist designs using blocks
>> from Xilinx System Generator for DSP blockset.
>>
>> Does anyone perhaps know how to solve this?
>>
>> Thanks for the help
>>
>> Heystek Grobler
>> --
>> You received this message because you are subscribed to the Google Groups
>> "casper@lists.berkeley.edu"  group.
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>> email to casper+unsubscr...@lists.berkeley.edu.
>> To post to this group, send email to casper@lists.berkeley.edu.
>>
>>
>>
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Re: [casper] casperfpga attribute error

[James Smith]

Hello Anshu,

Looping back into the mailing list so this is a reference for anyone else
who encounters this.

In order to use the casperfpga package with a ROACH 1 you need the
following:

   - bof file on the ROACH's filesystem, in the /boffiles directory. Either
   this must be on an SD card if you've booted from the SD card, or it must be
   in the appropriate place on the NFS share if you've booted from network. If
   your bof file is in whatever your current directory is, it will still not
   work.
   - fpg file in the current directory, this must correspond to the bof
   file. They're generated together by the casper_xps tool.


Steps are as follows:

import casperfpga
fpga = casperfpga.katcp_fpga.KatcpFpga(roachname) # port and timeout
optional
fpga.system_info["program_filename"] = boffile
fpga.program()
fpga.get_system_information(fpgfile)

And Bob's your uncle. There you go. It's likely that your problem was the
bof file not being accessible to the ROACH.

Just a note, that if you try to program a ROACH and it fails, the tcpborph
server often falls over. You may need to reboot the ROACH. To test this:

ssh root@
ps aux | grep tcpborphserver

Check if the output of that command has  anywhere in it. If so,
reboot your ROACH:
shutdown -r now

before trying to program it again.

Hope this helps,
James


On Fri, Jul 7, 2017 at 10:48 AM, Anshu Singh <anshusingh...@gmail.com>
wrote:

> Hi James,
>
> katchcp version: 0.3.5
> I upgraded to the latest version (0.6). It is working now.
> Now the fpga is connected, but I am not able to program it.
>
>
> The bof file is generated using MATLAB 2013a simulink version. ISE version
> is 14.7.
>
>
> The error is:
>
>
> *KatcpRequestFail*
>
> *Details: *
>
> In [1]: import casperfpga
>
> In [2]: boffile='lfpolv1_2048ch_2017_Jul_06_1811.bof'
>
> In [3]: fpga = casperfpga.katcp_fpga.KatcpFpga('100.100.100.1',7147,10)
>
> In [4]: fpga.is_connected()
> Out[4]: True
>
> In [5]: fpga.system_info['program_filename'] = boffile
>
> In [6]: fpga.program()
> 
> ---
> KatcpRequestFail  Traceback (most recent call
> last)
>  in ()
> > 1 fpga.program()
>
> /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
> program(self, filename)
> 326 complete_okay = True
> 327 if not complete_okay: # Modify to do an extra check
> --> 328 reply, _ = self.katcprequest(name='status',
> request_timeout=1)
> 329 # Not sure whether 1 second is a good timeout here
> 330 if reply.arguments[0] == 'ok':
>
> /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
> katcprequest(self, name, request_timeout, require_ok, request_args)
> 161 'Request %s on host %s failed.\n\t'
> 162 'Request: %s\n\tReply: %s' %
> --> 163 (request.name, self.host, request, reply))
> 164 elif reply.arguments[0] == katcp.Message.INVALID:
> 165 raise KatcpRequestInvalid(
>
> KatcpRequestFail: Request status on host 100.100.100.1 failed.
> Request: ?status
> Reply: !status fail program
>
>
>
> What could be the issue?
>
>
> On Fri, Jul 7, 2017 at 12:37 PM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Anshu,
>>
>> What version of katcp do you have installed? I have seen this issue when
>> the katcp library isn't up-to-date.
>>
>> I think you can get this either from pip or directly from github.
>>
>> Regards,
>> James
>>
>>
>> On Fri, Jul 7, 2017 at 7:39 AM, Anshu Singh <anshusingh...@gmail.com>
>> wrote:
>>
>>> Hello,
>>>
>>> While trying to link the CASPER ROACH1 board to PC, I am getting this
>>> error:
>>>
>>> *AttributeError: 'KatcpFpga' object has no attribute 'callback_request'*
>>>
>>>
>>> The steps followed are as such:
>>>
>>>
>>> In [1]: import casperfpga
>>>
>>> In [2]: fpga=casperfpga.katcp_fpga.KatcpFpga('100.100.100.1',7147,10)
>>> 
>>> ---
>>> AttributeErrorTraceback (most recent call
>>> last)
>>>  in ()
>>> > 1 fpga=casperfpga.katcp_fpga.KatcpFpga('100.100.100.1',7147,10)
>>>
>>> /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
>>> __init__(self, host, port, timeout, connect)
>>>  70 def __init__(self, host, port=7147,

Re: [casper] casperfpga attribute error

[James Smith]

Hello Anshu,

What version of katcp do you have installed? I have seen this issue when
the katcp library isn't up-to-date.

I think you can get this either from pip or directly from github.

Regards,
James


On Fri, Jul 7, 2017 at 7:39 AM, Anshu Singh  wrote:

> Hello,
>
> While trying to link the CASPER ROACH1 board to PC, I am getting this
> error:
>
> *AttributeError: 'KatcpFpga' object has no attribute 'callback_request'*
>
>
> The steps followed are as such:
>
>
> In [1]: import casperfpga
>
> In [2]: fpga=casperfpga.katcp_fpga.KatcpFpga('100.100.100.1',7147,10)
> 
> ---
> AttributeErrorTraceback (most recent call
> last)
>  in ()
> > 1 fpga=casperfpga.katcp_fpga.KatcpFpga('100.100.100.1',7147,10)
>
> /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
> __init__(self, host, port, timeout, connect)
>  70 def __init__(self, host, port=7147, timeout=20.0,
> connect=True):
>  71 async_requester.AsyncRequester.__init__(self, host,
> ---> 72
> self.callback_request,
>  73 max_requests=100)
>  74 katcp.CallbackClient.__init__(self, host, port,
>
> AttributeError: 'KatcpFpga' object has no attribute 'callback_request'
>
>
> I have tried with various versions of casperfpga from github but the error
> remains the same.
> What should be done in order to rectify this error?
>
>
>
> Thanks,
> Anshu
> Junior Research Fellow
> (Int. M.tech-Ph.D Batch 2013)
> Indian Institute of Astrophysics
> Koromangala II Block
> Bangalore-560034
>
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Re: [casper] Help to program roach1

[James Smith]

By way of explanation, I think this has something to do with the version of
tcpborphserver running on ROACH1. Upload_to_ram_and_program isn't
available, so you need to program it manually, and then manually set the
system info fpg file for the python interface to work with, while in ROACH2
this is done in one step. Unfortunately. But apart from that it works very
well.

On Mon, Apr 24, 2017 at 10:06 AM, James Smith <jsm...@ska.ac.za> wrote:

> Hi Heystek,
>
> I adapted casperfpga to work with ROACH but before you take the following
> advice please bear in mind that I haven't updated my working version of it
> for some time: I'm on commit 475ed6826b893230d62da8c7dcdcc2541bea83cf of
> the devel branch, Fri Mar 4 17:27:09 2016. Newer versions *shouldn't* break
> the approach that I use but I can't guarantee it as I haven't tested it.
>
> So with that having been said, this is what I do to fire up ROACH1 boards
> with casperfpga:
> gateware = "my_compiled_file"
> fpga = casperfpga.katcp_fpga.KatcpFpga(RoachIP, roachKATCPPort)
> fpga.system_info['program_filename'] = '%s.bof' % gateware #bof needs to
> be in appropriate directory on roachfs
> fpga.program()
> fpga.get_system_information('%s.fpg' % gateware) # fpg file needs to be
> in same directory as script being run
>
> Proceed as normal with casperfpga. If that doesn't work, post again with
> the error messages you get and we'll see what we can do.
>
> Regards,
> James
>
>
>
> On Mon, Apr 24, 2017 at 9:32 AM, Marc Welz <m...@ska.ac.za> wrote:
>
>> It has been a while, but I am not sure if/how the remote upload was
>> implemented in the roach1 and what its syntax was - it might have been
>> different. Telnet to port 7147 on the roach and type ?help - if there
>> is no progremote, see if you can find something similar ...
>>
>> On Sat, Apr 22, 2017 at 11:26 AM, Heystek Grobler
>> <heystekgrob...@gmail.com> wrote:
>> > Good day
>> >
>> > I have an interesting problem. I'm used to working on a ROACH2 and now I
>> > must do a project on a ROACH1 board.
>> >
>> > When Running the casperfpga package I received this error:
>> >
>> > In [1]: import casperfpga
>> >
>> > In [2]: fpga=casperfpga.katcp_fpga.KatcpFpga('192.168.33.3')
>> > In [3]:
>> > fpga.upload_to_ram_and_program('heystek_tut3_2017_Apr_19_
>> 1133.bof')--
>> -
>> > RuntimeError  Traceback (most recent call
>> last)
>> >  in ()
>> > > 1 fpga.upload_to_ram_and_program('heystek_tut3_2017_Apr_19_
>> 1133.bof')
>> >
>> > /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
>> > upload_to_ram_and_program(self, filename, port, timeout, wait_complete)
>> > 442 if request_result != '':
>> > 443 raise RuntimeError('progremote request(%s) on host
>> %s
>> > failed' %
>> > --> 444(request_result, self.host))
>> > 445
>> > 446 # start the upload thread and join
>> >
>> > RuntimeError: progremote request(Request to client 192.168.33.3
>> failed.) on
>> > host 192.168.33.3 failed
>> >
>> > I then tried running the corr package and I got this error:
>> >
>> > In [7]: fpga=corr.katcp_wrapper.FpgaClient('192.168.33.3',7147)
>> > 
>> ---
>> > TypeError Traceback (most recent call
>> last)
>> >  in ()
>> > > 1 fpga=corr.katcp_wrapper.FpgaClient('192.168.33.3',7147)
>> >
>> > /usr/local/lib/python2.7/dist-packages/corr/katcp_wrapper.pyc in
>> > __init__(self, host, port, tb_limit, timeout, logger)
>> >  86 self.host = host
>> >  87 self._timeout = timeout
>> > ---> 88 self.start(daemon = True)
>> >  89
>> >  90 # async stuff
>> >
>> > TypeError: start() got an unexpected keyword argument 'daemon'
>> >
>> > With my ROACH2 I had to update the kernel and file system with this
>> > instructions to solve the problem:
>> > https://www.mail-archive.com/casper@lists.berkeley.edu/msg06452.html
>> >
>> > but this does not work on the ROACH1 so I reverted back to this kernel
>> and
>> > file system
>> > https://casper.berkeley.edu/wiki/Setting_Up_BORPH_on_ROACH
>> >
>> > What am I do

Re: [casper] Help to program roach1

[James Smith]

Hi Heystek,

I adapted casperfpga to work with ROACH but before you take the following
advice please bear in mind that I haven't updated my working version of it
for some time: I'm on commit 475ed6826b893230d62da8c7dcdcc2541bea83cf of
the devel branch, Fri Mar 4 17:27:09 2016. Newer versions *shouldn't* break
the approach that I use but I can't guarantee it as I haven't tested it.

So with that having been said, this is what I do to fire up ROACH1 boards
with casperfpga:
gateware = "my_compiled_file"
fpga = casperfpga.katcp_fpga.KatcpFpga(RoachIP, roachKATCPPort)
fpga.system_info['program_filename'] = '%s.bof' % gateware #bof needs to be
in appropriate directory on roachfs
fpga.program()
fpga.get_system_information('%s.fpg' % gateware) # fpg file needs to be in
same directory as script being run

Proceed as normal with casperfpga. If that doesn't work, post again with
the error messages you get and we'll see what we can do.

Regards,
James



On Mon, Apr 24, 2017 at 9:32 AM, Marc Welz  wrote:

> It has been a while, but I am not sure if/how the remote upload was
> implemented in the roach1 and what its syntax was - it might have been
> different. Telnet to port 7147 on the roach and type ?help - if there
> is no progremote, see if you can find something similar ...
>
> On Sat, Apr 22, 2017 at 11:26 AM, Heystek Grobler
>  wrote:
> > Good day
> >
> > I have an interesting problem. I'm used to working on a ROACH2 and now I
> > must do a project on a ROACH1 board.
> >
> > When Running the casperfpga package I received this error:
> >
> > In [1]: import casperfpga
> >
> > In [2]: fpga=casperfpga.katcp_fpga.KatcpFpga('192.168.33.3')
> > In [3]:
> > fpga.upload_to_ram_and_program('heystek_tut3_2017_
> Apr_19_1133.bof')---
> 
> > RuntimeError  Traceback (most recent call
> last)
> >  in ()
> > > 1 fpga.upload_to_ram_and_program('heystek_tut3_2017_
> Apr_19_1133.bof')
> >
> > /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
> > upload_to_ram_and_program(self, filename, port, timeout, wait_complete)
> > 442 if request_result != '':
> > 443 raise RuntimeError('progremote request(%s) on host %s
> > failed' %
> > --> 444(request_result, self.host))
> > 445
> > 446 # start the upload thread and join
> >
> > RuntimeError: progremote request(Request to client 192.168.33.3 failed.)
> on
> > host 192.168.33.3 failed
> >
> > I then tried running the corr package and I got this error:
> >
> > In [7]: fpga=corr.katcp_wrapper.FpgaClient('192.168.33.3',7147)
> > 
> ---
> > TypeError Traceback (most recent call
> last)
> >  in ()
> > > 1 fpga=corr.katcp_wrapper.FpgaClient('192.168.33.3',7147)
> >
> > /usr/local/lib/python2.7/dist-packages/corr/katcp_wrapper.pyc in
> > __init__(self, host, port, tb_limit, timeout, logger)
> >  86 self.host = host
> >  87 self._timeout = timeout
> > ---> 88 self.start(daemon = True)
> >  89
> >  90 # async stuff
> >
> > TypeError: start() got an unexpected keyword argument 'daemon'
> >
> > With my ROACH2 I had to update the kernel and file system with this
> > instructions to solve the problem:
> > https://www.mail-archive.com/casper@lists.berkeley.edu/msg06452.html
> >
> > but this does not work on the ROACH1 so I reverted back to this kernel
> and
> > file system
> > https://casper.berkeley.edu/wiki/Setting_Up_BORPH_on_ROACH
> >
> > What am I doing wrong?
> >
> > Thanks for the help
> >
> > Heystek
> >
> > --
> > You received this message because you are subscribed to the Google Groups
> > "casper@lists.berkeley.edu" group.
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Re: [casper] Problem uploading .bof file to Roach1

[James Smith]

Hello Heystek,

If you're not sure on Marc's suggestion -- ssh in and use "df -h" and it
should tell you how much space you have left on the ROACH's filesystems.

Regards,
James


On Mon, May 15, 2017 at 1:48 PM, Marc Welz  wrote:

> Long shot - could you have run out of space on the roach ?
>
> On Mon, May 15, 2017 at 7:39 AM, Heystek Grobler
>  wrote:
> > Good day everyone
> >
> > I have encountered a weird problem. Everything was working fine until
> today.
> > I cant upload a .bof file to my roach1. I keep getting this error:
> >
> > #log error 2947729786047 poco ulpoad\_process\_exitet\_with\_code\_69
> >
> > I have tried uploading the file through kapcp and telnet but poco errors
> > keeps popping up.
> >
> > Does anyone have an idee whats going on?
> >
> > Thanks for the help
> >
> > Heystek
> >
> > --
> > You received this message because you are subscribed to the Google Groups
> > "casper@lists.berkeley.edu" group.
> > To unsubscribe from this group and stop receiving emails from it, send an
> > email to casper+unsubscr...@lists.berkeley.edu.
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Re: [casper] katadc

[James Smith]

Hello Heystek,

If you're not getting a spectrum, what are you getting? How have you
connected your katadc? (Both physically and with the yellow block)?

Regards,
James


On Wed, May 17, 2017 at 9:46 AM, Heystek Grobler 
wrote:

> Good day everyone
>
> I am trying to implement tutorial 3 on a ROACH1 with a katadc. I have
> previously done it on a ROACH2 with the iadc.
>
> For some reason I am struggling to get the katadc to work. I am using the
> katadc yellow block but I cant generate a spectrum. I hooked up an signal
> generator to the katadc and gave it a square wave at 50MHz.
>
> Am I doing something stupid? Or is there another yellow block that I
> should rather use.
>
> Have a great day
>
> Heystek Grobler
>
> --
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Re: [casper] katadc

[James Smith]

Hello Heystek,

It's conventional to use the sync0..3 outputs of the KatADC (through an OR
gate) into the Sync input of your PFB. This should be a PPS signal.

Do you have a PPS signal and clock reference going into your katadc? What
speed (i.e. FPGA clock frequency) are you running at? Try doing some
initial debugging e.g. in casperfpga in python with
fpga.estimate_clock_freq() or something like that, I can't remember the
exact name of the function.

It also helps to connect that OR-gated sync signal to a 1-bit counter and
to an LED output so you can actually see if a PPS is getting to the right
place.

Regards,
James


On Wed, May 17, 2017 at 9:57 AM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hi James
>
> Physically I have connected the signal generator to the katadc's "i" input
> connector with a square wave at 50MHz with amplitude of 2Vpp.
>
> The simulink model is connected as follows:
>
> [image: Inline image 2]
> If I program the ROACH and pull a spectrum of It I get nothing (only a
> straight line through zero) or sometimes I get the most random noise that
> is all over the place.
>
> Heystek
>
>
>
>
>
>
>
>
>
> On Wed, May 17, 2017 at 9:48 AM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Heystek,
>>
>> If you're not getting a spectrum, what are you getting? How have you
>> connected your katadc? (Both physically and with the yellow block)?
>>
>> Regards,
>> James
>>
>>
>> On Wed, May 17, 2017 at 9:46 AM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Good day everyone
>>>
>>> I am trying to implement tutorial 3 on a ROACH1 with a katadc. I have
>>> previously done it on a ROACH2 with the iadc.
>>>
>>> For some reason I am struggling to get the katadc to work. I am using
>>> the katadc yellow block but I cant generate a spectrum. I hooked up an
>>> signal generator to the katadc and gave it a square wave at 50MHz.
>>>
>>> Am I doing something stupid? Or is there another yellow block that I
>>> should rather use.
>>>
>>> Have a great day
>>>
>>> Heystek Grobler
>>>
>>> --
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>>> Groups "casper@lists.berkeley.edu" group.
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>>> an email to casper+unsubscr...@lists.berkeley.edu.
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>>>
>>
>>
>

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Re: [casper] Clock signal question

[James Smith]

Hello Heystek,

On Thu, May 25, 2017 at 2:50 PM, Heystek Grobler 
wrote:

> How does the gain work when pulling a spectrum out of the BRAMS?


You're going to need to be a bit more specific. I'm not too sure what
you're trying to do here.

Regards,
James

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Re: [casper] timing errors

[James Smith]

Hello Yunpeng,

Just to echo what Michael and Vereese said - those tools can help you get a
bit more insight into what's going on, and how badly your timing problem
is, but the timing report should tell you how by how much you're missing
timing (should be some nanosecond value).

If it's just a small amount then sprinkling a few delay blocks in-between
major sections of your design, or increasing adder / multiplier latency in
your DSP blocks can usually help.

Regards,
James


On Sat, Jun 3, 2017 at 6:54 PM, Michael D'Cruze <
michael.dcr...@postgrad.manchester.ac.uk> wrote:

> Hi Yunpeng, all,
>
>
>
> I recently wrote a memo which describes how you can use Xilinx
> SmartXplorer to help with timing issues. Have a look on the casper wiki in
> the Memos section: https://casper.berkeley.edu/
> wiki/images/f/f8/SmartXplorer_memo.pdf . It isn’t a free pass – you need
> to get fairly close using knowledge of individual hardware types on the
> FPGA, and you need to space out your design reasonably, by using pipelines.
> But it should help get over the final hurdle if you’re doing a reasonable
> job initially.
>
>
>
> Best,
>
> Michael
>
>
>
> *From:* 门云鹏 [mailto:yp...@pku.edu.cn]
> *Sent:* 03 June 2017 16:00
> *To:* casper@lists.berkeley.edu
> *Subject:* [casper] timing errors
>
>
>
> Dear all,
>
> I am using ROACH2 to develop digital receiving backend, but I often encounter 
> timing errors when I run casper_xps toolflow. I wonder if there is any 
> general solution to these timing errors.
>
> Thanks a lot,
>
> Yunpeng
>
>
>
> 
> ---
>
> Yunpeng Men
>
> PhD student
>
> Department of Astronomy & Kavli Institute for Astronomy and
> Astrophysics, Peking University
>
> Yi He Yuan Lu 5, Hai Dian Qu, Beijing 100871, P. R. China
>
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Re: Re: [casper] timing errors

[James Smith]

Hello Yunpeng,

Black boxing can help speed up compile time but the place-and-route needs
to run every time, so it won't really help the design meet timing. In my
experience that's the thing that takes long.

Good luck.

Regards,
James




On Mon, Jun 5, 2017 at 9:58 AM, Vereese Van Tonder <vere...@ska.ac.za>
wrote:

> Hi Yunpeng,
>
> You can try "Black Boxing" parts of your design, that you know works.
> There's a tutorial on the CASPER wiki here:
>
> https://casper.berkeley.edu/wiki/Tutorial_HDL_Black_Box
>
> I hope this helps.
>
>
> On Sun, Jun 4, 2017 at 4:43 AM, 门云鹏 <yp...@pku.edu.cn> wrote:
>
>> Hi James, Michael, and Vereese,
>>
>> Thanks for your reply. I have read the timing report to find the failing
>> paths, and tried to add delay blocks or increasing adder / multiplier
>> latency. It works well but not always, especially for timing errors in some
>> yellow blocks, for instance
>>
>> I will try SmartXplorer and PlanAead, and see if they work.
>>
>> What's more, the casper_xps toolflow often takes a few hours, which makes
>> me crazy (>﹏<). I guess this is because timing constraints are difficult
>> to meet. I wonder if there is any good method to accelerate the xps
>> toolflow. (Map uses 2 processors, and par uses 4 processors by default. The
>> cpu is @2.70GHz 8M)
>>
>> Thank you all again,
>>
>> Yunpeng
>>
>>
>>
>> 
>> ---
>> Yunpeng Men
>> PhD student
>> Department of Astronomy & Kavli Institute for Astronomy and
>> Astrophysics, Peking University
>> Yi He Yuan Lu 5, Hai Dian Qu, Beijing 100871, P. R. China
>>
>> -原始邮件-
>> *发件人:*"James Smith" <jsm...@ska.ac.za>
>> *发送时间:*2017-06-04 01:44:39 (星期日)
>> *收件人:* "Michael D'Cruze" <michael.dcr...@postgrad.manchester.ac.uk>
>> *抄送:* "门云鹏" <yp...@pku.edu.cn>, "casper@lists.berkeley.edu" <
>> casper@lists.berkeley.edu>
>> *主题:* Re: [casper] timing errors
>>
>>
>> Hello Yunpeng,
>>
>> Just to echo what Michael and Vereese said - those tools can help you get
>> a bit more insight into what's going on, and how badly your timing problem
>> is, but the timing report should tell you how by how much you're missing
>> timing (should be some nanosecond value).
>>
>> If it's just a small amount then sprinkling a few delay blocks in-between
>> major sections of your design, or increasing adder / multiplier latency in
>> your DSP blocks can usually help.
>>
>> Regards,
>> James
>>
>>
>> On Sat, Jun 3, 2017 at 6:54 PM, Michael D'Cruze <
>> michael.dcr...@postgrad.manchester.ac.uk> wrote:
>>
>>> Hi Yunpeng, all,
>>>
>>>
>>>
>>> I recently wrote a memo which describes how you can use Xilinx
>>> SmartXplorer to help with timing issues. Have a look on the casper wiki in
>>> the Memos section: https://casper.berkeley.edu/wi
>>> ki/images/f/f8/SmartXplorer_memo.pdf . It isn’t a free pass – you need
>>> to get fairly close using knowledge of individual hardware types on the
>>> FPGA, and you need to space out your design reasonably, by using pipelines.
>>> But it should help get over the final hurdle if you’re doing a reasonable
>>> job initially.
>>>
>>>
>>>
>>> Best,
>>>
>>> Michael
>>>
>>>
>>>
>>> *From:* 门云鹏 [mailto:yp...@pku.edu.cn]
>>> *Sent:* 03 June 2017 16:00
>>> *To:* casper@lists.berkeley.edu
>>> *Subject:* [casper] timing errors
>>>
>>>
>>>
>>> Dear all,
>>>
>>> I am using ROACH2 to develop digital receiving backend, but I often 
>>> encounter timing errors when I run casper_xps toolflow. I wonder if there 
>>> is any general solution to these timing errors.
>>>
>>> Thanks a lot,
>>>
>>> Yunpeng
>>>
>>>
>>>
>>> 
>>> ---
>>>
>>> Yunpeng Men
>>>
>>> PhD student
>>>
>>> Department of Astronomy & Kavli Institute for Astronomy and
>>> Astrophysics, Peking University
>>>
>>> Yi He Yuan Lu 5, Hai Dian Qu, Beijing 100871, P. R. China
>>>
>>> --
>>> You received this message because you are subscribed to the Google
>>> Groups "casper@lists.ber

Re: [casper] Error in tut3.py: No module named spead64_48

[James Smith]

Hello Xavier,

Casperfpga is lacking a bit of documentation, but see Jason Manley's email
to the list from yesterday. It's got a bit of a primer, and it works
broadly similarly to Corr but with some added useful time-saving features.
It would be good to get around to writing a user manual for it at some
point...

Regards,
James


On Mon, Jun 12, 2017 at 5:04 PM, Xavier Bosch 
wrote:

> Hi Jack,
> Yes, I only need it for communications, I do not need the corr_functions.
> I could not find documentation on casperfpga, so I end using the
> katcp_wrapper.py together with katcp==0.5.1, a version of what you
> suggested.
> For now it is working.
> Thank you,
> XB
>
>
>
>
> On Wed, Jun 7, 2017 at 8:45 AM Jack Hickish  wrote:
>
>> Hi Xavier,
>>
>> Assuming you're only going to use the katcp stuff in Corr to talk to your
>> boards, you don't really need corr_functions at all.
>>
>> In fact you can edit the __init__.py file in Corr/ to remove a lot of the
>> superfluous imports if they are causing you trouble.
>> The real solution is that everyone should be using the casperfpga
>> package, not Corr, but I don't know if this is adequately documented on the
>> wiki (I still use corr myself, because it works and I don't like change).
>> Purging the tutorials and wiki of suggestions to install corr will be part
>> of the workshop prep work in the next couple of months.
>>
>> Jack
>>
>> PS. When you get the corr import working, you might find you get another
>> error(!) when you try to make a connection to a board. I think you'll find
>> you need to downgrade your katcp version (my local setup uses 0.5.4).
>>
>>
>> On Mon, Jun 5, 2017, 12:33 PM Xavier Bosch 
>> wrote:
>>
>>> hi everyone,
>>> I am new in this list and also new in the CASPER world. I am learning
>>> through the tutorials provided in https://github.com/casper-
>>> astro/tutorials_devel.git . I am using Ubuntu 14.04.5 and I been able
>>> to compile and sensitize (generate the .bof file) up to tut3, included. Now
>>> I am trying to get data out of the ROACH2 using the Python file that comes
>>> with the tutorial and I am getting the following error:
>>>
>>>   File "/usr/local/lib/python2.7/dist-packages/corr/corr_functions.py",
>>> line 55, in 
>>> import spead64_48 as spead
>>> ImportError: No module named spead64_48
>>>
>>> I have the following Python modules installed in my system:
>>> 
>>> corr==0.7.3
>>> construct==2.8.12  -> I had to downgrade it to==2.5.3 because it was
>>> giving me trouble.
>>> katcp==0.6.1
>>> numpy==1.12.1
>>> spead==0.5.1
>>> ...
>>>
>>> but there is nothing like spead64_48 in my system. I tried changing
>>> thing here and there but nothing worked so far.
>>> What I am doing wrong?
>>> Thanks,
>>> XB
>>>
>>> --
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Re: [casper] katadc help in simulink

[James Smith]

Hello Heystek,

The KatADC is described here:
https://casper.berkeley.edu/wiki/KatADC

It's got two channels which you need to enable if you want to use them, and
31.5 dB variable attenuators which you need to set.

So if you want them to be on all the time, just hard-wire some 1s into en0
and en1. I'd suggest putting software registers into atten0 and atten1 then
writing to them from a Python script. You can adjust the attenuation from 0
dB to 31.5 dB in 0.5 dB increments using a 5-bit number.

Regards,
James



On Mon, May 8, 2017 at 2:17 PM, Heystek Grobler 
wrote:

> Good day everyone
>
> I have a ROACH1 board with a katadc. I have located the katadc under the
> CAPER XPS Blockset (I am trying to do tut3). I have swapped the iadc for
> the katadc.
>
> The problem is, the katadc has the following inputs:
> en0
> atten0
> en1
> atten1
>
> I need to connect something to those inputs to be able to compile a bof
> file. Does anyone perhaps know what inputs I should connect/use?
>
> Have a great day
>
> Thanks for the help
>
> Heystek Grobler
>
>
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Re: [casper] katadc help in simulink

[James Smith]

Hello Heystek,

It's probably better practice to use software registers (or you could just
use one register for all four inputs and slice it out), but you should also
have been able to use Xilinx constants, that should have compiled.

Regards,
James


On Mon, May 8, 2017 at 3:33 PM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hi James
>
> Thanks for the help!! I had to add software registers to en0 and en1 as
> well but know it compiles.
>
> Thanks for the help!!
>
> I really apreciate it
>
> Heystek
>
> On Mon, May 8, 2017 at 2:23 PM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Heystek,
>>
>> The KatADC is described here:
>> https://casper.berkeley.edu/wiki/KatADC
>>
>> It's got two channels which you need to enable if you want to use them,
>> and 31.5 dB variable attenuators which you need to set.
>>
>> So if you want them to be on all the time, just hard-wire some 1s into
>> en0 and en1. I'd suggest putting software registers into atten0 and atten1
>> then writing to them from a Python script. You can adjust the attenuation
>> from 0 dB to 31.5 dB in 0.5 dB increments using a 5-bit number.
>>
>> Regards,
>> James
>>
>>
>>
>> On Mon, May 8, 2017 at 2:17 PM, Heystek Grobler <heystekgrob...@gmail.com
>> > wrote:
>>
>>> Good day everyone
>>>
>>> I have a ROACH1 board with a katadc. I have located the katadc under the
>>> CAPER XPS Blockset (I am trying to do tut3). I have swapped the iadc for
>>> the katadc.
>>>
>>> The problem is, the katadc has the following inputs:
>>> en0
>>> atten0
>>> en1
>>> atten1
>>>
>>> I need to connect something to those inputs to be able to compile a bof
>>> file. Does anyone perhaps know what inputs I should connect/use?
>>>
>>> Have a great day
>>>
>>> Thanks for the help
>>>
>>> Heystek Grobler
>>>
>>>
>>> --
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>>>
>>
>>
>

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Re: [casper] ROACH1 Programming issues

[James Smith]

Hello Mugundhan,

Please describe your context a bit more - what libraries are you using?
Please also paste the error that you get? (and perhaps the code you used to
generate the error.)

Regards,
James


On Thu, Oct 12, 2017 at 12:17 PM, Mugundhan vijayaraghavan <
v.vaishnav151...@gmail.com> wrote:

> Hi,
>
> I'm facing a strange problem. I have an iADC, which I've connected to
> roach1 and have compiled a program to acquire raw samples from it. The
> simulation, compilation and generation works fine and I get the bof and the
> fpg files, which i place in their respective locations, and the ROACH gets
> programmed well.
>
> I also developed a iADC spectropolarimeter and generated the fpg and bof
> files and placed them in their locations, but now when I try programming
> the ROACH, i get Katcp request time out error. If i reprogram the first bof
> file, it works fine, but repeated compilation and program cycles have
> failed for hte second model, with the same katcp request failed error.
>
> Can someone kindly guide me solving it ?
>
> Thank you,
>
> --
> V. Mugundhan
> SRF, IIA
>
> --
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Re: [casper] ROACH1 Programming issues

[James Smith]

Hello Mugundhan,

Casperfpga is a work in progress and unfortunately some of the more recent
developments will have broken compatibility with ROACH1. Its main focus at
the moment is SKARAB / ROACH2.

I use the following commit to work on ROACH1:
avnuser@planck:~/SKASoftware/casperfpga$ git show
commit 475ed6826b893230d62da8c7dcdcc2541bea83cf
Merge: 9835009 7402b29
Author: Paul Prozesky <pa...@ska.ac.za>
Date:   Fri Mar 4 17:27:09 2016 +0200

Merge branch 'devel' of github.com:ska-sa/casperfpga into devel

Try installing casperfpga from that particular git commit and you'll likely
be more successful.

Also, before you use the fpga.program() function, you need to set the bof
file in the system information - I think I have mentioned how to do this in
the history of the mailing list somewhere before.

Let me know if it works.

Regards,
James


On Thu, Oct 12, 2017 at 12:35 PM, Mugundhan vijayaraghavan <
v.vaishnav151...@gmail.com> wrote:

> And I'm using the latest version of casperfpga library and katcp version.
>
> On Thu, Oct 12, 2017 at 3:56 PM, Mugundhan vijayaraghavan <
> v.vaishnav151...@gmail.com> wrote:
>
>> Hello James,
>>
>> I'm attaching the model files of the first and the second designs, along
>> with the bof and the fga files. I used the ipython terminal for programming
>> the fpga in both cases. The error I obtained is attached in a text file.
>>
>> Hope this helps,
>>
>> Thank you,
>>
>> Mugundhan V.
>>
>>
>>
>> On Thu, Oct 12, 2017 at 3:49 PM, James Smith <jsm...@ska.ac.za> wrote:
>>
>>> Hello Mugundhan,
>>>
>>> Please describe your context a bit more - what libraries are you using?
>>> Please also paste the error that you get? (and perhaps the code you used to
>>> generate the error.)
>>>
>>> Regards,
>>> James
>>>
>>>
>>> On Thu, Oct 12, 2017 at 12:17 PM, Mugundhan vijayaraghavan <
>>> v.vaishnav151...@gmail.com> wrote:
>>>
>>>> Hi,
>>>>
>>>> I'm facing a strange problem. I have an iADC, which I've connected to
>>>> roach1 and have compiled a program to acquire raw samples from it. The
>>>> simulation, compilation and generation works fine and I get the bof and the
>>>> fpg files, which i place in their respective locations, and the ROACH gets
>>>> programmed well.
>>>>
>>>> I also developed a iADC spectropolarimeter and generated the fpg and
>>>> bof files and placed them in their locations, but now when I try
>>>> programming the ROACH, i get Katcp request time out error. If i reprogram
>>>> the first bof file, it works fine, but repeated compilation and program
>>>> cycles have failed for hte second model, with the same katcp request failed
>>>> error.
>>>>
>>>> Can someone kindly guide me solving it ?
>>>>
>>>> Thank you,
>>>>
>>>> --
>>>> V. Mugundhan
>>>> SRF, IIA
>>>>
>>>> --
>>>> You received this message because you are subscribed to the Google
>>>> Groups "casper@lists.berkeley.edu" group.
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>>>> an email to casper+unsubscr...@lists.berkeley.edu.
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>>>>
>>>
>>> --
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>>>
>>
>>
>>
>> --
>> V. Mugundhan
>> SRF, IIA
>>
>
>
>
> --
> V. Mugundhan
> SRF, IIA
>

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Re: [casper] Choice of ADC for 16-element interferometer

[James Smith]

Siddharth,

ROACH1 is quite deprecated now, we don't recommend it for new projects.
There are still a number of them floating around, but no active development
on the libraries to support them.

I don't know of any ADCs with more than 2 inputs. You'd also be quite
pressed to fit a full 16-element correlator onto a single ROACH. With a
ROACH2 you may manage if it's simple.

Regards,
James


On Fri, Oct 20, 2017 at 12:26 PM, Siddharth Malu 
wrote:

> Dear CASPERites,
>
> Many, thanks, Indrajit, for your reply. Are there ADCs that can be used
> with ROACH1 and have more than 2 inputs? I am starting from scratch, and as
> far as I can see from CASPER websites, it would be easier to set up ROACH1
> as compared to ROACH2, and given the large number of ROACH1 users, it may
> be easier to get help on ROACH1. But I'd very much like to hear opinions
> from CASPERites about this.
>
> Many thanks, and look forward to your replies.
>
> Best regards,
> Siddharth
>
> On Fri, Oct 20, 2017 at 11:56 AM, Indrajit Vittal Barve <
> indra...@iiap.res.in> wrote:
>
>> Dear siddharth,
>>
>> Please go through this message. ADC16 is not (yet?) supported on ROACH1.
>> So consider with ROACH 2.
>>
>>
>>
>> https://www.mail-archive.com/casper@lists.berkeley.edu/msg06320.html
>>
>>
>>
>> With  regards
>> Indrajit
>> On 20 Oct 2017 11:25 am, Siddharth Savyasachi Malu <
>> savyasachi.i...@gmail.com> wrote:
>>
>> Dear CASPERites,
>>
>> I am trying to design a cheap 16-element interferometer using a ROACH1
>> board with 250-500 MHz bandwidth. Would you suggest the ADC16x250-8 for
>> this purpose?
>>
>> Best regards,
>> Siddharth
>> --
>> Siddharth Malu
>> Centre of Astronomy
>> Indian Institute of Technology Indore
>> Indore, India
>>
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Re: [casper] Choice of ADC for 16-element interferometer

[James Smith]

If you've got a ROACH2, there's not much point in getting started on a
ROACH1, the tools are more mature on a ROACH2.

I can't provide much support myself, but there are other users in the
mailing list who might be able to get you started.


On Fri, Oct 20, 2017 at 12:42 PM, Siddharth Savyasachi Malu <
savyasachi.i...@gmail.com> wrote:

> Thank you, James, for your reply. I have tried ROACH2v2, and the
> programmer working with me had some issues porting their ROACH1 design to
> ROACH2. However, it looks like ROACH2 would be the way to go, and that the
> ADC16x250-8 is usable only with ROACH2 currently.
>
> In this context, may I ask if there is someone who has experience setting
> up ADC16x250-8 with ROACH2, with 4 or 8 inputs? Also, can a single ROACH2v2
> board have two of these ADCs?
>
> Also, I think it would be worthwhile starting with a smaller version of an
> interferometer, say a 4-element, 250 MHz bandwidth version. Is there any
> chance I might be able to borrow a ROACH1 for about 3 months, if anyone has
> an old board they aren't using anymore?
>
> Thanks,
> Siddharth
>
> On Fri, Oct 20, 2017 at 3:58 PM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Siddharth,
>>
>> ROACH1 is quite deprecated now, we don't recommend it for new projects.
>> There are still a number of them floating around, but no active development
>> on the libraries to support them.
>>
>> I don't know of any ADCs with more than 2 inputs. You'd also be quite
>> pressed to fit a full 16-element correlator onto a single ROACH. With a
>> ROACH2 you may manage if it's simple.
>>
>> Regards,
>> James
>>
>>
>> On Fri, Oct 20, 2017 at 12:26 PM, Siddharth Malu <
>> savyasachi.i...@gmail.com> wrote:
>>
>>> Dear CASPERites,
>>>
>>> Many, thanks, Indrajit, for your reply. Are there ADCs that can be used
>>> with ROACH1 and have more than 2 inputs? I am starting from scratch, and as
>>> far as I can see from CASPER websites, it would be easier to set up ROACH1
>>> as compared to ROACH2, and given the large number of ROACH1 users, it may
>>> be easier to get help on ROACH1. But I'd very much like to hear opinions
>>> from CASPERites about this.
>>>
>>> Many thanks, and look forward to your replies.
>>>
>>> Best regards,
>>> Siddharth
>>>
>>> On Fri, Oct 20, 2017 at 11:56 AM, Indrajit Vittal Barve <
>>> indra...@iiap.res.in> wrote:
>>>
>>>> Dear siddharth,
>>>>
>>>> Please go through this message. ADC16 is not (yet?) supported on
>>>> ROACH1.  So consider with ROACH 2.
>>>>
>>>>
>>>>
>>>> https://www.mail-archive.com/casper@lists.berkeley.edu/msg06320.html
>>>>
>>>>
>>>>
>>>> With  regards
>>>> Indrajit
>>>> On 20 Oct 2017 11:25 am, Siddharth Savyasachi Malu <
>>>> savyasachi.i...@gmail.com> wrote:
>>>>
>>>> Dear CASPERites,
>>>>
>>>> I am trying to design a cheap 16-element interferometer using a ROACH1
>>>> board with 250-500 MHz bandwidth. Would you suggest the ADC16x250-8 for
>>>> this purpose?
>>>>
>>>> Best regards,
>>>> Siddharth
>>>> --
>>>> Siddharth Malu
>>>> Centre of Astronomy
>>>> Indian Institute of Technology Indore
>>>> Indore, India
>>>>
>>>> --
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>>>>
>>>>
>>> --
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>>
>>
>

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Re: [casper] ROACH2 4-element correlator compilation error

[James Smith]

Hello Bela,

I second Andrew's suggestion, but note also that "Error due to multiple
causes" can often mean that somewhere in the design there's a name that
Matlab doesn't like. Avoid using any capital letters or spaces in block
names, and avoid using names that are too long - if the full file-path of
the design contains capital letters, spaces or too many characters (I think
64 is the limit?) then it can fail.

Other Casperites can possibly correct me if I'm wrong on this but this is
the convention that I tend to follow.

Regards,
James


On Thu, Jan 18, 2018 at 8:23 AM, Andrew Martens  wrote:

> Hi Bela
>
> Please open you design in Matlab/Simulink and then Press 'Ctrl-D' (hold
> the Ctrl key down and hit the D key at the same time). This will do an
> 'Update' on your design and will give more useful error messages.
>
> Regards
> Andrew
>
> On Thu, Jan 18, 2018 at 7:28 AM, Bela Dixit  wrote:
>
>> Hi CASPERites,
>>
>> I am working on 5Gsps and ROACH2 boards.
>> While compiling four element 300MHz bandwidth correlator design, I am facing 
>> some error.
>> Kindly help me to sort out that error.
>> Please find the attached snapshot of error.
>>
>>
>>
>> Thanks & Regards,
>>
>> Bela Dixit
>>
>> --
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>> "casper@lists.berkeley.edu" group.
>> To unsubscribe from this group and stop receiving emails from it, send an
>> email to casper+unsubscr...@lists.berkeley.edu.
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>>
>
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Re: [casper] ROACH2 4-element correlator compilation error

[James Smith]

Hello Bela,

That looks fine - there are normally lots of warnings. You just need to
wait, these compiles can take several hours sometimes depending on their
complexity. Average for mine have been 1.5-2 hours.

Regards,
James


On Tue, Jan 30, 2018 at 8:48 AM, Bela Dixit <dixitb...@gmail.com> wrote:

> Thanks Andrew and James for suggestion.
> I had  updated the casper block by ctrl-D. Compilation proceed but still
> there is some problem in synthesis part.
> Kindly help me to sort out this problem.
> Please find the attached snapshot of command window.
> Thanks & Regards,
> Bela
>
>>
>>> On Thu, Jan 18, 2018 at 12:34 PM, James Smith <jsm...@ska.ac.za> wrote:
>>>
>>>> Hello Bela,
>>>>
>>>> I second Andrew's suggestion, but note also that "Error due to multiple
>>>> causes" can often mean that somewhere in the design there's a name that
>>>> Matlab doesn't like. Avoid using any capital letters or spaces in block
>>>> names, and avoid using names that are too long - if the full file-path of
>>>> the design contains capital letters, spaces or too many characters (I think
>>>> 64 is the limit?) then it can fail.
>>>>
>>>> Other Casperites can possibly correct me if I'm wrong on this but this
>>>> is the convention that I tend to follow.
>>>>
>>>> Regards,
>>>> James
>>>>
>>>>
>>>> On Thu, Jan 18, 2018 at 8:23 AM, Andrew Martens <and...@ska.ac.za>
>>>> wrote:
>>>>
>>>>> Hi Bela
>>>>>
>>>>> Please open you design in Matlab/Simulink and then Press 'Ctrl-D'
>>>>> (hold the Ctrl key down and hit the D key at the same time). This will do
>>>>> an 'Update' on your design and will give more useful error messages.
>>>>>
>>>>> Regards
>>>>> Andrew
>>>>>
>>>>> On Thu, Jan 18, 2018 at 7:28 AM, Bela Dixit <dixitb...@gmail.com>
>>>>> wrote:
>>>>>
>>>>>> Hi CASPERites,
>>>>>>
>>>>>> I am working on 5Gsps and ROACH2 boards.
>>>>>> While compiling four element 300MHz bandwidth correlator design, I am 
>>>>>> facing some error.
>>>>>> Kindly help me to sort out that error.
>>>>>> Please find the attached snapshot of error.
>>>>>>
>>>>>>
>>>>>>
>>>>>> Thanks & Regards,
>>>>>>
>>>>>> Bela Dixit
>>>>>>
>>>>>> --
>>>>>> You received this message because you are subscribed to the Google
>>>>>> Groups "casper@lists.berkeley.edu" group.
>>>>>> To unsubscribe from this group and stop receiving emails from it,
>>>>>> send an email to casper+unsubscr...@lists.berkeley.edu.
>>>>>> To post to this group, send email to casper@lists.berkeley.edu.
>>>>>>
>>>>>
>>>>> --
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>>>>> To unsubscribe from this group and stop receiving emails from it, send
>>>>> an email to casper+unsubscr...@lists.berkeley.edu.
>>>>> To post to this group, send email to casper@lists.berkeley.edu.
>>>>>
>>>>
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>>>
>>>
>>
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Re: [casper] ROACH2 4-element correlator compilation error

[James Smith]

Hello Bela,

That is a bit long - what happens if you just do Ctrl+D? Does it return any
messages?

I also find that on Simulink if you select *Display -> Signals & Ports ->
Port Data Types *it produces a more useful result.

Regards,
James


On Tue, Jan 30, 2018 at 9:33 AM, Bela Dixit <dixitb...@gmail.com> wrote:

> Hie James,
>
> I have waited around 7 to 9 hours, still I am getting same warnings.
>
> Thanks & Regards,
> Bela
>
>
> On Tue, Jan 30, 2018 at 12:22 PM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Bela,
>>
>> That looks fine - there are normally lots of warnings. You just need to
>> wait, these compiles can take several hours sometimes depending on their
>> complexity. Average for mine have been 1.5-2 hours.
>>
>> Regards,
>> James
>>
>>
>> On Tue, Jan 30, 2018 at 8:48 AM, Bela Dixit <dixitb...@gmail.com> wrote:
>>
>>> Thanks Andrew and James for suggestion.
>>> I had  updated the casper block by ctrl-D. Compilation proceed but still
>>> there is some problem in synthesis part.
>>> Kindly help me to sort out this problem.
>>> Please find the attached snapshot of command window.
>>> Thanks & Regards,
>>> Bela
>>>
>>>>
>>>>> On Thu, Jan 18, 2018 at 12:34 PM, James Smith <jsm...@ska.ac.za>
>>>>> wrote:
>>>>>
>>>>>> Hello Bela,
>>>>>>
>>>>>> I second Andrew's suggestion, but note also that "Error due to
>>>>>> multiple causes" can often mean that somewhere in the design there's a 
>>>>>> name
>>>>>> that Matlab doesn't like. Avoid using any capital letters or spaces in
>>>>>> block names, and avoid using names that are too long - if the full
>>>>>> file-path of the design contains capital letters, spaces or too many
>>>>>> characters (I think 64 is the limit?) then it can fail.
>>>>>>
>>>>>> Other Casperites can possibly correct me if I'm wrong on this but
>>>>>> this is the convention that I tend to follow.
>>>>>>
>>>>>> Regards,
>>>>>> James
>>>>>>
>>>>>>
>>>>>> On Thu, Jan 18, 2018 at 8:23 AM, Andrew Martens <and...@ska.ac.za>
>>>>>> wrote:
>>>>>>
>>>>>>> Hi Bela
>>>>>>>
>>>>>>> Please open you design in Matlab/Simulink and then Press 'Ctrl-D'
>>>>>>> (hold the Ctrl key down and hit the D key at the same time). This will 
>>>>>>> do
>>>>>>> an 'Update' on your design and will give more useful error messages.
>>>>>>>
>>>>>>> Regards
>>>>>>> Andrew
>>>>>>>
>>>>>>> On Thu, Jan 18, 2018 at 7:28 AM, Bela Dixit <dixitb...@gmail.com>
>>>>>>> wrote:
>>>>>>>
>>>>>>>> Hi CASPERites,
>>>>>>>>
>>>>>>>> I am working on 5Gsps and ROACH2 boards.
>>>>>>>> While compiling four element 300MHz bandwidth correlator design, I am 
>>>>>>>> facing some error.
>>>>>>>> Kindly help me to sort out that error.
>>>>>>>> Please find the attached snapshot of error.
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> Thanks & Regards,
>>>>>>>>
>>>>>>>> Bela Dixit
>>>>>>>>
>>>>>>>> --
>>>>>>>> You received this message because you are subscribed to the Google
>>>>>>>> Groups "casper@lists.berkeley.edu" group.
>>>>>>>> To unsubscribe from this group and stop receiving emails from it,
>>>>>>>> send an email to casper+unsubscr...@lists.berkeley.edu.
>>>>>>>> To post to this group, send email to casper@lists.berkeley.edu.
>>>>>>>>
>>>>>>>
>>>>>>> --
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>>>>>>> Groups "casper@lists.berkeley.edu" group.
>>>>>>> To unsubscribe from this group and stop receiving emails from it,
>>>>>>> send an email to caspe

Re: [casper] ROACH2 4-element correlator compilation error

[James Smith]

So updating the diagram at the moment produces no error, and you can see
the datatypes on the wires?


On Tue, Jan 30, 2018 at 9:49 AM, Bela Dixit <dixitb...@gmail.com> wrote:

> hie James,
>   I was getting some errors related to block, I corrected that error.
> After that it was proceeding but while synthesizing it stuck.
>
>
> Thanks & Regards,
> Bela
>
> Bela Dixit
> Electronics and Telecommunication engg(digital system)
>
>
> On Tue, Jan 30, 2018 at 1:07 PM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Bela,
>>
>> That is a bit long - what happens if you just do Ctrl+D? Does it return
>> any messages?
>>
>> I also find that on Simulink if you select *Display -> Signals & Ports
>> -> Port Data Types *it produces a more useful result.
>>
>> Regards,
>> James
>>
>>
>> On Tue, Jan 30, 2018 at 9:33 AM, Bela Dixit <dixitb...@gmail.com> wrote:
>>
>>> Hie James,
>>>
>>> I have waited around 7 to 9 hours, still I am getting same warnings.
>>>
>>> Thanks & Regards,
>>> Bela
>>>
>>>
>>> On Tue, Jan 30, 2018 at 12:22 PM, James Smith <jsm...@ska.ac.za> wrote:
>>>
>>>> Hello Bela,
>>>>
>>>> That looks fine - there are normally lots of warnings. You just need to
>>>> wait, these compiles can take several hours sometimes depending on their
>>>> complexity. Average for mine have been 1.5-2 hours.
>>>>
>>>> Regards,
>>>> James
>>>>
>>>>
>>>> On Tue, Jan 30, 2018 at 8:48 AM, Bela Dixit <dixitb...@gmail.com>
>>>> wrote:
>>>>
>>>>> Thanks Andrew and James for suggestion.
>>>>> I had  updated the casper block by ctrl-D. Compilation proceed but
>>>>> still there is some problem in synthesis part.
>>>>> Kindly help me to sort out this problem.
>>>>> Please find the attached snapshot of command window.
>>>>> Thanks & Regards,
>>>>> Bela
>>>>>
>>>>>>
>>>>>>> On Thu, Jan 18, 2018 at 12:34 PM, James Smith <jsm...@ska.ac.za>
>>>>>>> wrote:
>>>>>>>
>>>>>>>> Hello Bela,
>>>>>>>>
>>>>>>>> I second Andrew's suggestion, but note also that "Error due to
>>>>>>>> multiple causes" can often mean that somewhere in the design there's a 
>>>>>>>> name
>>>>>>>> that Matlab doesn't like. Avoid using any capital letters or spaces in
>>>>>>>> block names, and avoid using names that are too long - if the full
>>>>>>>> file-path of the design contains capital letters, spaces or too many
>>>>>>>> characters (I think 64 is the limit?) then it can fail.
>>>>>>>>
>>>>>>>> Other Casperites can possibly correct me if I'm wrong on this but
>>>>>>>> this is the convention that I tend to follow.
>>>>>>>>
>>>>>>>> Regards,
>>>>>>>> James
>>>>>>>>
>>>>>>>>
>>>>>>>> On Thu, Jan 18, 2018 at 8:23 AM, Andrew Martens <and...@ska.ac.za>
>>>>>>>> wrote:
>>>>>>>>
>>>>>>>>> Hi Bela
>>>>>>>>>
>>>>>>>>> Please open you design in Matlab/Simulink and then Press 'Ctrl-D'
>>>>>>>>> (hold the Ctrl key down and hit the D key at the same time). This 
>>>>>>>>> will do
>>>>>>>>> an 'Update' on your design and will give more useful error messages.
>>>>>>>>>
>>>>>>>>> Regards
>>>>>>>>> Andrew
>>>>>>>>>
>>>>>>>>> On Thu, Jan 18, 2018 at 7:28 AM, Bela Dixit <dixitb...@gmail.com>
>>>>>>>>> wrote:
>>>>>>>>>
>>>>>>>>>> Hi CASPERites,
>>>>>>>>>>
>>>>>>>>>> I am working on 5Gsps and ROACH2 boards.
>>>>>>>>>> While compiling four element 300MHz bandwidth correlator design, I 
>>>>>>>>>> am facing some error.
>>>>>>>>>> Kindly help me

Re: [casper] Red Hat Enterprise Linux--is it needed?

[James Smith]

Hello Jonathan,

For what it's worth, I used to run CentOS - I forget which version now. It
worked just fine, possibly a little bit better than Ubuntu subsequently
works, but that was subjective and I don't have any hard facts to back that
up.

But when I needed to change computers, and start from scratch again, I
decided just to go with what everyone else was using.

RHEL-based distros might work better than Ubuntu, but Ubuntu seems to work
just fine. And since most everyone uses it, it's easier to debug.

Regards,
James


On Thu, Aug 2, 2018 at 5:58 PM, Jonathan Weintroub <
jweintr...@cfa.harvard.edu> wrote:

> Dear Heystek, Adam, and James,
>
> Thanks very much for the feedback.
>
> It would seem I am correctly reading the zeitgeist, Ubuntu does seem to be
> strongly favored, and, indeed, now seems to be the only recommended Linux
> given by CASPER per the draft tools page set up by Brian and Jack.
>
> So I think I am well justified in letting my RHEL support lapse, and move
> forward with the CASPER recommended Linux.
>
> My pointed nature requires me to state that it is still true that Ubuntu
> is not the primary recommendation Xilinx makes, certainly not for ISE
> 14.7.  The tool flow leaders of CASPER are experts, so I am not going to
> worry about this, still, I recall responses on the mailing list mildly
> scolding various people seeing bugs for not strictly adhering to Xilinx
> recommendations.  Anyhow, there it is.
>
> Thanks very much for the responses to this, and for the hard work, at the
> current workshop/busy weeks, to make new and up to date tool flow
> documentation.
>
> Best wishes,
>
> Jonathan Weintroub
>
>
>
> > On Aug 1, 2018, at 3:50 AM, Heystek Grobler 
> wrote:
> >
> > Hey Jonathan
> >
> > I am running two setups.
> >
> > The first one is Ubuntu 14.04 LTS with Xilinx ISE 14.7 and Matlab 2012b
> > and it is running well.
> >
> > The second setup is Debian 8.9(Debian Jessie) with Xilinx ISE 14.7 and
> > Matlab 2012b. It took a while for matlab to work properly on Debian.
> There
> > was a few conflicts between Debians AWK and Matlabs AWK. After sorting
> out
> > the AWK issue, the system run perfectly.
> >
> > Have a great day
> >
> > Heystek
> >
> >
> >
> >
> >> Hi Jonathan and others,
> >>
> >> Check out our new documentation toolflow link hosted in ReadtheDocs
> thanks
> >> to Brian Bradford and Jack Hickish - we are currently using this for the
> >> hardware porting workshop running this week. Great job guys! :).
> >>
> >> https://casper-toolflow.readthedocs.io/en/latest/index.html
> >>
> >> https://casper-toolflow.readthedocs.io/
> >>
> >> All the documentation concerning mlib_devel, tutorials and very soon
> >> casperfpga will be hosted here. The hardware is still in the gthub wiki.
> >> Check out our new website thanks to Jack:
> >>
> >> http://casper-dsp.org
> >>
> >> The old Berkeley wiki will still stay active for now.
> >>
> >>
> >> Kind regards,
> >>
> >> Adam Isaacson
> >> South African Radio Astronomy Observatory (SARAO)
> >> Hardware Manager
> >> Cell: (+27) 825639602
> >> Tel:  (+27) 215067300
> >> email: aisaac...@ska.ac.za
> >>
> >>
> >> On Tue, Jul 31, 2018 at 10:29 PM, Jonathan Weintroub <
> >> jweintr...@cfa.harvard.edu> wrote:
> >>
> >>> Folks,
> >>>
> >>> Forgive me for raising an old chestnut of a question, because things
> >>> seem
> >>> to have evolved.
> >>>
> >>> A long time ago, when we first migrated from Windows to Linux tool
> >>> flows,
> >>> back in the ISE/EDK/ROACH days, I recall learning that RHEL (6 at the
> >>> time,
> >>> I think) was essential, because Xilinx ruled that that was the only
> >>> compatible Linux variant.
> >>>
> >>> My subjective observations lead me to think that many people use
> Ubuntu,
> >>> and other Linux's, for example CENTOS, for CASPER design.
> >>>
> >>> I can still find some references that RHEL is the only OS for ISE-based
> >>> design.
> >>>
> >>> But, for example, here:
> >>>
> >>> https://www.xilinx.com/support/documentation/sw_manuals/xili
> >>> nx2018_2/ug973-vivado-release-notes-install-license.pdf
> >>>
> >>> it would seem Ubuntu is officially blessed for Vivado—see page 11.
> >>> Mind
> >>> you, if you scroll down to page 13, it would appear Xilinx doesn’t
> >>> think
> >>> Ubuntu works with Matlab/Simulink as a third party tool.
> >>>
> >>> Once again, the RHEL reseller is bugging me to renew my support—I
> >>> really
> >>> hate maintaining licenses, by the way. I thought I’d poll collective
> >>> wisdom
> >>> before I respond, maybe we can just ditch RHEL?
> >>>
> >>> From a practical perspective is Ubuntu working for people?
> >
> > --
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Re: [casper] Re: Spectrum shifted (Beamformer)

[James Smith]

Hello Rolando,

You expect to see a DC bin, i.e. a large value in channel 0, and I have
often seen a large-ish value in bin 1 as well. After that it will drop off.

If you're seeing a peak in something other than 0, there may be something
wrong. Those spikes at the high end of your spectrum look a little bit
fishy to me, though (can someone correct me?) this may depend on which
Nyquist zone you're sampling in.

Regards,
James


On Mon, Mar 12, 2018 at 5:00 PM, Rolando Paz  wrote:

> Hi.
>
> With the help of Indrajit, I managed to understand where to place some
> delays to adjust the spectra position...
>
> My test tone is 60MHz.
>
> I still see a signal to the left of the graph, does that mean that I still
> have to adjust the simulink design more?
>
> Regards
>
> Rolando
>
> 2018-03-10 19:51 GMT-06:00 Jack Hickish :
>
>> Hi Rolando,
>>
>> My first suggestion would just be to carefully look at your design and
>> follow the sync and data paths looking for issues.  Otherwise you can
>> simulate a signal in a particular FFT bin and check with a scope to make
>> sure it stays where it should relative to the sync pulse. For these kinds
>> of simulations, sometimes I just make the simulation input a constant
>> (i.e., a DC signal). This should result in a spike in FFT channel 0, which
>> occurs the clock after the sync pulse.
>>
>> Cheers
>> Jack
>>
>> On Sat, 10 Mar 2018 at 17:42 Rolando Paz  wrote:
>>
>>> Very interesting. Thanks Jack.
>>>
>>> Is there any way to find the place and value of the latency that I must
>>> remove or add, to the synchronization pulse inside my design?
>>>
>>> Regards
>>>
>>> Rolando
>>>
>>>
>>> 2018-03-10 18:47 GMT-06:00 Jack Hickish :
>>>
 Hi Rolando,

 This sort of channel number offset issue usually indicates a
 misalignment between the sync pulse in the design and data where your data
 goes through an operation that has some latency, and this latency isn't
 compensated for in the sync signal.
 One clue is that there is usually a spike in FFT bin 0 (i.e., the DC
 bin). In your plots this spike appears at the end of the spectrum for the
 per-antenna plots, and seemingly at bin ~2 in the beamformer plot.

 You should fix this in your simulink design, by adding or removing
 latency in the sync or data signals to keep them aligned. You could just
 shift your spectra in software, but that's a bit of a hack -- really you
 should just fix the hardware bug.

 Cheers
 Jack


 On Sat, 10 Mar 2018 at 15:54 Rolando Paz  wrote:

> Hi Jack
>
> I did some tests with my beamformer design (4 inputs).
>
> Currently I only have a 70MHz test tone at the A and B inputs. I do
> not have anything connected at C and D inputs .
>
> The tone at A and B inputs is slightly offset to the left with respect
> to the 70MHz signal.
>
> In the C and D inputs appear some signals that I do not know why they
> appear.
>
> Do you know why the spectrum can move?
>
> In the case of the beamformer signal, it appears displaced to the
> right of the 70MHz tone. Why does this happen?
>
> Is this corrected in the spectrometer design (matlab design) or is it
> corrected with python?
>
> Best Regards
>
> Rolando Paz
>

>>>
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Re: [casper] Quick prototype platform

[James Smith]

Hello Karl,

How many antenna elements do you have? We've had simple two-antenna
interferometers with both F and X on a single ROACH-1. I'm still using one.
There's a tutorial on the wiki doing exactly this.

That being said, ROACH-1's biggest hassle is using CX4 Ethernet plugs,
which are finicky and it's hard to get the corresponding computer hardware
for capturing the output. ROACH2 has more up-to-date stuff.

So it kind of depends as you said on the specific requirements that you
have. The CASPER platforms are quite flexible though, so you'd be surprised
just how much they can accomplish.

Regards,
James


On 15 Mar 2018 23:59, "Karl Warnick"  wrote:

Hi all,

I have a non-astronomical comms antenna array project that does not have
detailed specs for bandwidth and number of antenna elements. I need to
build a programmable platform that I can use for multichannel sampling and
real time DSP.

Our group has considerable experience with ROACH based systems over the
years and hybrid FPGA - GPU architectures, but the students with much of
the expertise have graduated and moved on, as students tend to do. We have
an x64 board and ROACH that on paper could do the job, but the hardware
seems old enough now that I wonder if it might be wise to move to a new
platform for my new project. We also like the easier programmability of
GPUs for matrix based array signal processing algorithms. We also have a
system with digitizers, polyphase filterbanks running on ROACH boards,
ethernet switch, and HPCs with GPUs, but that system is in operation at GBO
and is probably overkill for the current project.

This leads to my question. To realize a system with 16 analog channels and
analog bandwidth ranging between a few MHz up to 100 MHz (I realize that
this is a rather ill defined range, but I feel fortunate to have the
flexibility), that can do digitization, filterbank to separate into
frequency channels, and enough processor power for real time XB
(correlator/beamformer) type signal processing, with current CASPER
hardware, what would be the ideal, recommended hardware setup?

The relatively modest bandwidth requirement may also point to a commercial
FPGA/ARM core board with an ADC expansion board, and I'm pursuing that path
as well. From another project, I have an expansion board of our own design
with eight ADC channels that plugs into a microZED board, which actually
comes somewhat close to meeting the current requirements. Expanding the ADC
board and moving to a bigger commercial digital board is an option.

Thanks to all for any feedback!

Best,
Karl

-- 
Karl F. Warnick
Department of Electrical and Computer Engineering
Brigham Young University
459 Clyde Building
Provo, UT 84602
(801) 422-1732





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Re: [casper] off-line data processing with ROACH2

[James Smith]

Hello Bela,

Depending on how you're reading your binary file on the computer, the
easiest thing to do would probably be to use the ROACH2's 10 GbE networking.

You can then use e.g. a python socket program to send the data to the
ROACH2 in chunks, receive and process it on the FPGA and then use the 10
GbE core again to send it back to the computer, or to a different computer
if the datarate is high enough to warrant sending and receiving on
different machines.

Specific details would depend more on exactly what you want to do.

Regards,
James


On Thu, Apr 19, 2018 at 8:06 AM, Bela Dixit  wrote:

> Hi CASPERites,
> I am having digitized data which is available in binary file. This
> data I want to push on to the ROACH2 board as an input for further
> processing.
>  Kindly suggest me what are the options that can possible in this
> regards.
>
>
>
>
>
> Thanks & Regards,
> Bela
>
>
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Re: [casper] off-line data processing with ROACH2

[James Smith]

Have a look at Tutorial 2:
https://casper.berkeley.edu/wiki/Tutorial_10GbE_ROACH2

This is a very simple example of using the networking obviously, but the
main ideas will hold.

Just be careful of endian-ness, make sure that you're interpreting packets
correctly, because computers tend to be little-endian while the FPGA will
(likely) use by default more intuitive big-endian logic, unless you design
otherwise.

On Thu, Apr 19, 2018 at 10:59 AM, Bela Dixit <dixitb...@gmail.com> wrote:

> Thanks James, I will look in to it.
>
> Thanks & Regards,
> Bela
>
>
> Bela Dixit
> Electronics and Telecommunication engg(digital system)
>
>
> On Thu, Apr 19, 2018 at 11:42 AM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Bela,
>>
>> Depending on how you're reading your binary file on the computer, the
>> easiest thing to do would probably be to use the ROACH2's 10 GbE networking.
>>
>> You can then use e.g. a python socket program to send the data to the
>> ROACH2 in chunks, receive and process it on the FPGA and then use the 10
>> GbE core again to send it back to the computer, or to a different computer
>> if the datarate is high enough to warrant sending and receiving on
>> different machines.
>>
>> Specific details would depend more on exactly what you want to do.
>>
>> Regards,
>> James
>>
>>
>> On Thu, Apr 19, 2018 at 8:06 AM, Bela Dixit <dixitb...@gmail.com> wrote:
>>
>>> Hi CASPERites,
>>> I am having digitized data which is available in binary file. This
>>> data I want to push on to the ROACH2 board as an input for further
>>> processing.
>>>  Kindly suggest me what are the options that can possible in this
>>> regards.
>>>
>>>
>>>
>>>
>>>
>>> Thanks & Regards,
>>> Bela
>>>
>>>
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Re: [casper] SNAP Tutorial 3

[James Smith]

Hello David,

A little late to the party but I thought I'd throw in 2c from our
perspective.

The other thing we usually try to do with ADCs (this was an issue on the
ROACH1s) is to put in a bit of white noise with whatever test signal we
were using (sine wave usually). When you get actual sky, then you will have
to fiddle with signal levels again until you get an optimum, because the
sky signal will invariably be different from your lab test signals.

Regards,
James


On Fri, Jan 18, 2019 at 7:37 PM David Marsh  wrote:

> Thank you Dan!
>
> Using the adc snapshot, I saw that with no input the adc was toggling
> between -1 and 0. This was the cause of the
> spikes in the spectrum. I also looked at the adc samples with a sine wave
> as the input and everything looked as
> expected as you described.
>
> Thanks,
> David
>
>
>
> On Tue, Jan 15, 2019 at 11:07 AM Dan Werthimer 
> wrote:
>
>>
>> hi david,
>>
>> when you have no signal going into an adc, it will typically chatter
>> between two values, around -1, 0 and +1,
>> and you'll see a lot of RFI and interleave spurs, so the spectrum you
>> sent around doesn't surprise me,
>>
>> but if you put in a sine wave that is much larger than the ADC chatter,
>> say Vpp ranging from -100 to +100 (out of -128 to +127 for an 8 bit ADC),
>> then the power spectrum spurs should be very small compared to the sine
>> wave power
>> (about a factor of 10,000 in power (100 in voltage)).
>>
>> can you use the adcsnap shot to look at the samples coming from your adc,
>> and see what the relative levels are of the sine wave to the noise?
>> does the power spectrum agree with what you see in the snapshot?
>>
>> best wishes,
>>
>> dan
>>
>>
>>
>>
>> On Tue, Jan 15, 2019 at 9:59 AM David Marsh 
>> wrote:
>>
>>> Hi all,
>>>
>>> Sorry if this has already been explained/solved.
>>> I programmed Tutorial 3 onto a SNAP board and noticed some unexpected
>>> spikes in the spectrum.  I have set up the hardware as explained in the
>>> python script with a 10 MHz, 8dBm  reference going into the SYNTH_OSC SMA
>>> (3rd SMA from the left).
>>>
>>> The attached figure shows the spectrum with no input going into the SNAP
>>> board. There are large spikes in the spectrum every 50 MHz with the largest
>>> at 200 MHz.
>>>
>>> When I add a signal to the SNAP board, I can see it in the spectrometer
>>> at the correct frequency
>>> but the other spikes are still present.
>>>
>>> Do you know what is causing these spikes and how they can be removed?
>>> Any help would be greatly appreciated.
>>>
>>> Thanks,
>>> David
>>>
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Re: [casper] Timestamp in ROACH2 and PTP

[James Smith]

Hello Franco,

Jack's email explained more explicitly what I tried to convey. Did it make
it clear?

Regards,
James


On Sat, Mar 9, 2019 at 12:44 AM Jack Hickish  wrote:

> Hi Franco,
>
> The general principle is generally this --
>
> We assume that the system has
> 1. A CPU-based control computer (a laptop / desktop / posh server /
> whatever) which has a standard NTP client running. NTP allows this computer
> to know the time good to some number of milliseconds.
> 2. FPGAs in the system have an GPS pulse-per-second (PPS) input, which
> sends a pulse on each UTC second, good to 10s of nanoseconds.
> 3. Some firmware on your FPGAs which allows an arm signal to be generated
> by software, causing some internal counter to be generated from the next
> PPS pulse edge.
>
> You then do the following:
>
> On your control computer you sleep until a second boundary passes. Then
> you issue an arm of the FPGA boards. You don't know exactly when this arm
> arrives -- NTP isn't that accurate, and the latency of issuing an FPGA
> write is unknown -- this is why you can't use this signal alone for
> defining timing. But... you *do* know the next second boundary that will
> follow the arm. On this second, a PPS (which is good to <100us) triggers
> the reset of your FPGA's counter logic. You can then use this counter to
> indicate time in FPGA cycles since reset. Since you know the reset time, if
> you use this counter to stamp data packets you can figure out the time
> associated with the data in these packets.
>
> You can probably do something in python like:
> from time import *
> sleep(1 - (time() % 1)) # Sleep until the next second boundary
> sleep(0.1) # sleep until 100ms past this second
> my_fpga.arm() # Arm the sync generator logic
> arm_time = int(time()) + 1 # The next second tick will pass at this time
> and reset your boards
> # write the arm_time somewhere, so that when you get a packet timestamped
> with some counter, you can do
> # time_of_this_packet = arm_time + (counter_value /
> counter_ticks_per_second)
>
> Maybe that was helpful. Maybe it will add to your confusion. Probably the
> above pseudo code doesn't work in real life :)
>
> Cheers
> Jack
>
> On Fri, 8 Mar 2019 at 10:50, Franco  wrote:
>
>> Hi James,
>>
>> Thank you for your answer. Yes, I use and ADC for data acquisition. I
>> understand the general idea of your system. What I don't understand is
>> where you get the start time of the ROACH2. Is generated by the TRF? Is
>> there a different system that initialize all the synchronized devices and
>> that record the start time? Sorry if it is basic question.
>>
>> Thanks,
>>
>> Franco
>>
>> On Thu, Mar 7, 2019 at 3:52 AM James Smith  wrote:
>>
>>> Hello Franco,
>>>
>>> As I understand it, PTP wasn't terribly useful in our application
>>> (though I wasn't involved with this directly). You can probably sync the
>>> little Linux instance that runs on the ROACH2, but getting the time
>>> information onto your FPGA may prove somewhat tricky.
>>>
>>> Are you using an ADC card in the ROACH2? Or is the data digitised
>>> separately?
>>>
>>> What we've done with ROACH and ROACH2 designs in the past is more or
>>> less this:
>>>
>>>- FPGA's clock comes from a timing & frequency reference (TFR).
>>>- ROACH2 gets a 1PPS input from the same TFR.
>>>- In the FPGA logic there's a counter which is reset as part of the
>>>initialisation, and some logic that starts the counter going after a set
>>>number of 1PPS pulses (two to three, I forget exactly now).
>>>- The output of this counter is pipelined along with the data and
>>>then sent out as part of the SPEAD data on the 10GbE network.
>>>
>>> The idea here being that you know with a fairly high degree of precision
>>> which pulse your ROACH was initialised on. The counter that comes through
>>> on the SPEAD packet counts in FPGA clock cycles (or multiples thereof,
>>> perhaps you might want to count in spectra), and then you can use the start
>>> time to calculate the timestamp of each packet (Unix time, MJD, whichever
>>> your preferred reference is).
>>>
>>> Hope that helps.
>>>
>>> Regards,
>>> James
>>>
>>>
>>> On Wed, Mar 6, 2019 at 7:41 PM Franco  wrote:
>>>
>>>> Dear Casperiites,
>>>>
>>>> I was given the task of timestamping ROACH2 spectral data in a
>>>> telescope that uses PTP (precision time protocol) as a synchronizat

Re: [casper] Timestamp in ROACH2 and PTP

[James Smith]

Hello Franco,

As I understand it, PTP wasn't terribly useful in our application (though I
wasn't involved with this directly). You can probably sync the little Linux
instance that runs on the ROACH2, but getting the time information onto
your FPGA may prove somewhat tricky.

Are you using an ADC card in the ROACH2? Or is the data digitised
separately?

What we've done with ROACH and ROACH2 designs in the past is more or less
this:

   - FPGA's clock comes from a timing & frequency reference (TFR).
   - ROACH2 gets a 1PPS input from the same TFR.
   - In the FPGA logic there's a counter which is reset as part of the
   initialisation, and some logic that starts the counter going after a set
   number of 1PPS pulses (two to three, I forget exactly now).
   - The output of this counter is pipelined along with the data and then
   sent out as part of the SPEAD data on the 10GbE network.

The idea here being that you know with a fairly high degree of precision
which pulse your ROACH was initialised on. The counter that comes through
on the SPEAD packet counts in FPGA clock cycles (or multiples thereof,
perhaps you might want to count in spectra), and then you can use the start
time to calculate the timestamp of each packet (Unix time, MJD, whichever
your preferred reference is).

Hope that helps.

Regards,
James


On Wed, Mar 6, 2019 at 7:41 PM Franco  wrote:

> Dear Casperiites,
>
> I was given the task of timestamping ROACH2 spectral data in a telescope
> that uses PTP (precision time protocol) as a synchronization protocol. I
> understand that ROACH's BORPH come preloaded with NTP (network time
> protocol) libraries/daemos, but PTP is preferred because is already in use
> in the telescope, and it achieves greater time precision.
>
> Does somebody know if it is feasible to compile/install PTP libraries in
> BORPH?
>
> Alternatively, we have though of sending the ROACH the current time
> through a GPIO pin using IRIG-B timecode standard. Has anybody done
> something similar in the past?
>
> Thanks,
>
> Franco
>
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Re: [casper] ROACH 1 boot issue

[James Smith]

Hello Indrajit,

Check the settings on your serial connection - did you turn off Flow
Control?

Regards,
James


On Wed, Feb 13, 2019 at 1:47 PM indrajit  wrote:

> Hello James,
>
> I am also doing the same. I am able to see the booting sequences via the
> serial terminal counting down from 10 and I am trying to interrupt but the
> keystrokes are not interrupting the boot menu.
>
> Even I changed the SD card which is logically nothing to do with the
> booting sequence.
>
> Thanks and regards
>
> Indrajit
>
>
>
> On Wednesday 13 February 2019 05:07 PM, James Smith wrote:
>
> Hello Indrajit,
>
> Why were you not able to interrupt the process? Connect to the ROACH via
> the serial port then reset it - you should be able then to see the place to
> interrupt and set netboot (or whatever else you need) quite easily.
>
> Regards,
> James
>
>
> On Wed, Feb 13, 2019 at 1:31 PM indrajit  wrote:
>
>> Hello all,
>>
>> A new ROACH1 while taking measurements stopped responding. Then via
>> serial communication, found that it got booted using the flash.
>> Restarted and trying to interrupt using the serial terminal and boot via
>> MMC-BOOT.  I couldn't interrupt using the keyboard. I inserted another
>> working SD card and tried the same. Failed to boot via the memory card.
>>
>> Thanks and regards
>>
>> indrajit
>>
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Re: [casper] ROACH 1 boot issue

[James Smith]

Hello Indrajit,

Why were you not able to interrupt the process? Connect to the ROACH via
the serial port then reset it - you should be able then to see the place to
interrupt and set netboot (or whatever else you need) quite easily.

Regards,
James


On Wed, Feb 13, 2019 at 1:31 PM indrajit  wrote:

> Hello all,
>
> A new ROACH1 while taking measurements stopped responding. Then via
> serial communication, found that it got booted using the flash.
> Restarted and trying to interrupt using the serial terminal and boot via
> MMC-BOOT.  I couldn't interrupt using the keyboard. I inserted another
> working SD card and tried the same. Failed to boot via the memory card.
>
> Thanks and regards
>
> indrajit
>
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Re: [casper] Bringing up a new ROACH2

[James Smith]

Hello Dale,

Yes, the instructions you linked should work.

Regards,
James


On Mon, 4 Feb 2019, 23:17 Gary, Dale E.  Hi James,
>
> Thanks for the reply.  The ROACHes at the observatory are netbooted, and I
> do not have an SD card for booting, so would have to create one.  I suppose
> I could clone the uboot system from the observatory to campus and try to
> set up tftp etc. -- that is pretty much what I intended to do using the
> instructions I had linked to, but my question is whether there are new
> instructions somewhere that I should use.  It seems the answer is no, so I
> will proceed with the old instructions.
>
> Thanks,
> Dale
>
> On Mon, Feb 4, 2019 at 5:37 AM James Smith  wrote:
>
>> Hello Dale,
>>
>> Do you have any existing, functioning ROACH2 boards? Are they booting
>> from an SD card or from network? If it's a network card then it's a simple
>> matter to copy the one to the other, if from network then the most you may
>> need to do is update your dnsmasq.conf to assign an IP address to the new
>> ROACH2 (its MAC address should be the same as existing ones but the last
>> few digits reflect the serial number of the ROACH2).
>>
>> The instructions linked look as though they should work but AFAIK it's
>> been a while since anyone put in a new ROACH2 anywhere, so YMMV. At SKA,
>> we've mostly moved on to SKARAB. However, there's quite a bit of
>> organisational memory, so if you battle, just shout.
>>
>> Regards,
>> James
>>
>>
>> On Sun, Feb 3, 2019 at 8:51 PM Gary, Dale E. 
>> wrote:
>>
>>> Hi All,
>>>
>>> We need to bring up a new ROACH2 board from scratch for the purpose of
>>> introducing students to the tools based on the Casper 2018 tutorials.
>>> Although I did all of this 3-4 years ago at our observatory, I need to
>>> refresh my memory, and I would like to take advantage of any new
>>> developments.  Are the instructions (ca 2015) still correct as listed
>>> here:
>>> https://casper.ssl.berkeley.edu/wiki/ROACH-2_Revision_2#Updating_tcpborphserver_3_etc.
>>> ?  If there are updated instructions, please let me know.
>>>
>>> Thanks,
>>> Dale Gary
>>>
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Re: [casper] Bringing up a new ROACH2

[James Smith]

Hello Dale,

Do you have any existing, functioning ROACH2 boards? Are they booting from
an SD card or from network? If it's a network card then it's a simple
matter to copy the one to the other, if from network then the most you may
need to do is update your dnsmasq.conf to assign an IP address to the new
ROACH2 (its MAC address should be the same as existing ones but the last
few digits reflect the serial number of the ROACH2).

The instructions linked look as though they should work but AFAIK it's been
a while since anyone put in a new ROACH2 anywhere, so YMMV. At SKA, we've
mostly moved on to SKARAB. However, there's quite a bit of organisational
memory, so if you battle, just shout.

Regards,
James


On Sun, Feb 3, 2019 at 8:51 PM Gary, Dale E.  wrote:

> Hi All,
>
> We need to bring up a new ROACH2 board from scratch for the purpose of
> introducing students to the tools based on the Casper 2018 tutorials.
> Although I did all of this 3-4 years ago at our observatory, I need to
> refresh my memory, and I would like to take advantage of any new
> developments.  Are the instructions (ca 2015) still correct as listed
> here:
> https://casper.ssl.berkeley.edu/wiki/ROACH-2_Revision_2#Updating_tcpborphserver_3_etc.
> ?  If there are updated instructions, please let me know.
>
> Thanks,
> Dale Gary
>
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Re: [casper] Re: casperfpga package issue.

[James Smith]

We use this tag in our repo for supporting ROACH1:
https://github.com/ska-sa/casperfpga/releases/tag/AVN_legacy
Note that you can't use upload_to_ram_and_program. It's a three-step
process.

fpga.system_info['program_filename'] = '%s.bof' % gateware #bof needs to be
on the roachfs for this to work
fpga.program()
fpga.get_system_information('%s.fpg' % gateware) #fpg file needs to be in
current working directory

Give that a spin.



On Fri, May 10, 2019 at 9:06 AM Adam Isaacson  wrote:

> Hi Indrajit,
>
> This how to is fairly old now - many changes have been made since then and
> we have and are moving all CASPER documentation to ReadtheDocs or at least
> readme.md files in github, which can be easily added to ReadtheDocs if
> necessary. The casperfpga repo still needs to be properly documented and
> this is due to happen in July after the Hardware Porting Workshop. If ROACH
> support is lacking and it becomes a requirement, then we can look at this
> as a task to add during that week. Jack, would be able to give you better
> feedback here.
>
> I am assuming you are using the casper-astro repo? I know Jack made a
> recent change to get casperfpga working with ROACH2 i.e. the
> upload_to_ram_and_program() can now configure the FPGA on ROACH2. I am not
> sure about ROACH1 - a bit before my time here. Others may know more.
>
> casper-astro casperfpga repo:
> https://github.com/casper-astro/casperfpga/commits/master
>
> In this repo there is a readme.md file, which explains how to install
> casperfpga and also references commit hashes that work with ROACH/ROACH2. I
> haven't tried them so I am not sure.
>
> I hope this helps.
>
> Kind regards,
>
> Adam Isaacson
> South African Radio Astronomy Observatory (SARAO)
> Hardware Manager
> Cell: (+27) 825639602
> Tel:  (+27) 215067300
> email: aisaac...@ska.ac.za
>
>
>
> On Fri, May 10, 2019 at 7:44 AM Indrajit Barve 
> wrote:
>
>> Dear Adam,
>>
>> I followed the steps which you have given in the bellow link to install
>> casperfpga package.
>>
>> https://www.mail-archive.com/casper@lists.berkeley.edu/msg06436.html
>>
>> https://docs.google.com/document/d/1mqDIwhHo3981_Rq9Ma6Dl8UnQUzPah6DKQ55fsaeI4c/edit
>> By following the steps via git . Hope it downloads the latest version of
>> katcp and casperfpga.
>>
>> I am using ROACH1 and I am trying to program the device and I am getting
>> the following errors.
>>
>> 
>>
>>
>> import time,struct,sys,logging,casperfpga
>> from struct import *
>> fpga = casperfpga.katcp_fpga.KatcpFpga('100.100.100.1',7147,10)
>> bitstream='spectrum_test14_2019_May_09_1616.bof'
>> fpga.system_info['program_filename'] = bitstream
>> fpga.program()
>> time.sleep(3)
>>
>> *'module' object has no attribute 'katcp_fpga' *
>>
>> I tried the other ways
>>
>> roach = casperfpga.CasperFpga('100.100.100.1')
>> roach.upload_to_ram_and_program('spectrum_test14_2019_May_09_1616.fpg')
>>
>>
>>
>>
>> ---
>> TypeError Traceback (most recent call
>> last)
>>  in ()
>> > 1
>> roach.upload_to_ram_and_program('spectrum_test14_2019_May_09_1616.fpg')
>>
>> /usr/local/lib/python2.7/dist-packages/casperfpga-3.2.dev644+devel.3377047-py2.7-linux-x86_64.egg/casperfpga/casperfpga.pyc
>> in upload_to_ram_and_program(self, filename, wait_complete, legacy_reg_map,
>> chunk_size, initialise_objects)
>> 278 filename = self.bitstream
>> 279 rv = self.transport.upload_to_ram_and_program(
>> --> 280 filename=filename, wait_complete=wait_complete,
>> chunk_size=chunk_size)
>> 281 if not wait_complete:
>> 282 return True
>>
>> TypeError: upload_to_ram_and_program() got an unexpected keyword argument
>> 'chunk_size'
>>
>> +
>>
>>
>>
>>
>>
>> Indrajit Barve
>> indra...@iiap.res.in
>> 080-22541492
>>
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Re: [casper] Re: How to upload and run two .bof files in ROACH2

[James Smith]

Zhang,

If your logic is small enough and both designs can fit onto the ROACH2, you
can combine them in Simulink and compile a new bof (or fpg) file and use
this instead.

Regards,
James


On Thu, Jul 11, 2019 at 2:16 PM Jack Hickish  wrote:

> Hi Zhang,
>
> Alas, that is impossible!
>
> Cheers
> Jack
>
> On Thu, 11 Jul 2019 at 12:19, zhang laiyu  wrote:
> >
> > Hi,Jack
> >
> >  I want to upload and run two .bof files in ROACH2  at the
> same time. If is possible,how to to do it ? Thank you.
> >
> >
> >
> >
> >
> >
> > Cheers!
> >
> > >
> > ZHANG Laiyu
> > Phone(China)   010-88236415
> > Cellphone(China)   13681385567
> > E-mail:zhan...@ihep.ac.cn
> > Address:   19B Yuquan Road,Shijingshan District,Beijing，China
> > Department:Center for Particle Astrophysics
> > Office:Astrophysics Building 205
> >
> > Institute of High Energy Physics, CAS
> > web: http://www.ihep.cas.cn
> >
> > >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
>
> --
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> .
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Re: [casper] python problem

[James Smith]

Also, I'm not sure whether I'm using a deprecated approach, but I do the
following:

fpga = casperfpga.katcp_fpga.KatcpFpga(,)



On Mon, Jul 29, 2019 at 11:01 PM Jack Hickish  wrote:

> Hi Gonzalo,
>
> You're not running your ipython shell within the casperfpga directory,
> are you? I know that can cause weird problems with the import.
>
> Cheers
> Jack
>
> On Mon, 29 Jul 2019 at 12:03, Gonzalo Burgos  wrote:
> >
> > Hello,
> > I tried to use your suggestions but now I can't connect to the roach.
> This a new error come up after the reinstall of the casperfpga v0.4.3 and I
> test the same with the v0.4.2 and v0.4.1 getting the same error.
> >
> > what I can do?
> >
> > In [2]: fpga = casperfpga.CasperFpga('roach020e18')
> >
> ---
> > AttributeErrorTraceback (most recent call
> last)
> >  in ()
> > > 1 fpga = casperfpga.CasperFpga('roach020e18')
> >
> > AttributeError: 'module' object has no attribute 'CasperFpga'
> >
> > regards
> >
> > El jue., 18 jul. 2019 a las 4:35, Amish Patel ()
> escribió:
> >>
> >> Hi Gonzalo,
> >>
> >> Also worth mentioning for completeness, please do remove any existing
> installation(s) of casperfpga on your machine/server via the command below.
> >> - sudo rm -r
> /usr/local/lib/python2.7/dist-packages/casperfpga-.egg
> >> - You should also check if there are any other items laying around in
> the /dist-packages/ folder from this casperfpga install
> >>
> >> Do let me/us know how it goes.
> >>
> >> Regards
> >>
> >> Amish Patel
> >> SARAO
> >>
> >>
> >> On Thu, 18 Jul 2019 at 08:52, James Smith  wrote:
> >>>
> >>> Hello Gonzalo,
> >>>
> >>> Your Casperfpga version seems to be a bit too recent - I stand under
> correction here but later versions might have broken backwards
> compatibility with ROACH2.
> >>>
> >>> Try checking out v0.4.3 or one of the other slightly older releases in
> your casperfpga repo and reinstalling:
> >>>
> >>> cd /path/to/casperfpga
> >>> git checkout v0.4.3
> >>> sudo python setup.py install
> >>>
> >>> Give that a whirl and let us know how you get on.
> >>>
> >>> Regards,
> >>> James
> >>>
> >>>
> >>> On Thu, Jul 18, 2019 at 12:04 AM Gonzalo Burgos 
> wrote:
> >>>>
> >>>> Hi everyone.
> >>>> I installed all toolflow for roach2
> >>>>
> >>>> -matlab2012b -
> >>>> -ISE, xilinx 14.7
> https://github.com/casper-astro/mlib_devel/wiki/How-to-install-Xilinx-ISE
> and  import the ip cores from 11 de xilinx version
> >>>> -Python libraries
> https://docs.google.com/document/d/1mqDIwhHo3981_Rq9Ma6Dl8UnQUzPah6DKQ55fsaeI4c/edit
> >>>> -Simulink libraries
> >>>>
> >>>> but when i try to upload .fpg file on roach, python shows me this
> error.
> >>>>
> >>>>
> >>>> In [3]: fpga.upload_to_ram_and_program('roach2_tut_intro.fpg')
> >>>>
> ---
> >>>> TypeError Traceback (most recent call
> last)
> >>>>  in ()
> >>>> > 1 fpga.upload_to_ram_and_program('roach2_tut_intro.fpg')
> >>>>
> >>>>
> /usr/local/lib/python2.7/dist-packages/casperfpga-3.2.dev629+master.19c93d9-py2.7-linux-x86_64.egg/casperfpga/casperfpga.pyc
> in upload_to_ram_and_program(self, filename, wait_complete, legacy_reg_map,
> chunk_size)
> >>>> 268 filename = self.bitstream
> >>>> 269 rv = self.transport.upload_to_ram_and_program(
> >>>> --> 270 filename=filename, wait_complete=wait_complete,
> chunk_size=chunk_size)
> >>>> 271 if not wait_complete:
> >>>> 272 return True
> >>>>
> >>>> TypeError: upload_to_ram_and_program() got an unexpected keyword
> argument 'chunk_size
> >>>>
> >>>> Thanks and cheers!
> >>>> --
> >>>>
> >>>> --
> >>>> You received this message because you are subscribed to the Google
> Groups "casper@lists.berkeley.edu" group.
> >>>> To unsubscrib

Re: [casper] python problem

[James Smith]

Hello Gonzalo,

Your Casperfpga version seems to be a bit too recent - I stand under
correction here but later versions might have broken backwards
compatibility with ROACH2.

Try checking out v0.4.3 or one of the other slightly older releases in your
casperfpga repo and reinstalling:

cd /path/to/casperfpga
git checkout v0.4.3
sudo python setup.py install

Give that a whirl and let us know how you get on.

Regards,
James


On Thu, Jul 18, 2019 at 12:04 AM Gonzalo Burgos  wrote:

> Hi everyone.
> I installed all toolflow for roach2
>
> -matlab2012b -
> -ISE, xilinx 14.7
> https://github.com/casper-astro/mlib_devel/wiki/How-to-install-Xilinx-ISE
> and  import the ip cores from 11 de xilinx version
> -Python libraries
> https://docs.google.com/document/d/1mqDIwhHo3981_Rq9Ma6Dl8UnQUzPah6DKQ55fsaeI4c/edit
>
> -Simulink libraries
>
> but when i try to upload .fpg file on roach, python shows me this error.
>
>
> In [3]: fpga.upload_to_ram_and_program('roach2_tut_intro.fpg')
> ---
> TypeError Traceback (most recent call last)
>  in ()
> > 1 fpga.upload_to_ram_and_program('roach2_tut_intro.fpg')
>
> /usr/local/lib/python2.7/dist-packages/casperfpga-3.2.dev629+master.19c93d9-py2.7-linux-x86_64.egg/casperfpga/casperfpga.pyc
> in upload_to_ram_and_program(self, filename, wait_complete, legacy_reg_map,
> chunk_size)
> 268 filename = self.bitstream
> 269 rv = self.transport.upload_to_ram_and_program(
> --> 270 filename=filename, wait_complete=wait_complete,
> chunk_size=chunk_size)
> 271 if not wait_complete:
> 272 return True
>
> TypeError: upload_to_ram_and_program() got an unexpected keyword argument
> 'chunk_size
>
> Thanks and cheers!
> --
>
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> .
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Re: [casper] Problems booting ROACH 1

[James Smith]

Hello Sebastian,

Here's a snippet from one of our internal guides on how to set a ROACH1 up.
Check that you've got the baud rate set correctly, if you get absolutely
nothing on the serial port. You do need to configure the ROACH to boot from
the NFS.

If you get nothing on the serial port though, that could indicate that the
ROACH is faulty?


   -

   Connect the serial port of the ROACH to the Windows PC using the
   USB-to-serial converter and establish a serial connection using Putty or
   similar software (baud rate 115200). Remember to check the COM port using
   the technique described above.
   -

   Power up (or reboot) the ROACH, keeping an eye on the terminal
   -

   Press a key on to get into the UBOOT configuration. Typing help lists
   the possible commands.

Input: printenv bootcmd

Output: bootcmd=run mmcboot

   -

   Change this to run netboot

Input: setenv bootcmd run netboot

Input: saveenv

   -

   Verify that the ROACH is booting from NFS rebooting on the front panel,
   or by typing boot in U-BOOT.



   -

   Keep the serial connection open until booting is finished and you get a
   login prompt. Login to the ROACH. The default login is root with no
   password. Check that the filesystem has correctly loaded from the NFS uboot
   partition.


Regards,
James


On Thu, Nov 7, 2019 at 12:37 AM Sebastian Hincapié Tarquino <
sebastian.hincapi...@gmail.com> wrote:

> Hello all
>
> I am currently trying to work with a ROACH 1. I'm going through the ROACH
> NFS Guide, but my ROACH isn't booting, and minicom shows nothing, also it
> won't let me execute any direct instruction o transfer files.
> I've tried booting from SD card using either
> filesystem_etch_2009-11-30.tar.bz
> 
> and filesystem_etch_nfs.tar.gz
> 
> from this link:
> https://casper.ssl.berkeley.edu/svn/trunk/roach/sw/binaries/filesystem/ ,
> but neither worked.
>
> Do you have any idea what else could I do?
>
> Thanks in advance
>
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Re: [casper] Re: Help with 10GBE network

[James Smith]

Thanks for a well-thought-out response, Jack. Just to add my 2c -

Depending on your install, there's sometimes a firewall which blocks
high-range UDP ports which we typically use by default. So if you can see
packets coming in with Wireshark / tcpdump, but for some reason your Python
sockets are hanging around with nothing happening, check that your firewall
isn't blocking the packets.

Ubuntu *shouldn't* have this issue but I have seen it on CentOS.


On Wed, Oct 9, 2019 at 1:55 AM Jack Hickish  wrote:

> Hi Heystek,
>
> Gonna throw this one to the maillist because some other folk might find
> the conversation useful.
>
> Am I right in thinking that you have a ROACH2 design which is outputting
> data over the 10GbE port (similar to the transmission side of tutorial 2)
> but want to know how to receive the data from a server, rather than just
> the loopback test performed in the tutorial?
> If so, the answer is, you'll need some code similar to
> https://wiki.python.org/moin/UdpCommunication#Receiving
> This will work fine for relatively low speed - for higher performance
> you'll probably want to look at using the C socket library directly, or one
> of the various higher-level libraries that other astronomy folk use which
> include (e.g. spead2 (for reading SPEAD packets) and/od full piplineing
> engines like HASHPIPE / Bifrost). Needless to say, everyone likes their
> software to be slightly different to everyone else's, so there are a bunch
> of libraries around. But I'd recommend starting with python to get the hang
> of things.
>
> In the example, you instantiate a UDP/IP socket (the traffic from a CASPER
> 10GbE core is always UDP), and bind it to the IP address and port you want
> to receive on (i.e, this should be the same as the destination address the
> ROACH is using).
> Then you simply call recvfrom (or recv) against the socket and get your
> data back as a raw binary string (which you'll need to decode with
> struct.unpack calls (or numpy.fromstring, or similar).
>
> Things you might want to try when this inevitably doesn't work out the box.
> 1. Verify your ROACH really is sending packets by putting some registers
> which count the number of valid eof pulses going into the ethernet core.
> (some of this kind of debugging is automatically built in to casperfpga --
> see tut2 for details)
> 2. run tcpdump (`sudo tcpdump -i `) to verify
> that packets are showing up at your machine. Use tcpdump's -e flag to check
> that the MAC addresses / IP addresses in this packet are what you expect.
> 3. Write a simple python TX script (
> https://wiki.python.org/moin/UdpCommunication#Sending) to send packets
> from one server to another, to verify your receive code is working without
> the bazillion unknowns a ROACH brings to the table.
> 4. Be sure to check that the packets you are sending are smaller than the
> MTU (
> https://www.cyberciti.biz/faq/how-can-i-setup-the-mtu-for-my-network-interface/)
> that your server will accept
>
>
> Cheers
> Jack
>
> On Tue, 8 Oct 2019 at 03:08, Heystek Grobler 
> wrote:
>
>> Hey Jack
>>
>> I hope that you are still doing well?
>>
>> I am struggling with the 10GBE SFP+ block. I have it in my design, the
>> design complies and is working, but how do I actually get the data from
>> the 10 GBE block?
>>
>> To use a python script with a BRAM block over normal ethernet is easy, but
>> how do I go to work with the 10 GBE block? The tutorials do not really
>> explain it or provide an example.
>>
>> Have a great day
>>
>> Heystek
>>
>>
>> --
>> Heystek Grobler
>> 0832721009
>> 012 3013202
>> heys...@hartrao.ac.za
>>
>> Spectroscopy Research Group
>> Department of Fundamental Astronomy
>> South African Radio Astronomy Observatory (SARAO) Hartebeesthoek Site
>>
>>
>> --
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Re: [casper] ROACH-2 Register Read/Write Errors

[James Smith]

Hello Kristen,

You're using rather out-of-date software there...

Could you try using casperfpga instead of corr, and upgrade your katcp to
at least version 0.6.2? (Do it in a virtual environment if you don't want
to clobber your install).

I use this particular casperfpga commit on ROACH2, but I think more recent
ones might work:
https://github.com/ska-sa/casperfpga/tree/v3.1

See if that assists?

Regards,
James


On Fri, Jan 10, 2020 at 11:38 PM 'Virkler, Kristen M (US 335J)' via
casper@lists.berkeley.edu  wrote:

> Hello,
>
>
>
> I am running a script on ROACH-2 boards that writes and reads a particular
> register (ex: acc_len). After 31 or more write/read commands I consistently
> get the following errors:
>
>
>
> Exception in thread Thread-254:
>
> Traceback (most recent call last):
>
>   File "/usr/lib/python2.7/threading.py", line 801, in __bootstrap_inner
>
> self.run()
>
>   File "/usr/lib/python2.7/threading.py", line 754, in run
>
> self.__target(*self.__args, **self.__kwargs)
>
>   File "grab.py", line 38, in progFpga
>
> *fpga.write_int('acc_len',65536)*
>
>   File "/usr/local/lib/python2.7/dist-packages/corr/katcp_wrapper.py",
> line 412, in write_int
>
> self.write(device_name, data, offset*4)
>
>   File "/usr/local/lib/python2.7/dist-packages/corr/katcp_wrapper.py",
> line 362, in write
>
> % (device_name, offset, unpacked_wrdata, unpacked_rddata))
>
> *RuntimeError: Verification of write to acc_len at offset 0 failed. Wrote
> 0x0001... but got back 0x...*
>
>
>
>
>
> Exception in thread Thread-264:
>
> Traceback (most recent call last):
>
>   File "/usr/lib/python2.7/threading.py", line 801, in __bootstrap_inner
>
> self.run()
>
>   File "/usr/lib/python2.7/threading.py", line 754, in run
>
> self.__target(*self.__args, **self.__kwargs)
>
>   File "grab.py", line 87, in newSpec
>
> *specCountOld = fpga.read_uint('acc_cnt');*
>
>   File "/usr/local/lib/python2.7/dist-packages/corr/katcp_wrapper.py",
> line 424, in read_uint
>
> data = self.read(device_name, 4, offset*4)
>
>   File "/usr/local/lib/python2.7/dist-packages/corr/katcp_wrapper.py",
> line 270, in read
>
> str(size))
>
>   File "/usr/local/lib/python2.7/dist-packages/corr/katcp_wrapper.py",
> line 61, in _request
>
> reply, informs = self.blocking_request(request,keepalive=True)
>
>   File
> "/usr/local/lib/python2.7/dist-packages/katcp-0.3.4-py2.7.egg/katcp/client.py",
> line 623, in blocking_request
>
> (msg.name, timeout))
>
> *RuntimeError: Request read timed out after 10.0 seconds.*
>
>
>
>
>
> The issue is resolved by restarting the script and creating new katcp
> client connections with the ROACH-2 boards.
>
>
>
> tcpborphserver information:
>
> #version memcpy-88-g38ad77a-dirty
>
> #build-state 2013-04-11T11:50:43
>
>
>
> Any help or suggestions would be very much appreciated!
>
>
>
> Thanks,
>
>
>
> Kristen Virkler
>
> NASA JPL
>
>
>
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Re: [casper] ROACH2 / katADC million channel spectrometer

[James Smith]

Hello Molly,

We have done something broadly similar using ROACH2 and katADC, but only
1024 channels:
https://github.com/ska-sa/AVNRoachGateware/tree/master/WideBandSpectrometer

What frequency are you looking at? The only thing I'm thinking is that you
might struggle to get the design to meet timing if you're clocking the
board too fast.

Shout if you get stuck.

Regards,
James


On Mon, Mar 9, 2020 at 8:34 PM Molly Smith  wrote:

> Hello,
>
> I'm new to CASPER and am trying to implement a million channel
> spectrometer on ROACH2 with the katADC. Does anyone know of any useful
> resources or has done something similar?
>
> I have experience using Vivado for newer FPGA development and am
> comfortable with Verilog & VHDL. I'm not familiar with the Simulink/ISE
> workflow and have been relying on the tutorials to come up to speed.
>
> I'm currently trying to modify Tutorial 3 (wideband spectrometer) to use
> the katADC instead.
>
> Thanks,
> Molly
>
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Re: [casper] ROACH1 - ethernet problem.

[James Smith]

Just to add to what Jason has said, older 100 Mbps switches are easy enough
to pick up secondhand on eBay and such, depending on where you are. They're
quite cheap.

On Fri, Apr 17, 2020 at 3:19 PM Jason Manley  wrote:

>
> > Since we are running the ancient Debian Etch on this unit, I have no
> access to ethtool, with which I understand that you can switch to 100mpbs.
> Is there any other way to force 100mbps operation?
>
> This actually wouldn't work anyway (we tried it). Something is broken in
> that Nat.Semi PHY's autonegotiation. Sometimes it works, other times not.
> And some boards were more susceptible to failing.
>
> You really need a 100mbps switch, or a 1Gbps switch that you can
> down-speed to lock the port to 100mbps.
>
> Jason
>
>
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Re: [casper] ROACH1 - ethernet problem.

[James Smith]

Ramesh,

I've never actually gotten a ROACH to talk directly to a server. The
auto-negotiation in the NIC is not great.

You pretty much need a switch in-between. Which is why Jason recommended
using an old 100Mbps switch.

Regards,
James


On Fri, Apr 17, 2020 at 4:00 PM Ramesh Karuppusamy 
wrote:

>
>
> I just tried this by putting a spare network interface on to 100mbps and
> also forcing the ROACH1 eth0 to 100mpbs - this did not help. Looks like the
> ethernet device on the ROACH1 is dead.
>
> I used mii-tool to force 100mbps operation:
>
> root@roach:~# mii-tool -F 100baseTx-HD eth0
> root@roach:~# mii-tool eth0
> eth0: 100 Mbit, half duplex, link ok
>
> And similar command on a server with spare eth3 (connected to the ROACH in
> question).
>
> Cheers,
> Ramesh
>
>
>
>
> On 17. Apr 2020, at 15:41, James Smith  wrote:
>
> Just to add to what Jason has said, older 100 Mbps switches are easy
> enough to pick up secondhand on eBay and such, depending on where you are.
> They're quite cheap.
>
> On Fri, Apr 17, 2020 at 3:19 PM Jason Manley  wrote:
>
>>
>> > Since we are running the ancient Debian Etch on this unit, I have no
>> access to ethtool, with which I understand that you can switch to 100mpbs.
>> Is there any other way to force 100mbps operation?
>>
>> This actually wouldn't work anyway (we tried it). Something is broken in
>> that Nat.Semi PHY's autonegotiation. Sometimes it works, other times not.
>> And some boards were more susceptible to failing.
>>
>> You really need a 100mbps switch, or a 1Gbps switch that you can
>> down-speed to lock the port to 100mbps.
>>
>> Jason
>>
>>
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Re: [casper] Measuring a FFT in Simulink

[James Smith]

Hello Heystek,

You can probably use a "to workspace" sink, then you'll be able to display
the data however you want in some matlab code once the simulation is
finished running.

Canonically, just applying an FFT to frequency-domain data will get you
back into the time domain, multiplied by some scaling factor. You need both
halves of the symmetric FFT though, so the output of e.g. the
fft_wideband_real wouldn't be meaningful to apply another FFT to it.

Regards,
James




On Thu, Apr 23, 2020 at 9:40 AM Heystek Grobler 
wrote:

> Good day Casperites
>
> I have an interesting question. I am using a  FFT in simulink for the use
> in a spectrometer design. I want to test the output of the FFT by using
> some kind of scope. Simulink only has spectrum scope, that would be
> perfect, but the scope does a second FFT on the signal. The other option is
> a vector scope, but that does not give the result that I am looking for.
>
> Does anyone have a suggestion on how I can see the results of the FFT in
> simulink?
>
> Then I have another question. What would be expected if I do a FFT on a
> FFT? As far as I can figure out, the FFT of the FFT should just be time
> reversed?
>
> Thanks for the help!
>
> Heystek
>
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Re: [casper] Measuring a FFT in Simulink

[James Smith]

Hello Heystek,

This should have been part of your undergrad signal-processing course.
Usually in an inverse FFT, they include a scaling factor of 1/sqrt(2) or
something like that, I forget exactly. You might find some references here:
https://www.dspguide.com/

The application is doing signal-processing in the frequency domain, which
can often be computationally more efficient than in the time-domain. You'd
multiply a window of frequency domain data with the frequency-domain
representation of what your filter should look like, then IFFT to get a
filtered time-domain signal.

Just note that for a spectrometer we'd generally use a PFB, not just an
FFT, so the same mathematical relation is NOT true for these cases.

Regards,
James


On Thu, Apr 23, 2020 at 10:00 AM Heystek Grobler 
wrote:

> Hey James
>
> I thought of the “to workspace” sink. I am not to familiar to write from
> Simulink to the workspace, but I will give it a go! Thanks for the help.
>
> Out of curiosity, if I have both halves of the symmetric FFT, what would
> be an application do to another FFT? I have written an Matlab script to
> play around with this idee. When I run the script, the the FFT of an FFT
> gives me a time domain signal, but the result has a larges amplitude. When
> I do a 3rd FFT I get the frequency domain again, and it is also amplified.
>
> It is just something that I picked up.
>
> Heystek
>
> On 23 Apr 2020, at 11:51, James Smith  wrote:
>
> Hello Heystek,
>
> You can probably use a "to workspace" sink, then you'll be able to display
> the data however you want in some matlab code once the simulation is
> finished running.
>
> Canonically, just applying an FFT to frequency-domain data will get you
> back into the time domain, multiplied by some scaling factor. You need both
> halves of the symmetric FFT though, so the output of e.g. the
> fft_wideband_real wouldn't be meaningful to apply another FFT to it.
>
> Regards,
> James
>
>
>
>
> On Thu, Apr 23, 2020 at 9:40 AM Heystek Grobler 
> wrote:
>
>> Good day Casperites
>>
>> I have an interesting question. I am using a  FFT in simulink for the use
>> in a spectrometer design. I want to test the output of the FFT by using
>> some kind of scope. Simulink only has spectrum scope, that would be
>> perfect, but the scope does a second FFT on the signal. The other option is
>> a vector scope, but that does not give the result that I am looking for.
>>
>> Does anyone have a suggestion on how I can see the results of the FFT in
>> simulink?
>>
>> Then I have another question. What would be expected if I do a FFT on a
>> FFT? As far as I can figure out, the FFT of the FFT should just be time
>> reversed?
>>
>> Thanks for the help!
>>
>> Heystek
>>
>> --
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>> "casper@lists.berkeley.edu" group.
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>> email to casper+unsubscr...@lists.berkeley.edu.
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>>
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Re: [casper] casperfpga module error: no module named bitfield

[James Smith]

Excellent insight about Python, Jack.

For the information of anyone interested, I did our port and tested it 
on SKARAB. Amish Patel did some testing of the katcp stuff on Red Pitaya 
- but I'm not sure that I remember what the outcome was. I think it 
didn't work and I did not have a chance at the time to fix the problem. 
But then it may have worked. I forget.


Regards,
James


On 2020/05/07 13:46, Jack Hickish wrote:

Hi all

It seems a bunch of people have made Py3 versions which, for very 
understandable reasons, mostly only work for the boards they have on 
hand to test. E.g., the ska-sa branch has only been tested (as far as 
I'm aware) with SKARAB, and when I used it wouldn't work out the box 
on SNAP. I've been trying to gather different people's work in the 
casper-astro py3-merge branch, this includes the ska-sa/python3-port 
branch, SNAP work from others, and will at some point incorporate some 
SNAP2 stuff from me.


I've no idea what the state of katcp (i.e. ROACH2 / SNAP+raspberry pi) 
comms is - I suspect it won't be without issues. ROACH2 also 
potentially creates issues in that most of the earlier ROACH2 boot 
images don't support casperfpga's mechanism for programming. So shout 
if you get into trouble. FWIW the way I've been installing casperfpga is:


git clone it; cd casperfpga
pip install -r build_requirements.txt
python setup.py install

I have no idea if this is the recommended way. It is python after all, 
so it's important that there should be at least 4 ways to install, and 
ideally only 2.5 of these should actually work.


Cheers
Jack

On Thu, 7 May 2020 at 09:01, Adam Isaacson <mailto:aisaac...@ska.ac.za>> wrote:


Hi Sean and Wael,

Yes, that is correct. Casperfpga is only supported with python 2.x
for now. We have been working on porting this to python3. I know
at SARAO we have a python3 compatible version, but I haven't
tested it fully yet.

You are welcome to try and let me/James Smith know:

https://github.com/ska-sa/casperfpga/tree/python3-port

Kind regards,

Adam Isaacson
South African Radio Astronomy Observatory (SARAO)
Hardware Manager
Cell: (+27) 825639602
Tel:  (+27) 215067300
email: aisaac...@ska.ac.za <mailto:aisaac...@ska.ac.za>





On Thu, May 7, 2020 at 2:38 AM Wael Farah mailto:wael.a.fa...@gmail.com>> wrote:

Hi Sean,

I might be wrong, but this error is due to the fact that the
casperfpga module that you are using (when you do "pip
install" and/or the master branch of the github repo) is meant
to work on python 2.x.

What I can suggest doing is the following:

Uninstall casperfpga
>> pip uninstall casperfpga

Then in your git directory, do a
>> git checkout py3-merge

This will switch to the python3 version of the module, and
then install it.

Hope this will fix the problem!

Cheers,
Wael

On Wed, 6 May 2020 at 10:23, Sean Mckee mailto:semc8...@colorado.edu>> wrote:

Greetings Casperites,

I'm new to Linux, and I think I must have some simple
setting adjusted incorrectly.

I'm running ubuntu 16.04 and tried this on a fresh install.

I first simply tried "pip install casperfpga", but this
gave me the error message:

ERROR: Could not find a version that satisfies the
requirement casperfpga (from versions: none)
ERROR: No matching distribution found for casperfpga

I then cloned from
https://github.com/casper-astro/casperfpga.git and
installed. The installation seemed to go fine, but when I
open up an ipython instance and type "import casperfpga" I
get the following:

> 1 import casperfpga


/home/sean/Casper/casper_venv/lib/python3.5/site-packages/casperfpga-0.1.3-py3.5-linux-x86_64.egg/casperfpga/__init__.py
in ()
      4
      5 # import all the main classes that we'll use often
> 6 from bitfield import Bitfield, Field
      7 from katadc import KatAdc
      8 from casperfpga import CasperFpga

ImportError: No module named 'bitfield'

I tried installing bitfield via "pip install bitfield",
but this seems to be a different version of bitfield than
expected by casperfpga. I get this error message:

> 1 import casperfpga


/home/sean/Casper/casper_venv/lib/python3.5/site-packages/casperfpga-0.1.3-py3.5-linux-x86_64.egg/casperfpga/__init__.py
in ()
      4
      5 # import all the main classes that we'll use often
> 6 from bitfield import Bitfield, Field

Re: [casper] Help with timing constraint

[James Smith]

Hello Heystek,

You will have to go through the timing reports and see which signal path is
failing timing, and by how much.

Once you have an idea, you will need to sprinkle delay blocks and / or
adjust latencies in your logic to get to a point where the place-and-route
can find a layout that satisfies timing requirements.

It's a bit of a black art, always hit and miss for me.

Regards,
James




On Wed, Aug 26, 2020 at 8:00 AM Heystek Grobler 
wrote:

> Good day everyone
>
> I am running a design but ran into this problem:
>
> xflow done!
> touch __xps/system_routed
> xilperl /opt/Xilinx_ISE/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl
> -error yes implementation/system.par
> Analyzing implementation/system.par
>
> 
> ERROR: 1 constraint not met.
>
> PAR could not meet all timing constraints. A bitstream will not be
> generated.
>
> To disable the PAR timing check:
>
> 1> Disable the "Treat timing closure failure as error" option from the
> Project Options dialog in XPS.
>
> OR
>
> 2> Type following at the XPS prompt:
> XPS% xset enable_par_timing_error 0
>
> 
> system.make:140: recipe for target 'implementation/system.bit' failed
> gmake: *** [implementation/system.bit] Error 1
> ERROR:EDK -
>Error while running "gmake -f system.make bits".
>
> It seems to be a timing constraint.
>
> How do I deal with this?
>
> Thanks for the help!
>
> Heystek
>
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Re: [casper] Installation of Matlab 2012B

[James Smith]

Hi Heystek,

Unfortunately not - I have had this in the past as well IIRC, some of the
more modern Linux distributions will give you something like "en0s1" or the
like. Matlab is stuck in the past, looking for eth0.

It's easy enough to change the name, but bear in mind that you may have
some funnies elsewhere that you will need to change as well (e.g. if you
have /etc/network/interfaces - you'll need to update that too).

Regards,
james


On Tue, Aug 18, 2020 at 10:51 AM Heystek Grobler 
wrote:

> Hey Mike
>
> Thank you for your reply!
>
> On the Mathworks forums some of the folks suggest to “force” a name
> change. Apparently the license is looking for “eth0” but on my machine it
> is “em1”.  That is what is. causing the error.
>
> I was just wondering if there is perhaps a more elegant solution to this.
>
> Thanks for the help!
>
> Heystek
>
>
>
>
> On 18 Aug 2020, at 12:44, Michael D'Cruze 
> wrote:
>
> Hi Heystek,
>
> I’ve seen a similar thing recently installing ISE on a Linux 7 machine. It
> looks like a complaint about the naming convention of your primary NIC. You
> can force a name-change if you want using the network manager (I did it in
> RHEL, unsure about Ubuntu) but better to find a solution from Mathworks if
> you can. What does the indicated solution say?
>
> Good luck,
> Mike
>
>
> *From:* Heystek Grobler [mailto:heystekgrob...@gmail.com
> ]
> *Sent:* 18 August 2020 11:34
> *To:* Casper Lists
> *Subject:* [casper] Installation of Matlab 2012B
>
> Hello everyone
>
> I have a bit of a problem. The first time that I am experiencing it. I am
> trying to install Matlab 2012B on a Ubuntu machine (That I redid), but the
> installation gives this error:
>
> 
>
> Does anyone perhaps know how to fix this?
>
> Heystek
>
>
> --
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Re: [casper] SNAP FPGA data endianness and networking

[James Smith]

Hello Nitish,

So I'm going to play devil's advocate and say that while you could do the
byte swapping in the FPGA, it would be morally wrong ;-)

Ideally, all data that goes out on a network will be network order, and you
use the ntohl or htohs functions to get it in host format. That way the
code stays more portable - if you one day find yourself on a big-endian
system, it would work without modification.
(https://en.wikipedia.org/wiki/Endianness#Networking)

Sometimes for performance reasons you may have to make these kinds of
compromises, and if you do you should document them well! But most modern
servers should have no issue with 10Gb/s datarates. You could probably even
do the swaps in the GPUs using Nvidia's primitives.

Regards,
James




On Tue, Aug 18, 2020 at 1:28 PM Nitish Ragoomundun <
nitish.ragoomun...@gmail.com> wrote:

> Hi,
>
> Thanks a lot Jack. It makes sense.
> And thank you very much for the note on the 2x32-bit pair. It is exactly
> how our data is formatted.
> Ok, we will go with an FPGA correction instead of a CPU byteswap. I am
> guessing it will be faster this way.
>
> Thanks again.
> Cheers
> Nitish
>
>
> On Tue, Aug 18, 2020 at 4:47 PM Jack Hickish 
> wrote:
>
>> Hi Nitish,
>>
>> To try and answer your first question without adding confusion --
>>
>> If you send a UFix64_0 value into the 10GbE block, you will need to
>> interpret it on the other end via an appropriate 64-bit byte swap if your
>> CPU is little-endian.
>> If you send a 64-bit input into the 10GbE block where the most
>> significant 32 bits are the value A, and the least significant bits are
>> value B, you should interpret the 64-bits  on your little endian CPU as the
>> struct
>>
>> typedef struct pkt {
>>   uint32_t A;
>>   uint32_t B;
>> } pkt;
>>
>> where each of the A and B will need byteswapping before you use them.
>>
>> To answer your second question --
>> Yes, you can absolutely flip the endianness on the FPGA prior to
>> transmission so you don't have to byteswap on your CPU. You can either do
>> this with a bus-expand + bus-create blocks, using the first to split your
>> words into bytes, and then flipping them before concatenating. The Xilinx
>> "bitbasher" block would also be good for this, using the Verilog (for a
>> 64-bit input):
>>
>> out = {in[7:0], in[15:8], in[23:16], in[31:24], in[39:32], in[47:40],
>> in[55:48], in[63:48]}
>>
>> If your 64 bit data streams are not made up of 64-bit integers (eg, they
>> are pairs of 32-bit integers) then you should flip the 4 bytes of each
>> value individually, but leave the ordering of the two values within the 64
>> bits unchanged.
>>
>> Hopefully that makes sense
>>
>> Jack
>>
>>
>> On Tue, 18 Aug 2020 at 13:28, Nitish Ragoomundun <
>> nitish.ragoomun...@gmail.com> wrote:
>>
>>>
>>> Hello,
>>>
>>> We are setting up the digital back-end of a low-frequency telescope
>>> consisting of SNAP boards and GPUs. The SNAP boards packetize the data and
>>> send to the GPU processing nodes via 10 GbE links. We are currently
>>> programming the packetizer/depacketizer.
>>> I have a few questions about the 10gbe yellow blocks and endianness. We
>>> observed from the tutorials that the data stored in bram is big-endian. I
>>> would like to know how the data is handled by the 10gbe and in what form is
>>> it sent over the network.
>>> Our depacketizers run on Intel processors, which are little-endian. We
>>> are aware that network byte order is big-endian, but we noticed that
>>> integer data can be sent from one Intel machine to another via network
>>> without ever calling ntohl( ) or htonl( ) and the data was preserved. So,
>>> we would like to know if we need to correct the endianness when receiving
>>> the data from the SNAP.
>>>
>>> If we need to perform this correction, is there a way we could possibly
>>> correct the endianness on the FPGA itself before input to the 10gbe block?
>>>
>>> Thanks,
>>> Nitish
>>>
>>> --
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>>> 
>>> .
>>>
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>> 

Re: [casper] SNAP FPGA data endianness and networking

[James Smith]

Hi Dave,

Yes of course! Though it makes little sense IMO to do the conversion on the
host CPU, as GPUs are pretty well-equipped to do this operation pretty
quickly if the need arises.

In some cases being pragmatic is important - if your instrument is small,
for example, and you don't have any user-supplied equipment. In the MeerKAT
case however, we specifically cater for having third-party computers
connecting to our network, then some sort of standards-compliance comes in
very handy. Though most of our data is 8- (or 10-) bit anyway so byte order
makes little difference.

Regards,
James


On Tue, Aug 18, 2020 at 3:30 PM David MacMahon  wrote:

> I guess I’m going to play angels’s advocate and suggest the pragmatic over
> the dogmatic. :)
>
> Some standards mandate network byte order, aka big endian, but if you’re
> not constrained in that way and you know that the data will be processed
> downstream by a little-endian system for the foreseeable future, then I
> think it makes sense to send it out in little-endian form. You can use
> `le32toh()` etc in the receiving code to make it host-endian agnostic, but
> on little-endian systems that is optimized away to nothing. Sure, that
> might only be saving 1 CPU cycle per value, but when you’re dealing with
> billions of values per second that can start adding up!
>
> Of course, the packet format should be documented regardless of which
> endianess is used. Future users will thank you.
>
> Cheers,
> Dave
>
> On Aug 18, 2020, at 07:21, James Smith  wrote:
>
> 
> Hello Nitish,
>
> So I'm going to play devil's advocate and say that while you could do the
> byte swapping in the FPGA, it would be morally wrong ;-)
>
> Ideally, all data that goes out on a network will be network order, and
> you use the ntohl or htohs functions to get it in host format. That way the
> code stays more portable - if you one day find yourself on a big-endian
> system, it would work without modification.
> (https://en.wikipedia.org/wiki/Endianness#Networking
> <https://en.wikipedia.org/wiki/Endianness#Networking>
> )
>
> Sometimes for performance reasons you may have to make these kinds of
> compromises, and if you do you should document them well! But most modern
> servers should have no issue with 10Gb/s datarates. You could probably even
> do the swaps in the GPUs using Nvidia's primitives.
>
> Regards,
> James
>
>
>
>
> On Tue, Aug 18, 2020 at 1:28 PM Nitish Ragoomundun <
> nitish.ragoomun...@gmail.com> wrote:
>
>> Hi,
>>
>> Thanks a lot Jack. It makes sense.
>> And thank you very much for the note on the 2x32-bit pair. It is exactly
>> how our data is formatted.
>> Ok, we will go with an FPGA correction instead of a CPU byteswap. I am
>> guessing it will be faster this way.
>>
>> Thanks again.
>> Cheers
>> Nitish
>>
>>
>> On Tue, Aug 18, 2020 at 4:47 PM Jack Hickish 
>> wrote:
>>
>>> Hi Nitish,
>>>
>>> To try and answer your first question without adding confusion --
>>>
>>> If you send a UFix64_0 value into the 10GbE block, you will need to
>>> interpret it on the other end via an appropriate 64-bit byte swap if your
>>> CPU is little-endian.
>>> If you send a 64-bit input into the 10GbE block where the most
>>> significant 32 bits are the value A, and the least significant bits are
>>> value B, you should interpret the 64-bits  on your little endian CPU as the
>>> struct
>>>
>>> typedef struct pkt {
>>>   uint32_t A;
>>>   uint32_t B;
>>> } pkt;
>>>
>>> where each of the A and B will need byteswapping before you use them.
>>>
>>> To answer your second question --
>>> Yes, you can absolutely flip the endianness on the FPGA prior to
>>> transmission so you don't have to byteswap on your CPU. You can either do
>>> this with a bus-expand + bus-create blocks, using the first to split your
>>> words into bytes, and then flipping them before concatenating. The Xilinx
>>> "bitbasher" block would also be good for this, using the Verilog (for a
>>> 64-bit input):
>>>
>>> out = {in[7:0], in[15:8], in[23:16], in[31:24], in[39:32], in[47:40],
>>> in[55:48], in[63:48]}
>>>
>>> If your 64 bit data streams are not made up of 64-bit integers (eg, they
>>> are pairs of 32-bit integers) then you should flip the 4 bytes of each
>>> value individually, but leave the ordering of the two values within the 64
>>> bits unchanged.
>>>
>>> Hopefully that makes sense
>>>
>>> Jack
>>>
>>>

Re: [casper] PFB (taps): Effects on time resolution

[James Smith]

Hello Colm,

Yes, you're correct. That's how some of our narrowband designs work - you
use each PFB channel as a very narrow bandpass filter, and treat its output
as a complex time-series. So you can pass it through another PFB to get a
higher-resolution spectrum, at the expense of very much lower time
resolution of course.

Regards,
James


On Fri, Aug 28, 2020 at 11:04 AM Colm Bracken  wrote:

> Hi Cedric,
>
> Great, thanks for confirming that.
> One more question, if you don't mind?
>
> If a narrow band signal is off-centre relative to one of my frequency
> bins, will the measured amplitude change each time I run the FFT?
> For example, if my FFT frequency bins are exactly 1 MHz wide (1024 pt FFT
> applied to 1 GSPS ADC data), and I am trying to measure a sinusoid with a
> frequency of 5.1 MHz, will the measured amplitude oscillate at a frequency
> of 0.1 MHz (5.1 MHz - 5 MHz)? Basically, my sampling (in terms of how often
> I sample the full time stream for the FFT) is out of phase with the signal
> to be measured?
>
> I probably didn't explain that very well, apologies.
>
> Best wishes,
> Colm
>
> On Fri, 28 Aug 2020 at 11:17, 'Cedric Viou' via casper@lists.berkeley.edu
>  wrote:
>
>> Hi Colm,
>>
>> You are right.
>>
>> PFB is a great way to reduce frequency smearing but the down-side is time
>> smearing.
>>
>> A brief event will be convolved with at least one of your PFB 8-tap
>> filters that end up feeding several FFT computations in a row.
>> So, you get time smearing for that short event...
>>
>> Regards,
>>
>> Cedric
>>
>>
>> Le 28/08/2020 à 11:56, Colm Bracken a écrit :
>> > Hi All,
>> >
>> > I have a question, which is probably DSP 101 basics, but I just wasn't
>> 100% sure.
>> >
>> > If I am applying a 1024 point FFT to a continuous time-stream from an
>> ADC with sampling ~ 1 GSPS, I will have a time resolution ~ 1 microsecond
>> (and frequency res. of ~ 1 MHz).
>> >
>> > But, if I instead apply an 8 tap PFB, am I essentially smearing out my
>> time resolution by a factor of 8, since I am now summing 8 rows of my 1024
>> point time streams?
>> > I can't see how the number of PFB taps wouldn't affect my time
>> resolution. Or am I missing something?
>> >
>> > Thanks in advance,
>> > Colm
>> >
>> > --
>> >
>> > *Dr Colm Bracken*
>> > Lecturer
>> > Maynooth University Experimental Physics
>> >
>> >
>> > Maynooth University, Maynooth, Co. Kildare, Ireland.
>> >
>> > T: +353 1 708 3641
>> > E: colm.brac...@mu.ie  W:
>> www.maynoothuniversity.ie 
>> >
>> > Follow my work on https://nuim.academia.edu/ColmBracken
>> >
>> >
>> >
>> > And
>> >
>> >
>> > Research Associate
>> >
>> > Astronomy & Astrophysics Section
>> > School of Cosmic Physics
>> > Dublin Institute for Advanced Studies
>> > 31 Fitzwilliam Place
>> > Dublin 2, D02 XF86
>> >
>> >
>> >
>> > T: +353 1 440 6656 ext 352
>> > E: cbrac...@cp.dias.ie  W:
>> www.dias.ie/2017/06/22/dr-colm-bracken <
>> https://www.dias.ie/2017/06/22/dr-colm-bracken>
>> >
>> > Follow my work on https://nuim.academia.edu/ColmBracken
>> >
>> > --
>> > You received this message because you are subscribed to the Google
>> Groups "casper@lists.berkeley.edu" group.
>> > To unsubscribe from this group and stop receiving emails from it, send
>> an email to casper+unsubscr...@lists.berkeley.edu > casper+unsubscr...@lists.berkeley.edu>.
>> > To view this discussion on the web visit
>> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAEx9wh9GmrYZ7_uLkXwSKqOp3GYm1Ei_0Bq-TPg9pt8LgQdprw%40mail.gmail.com
>> <
>> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAEx9wh9GmrYZ7_uLkXwSKqOp3GYm1Ei_0Bq-TPg9pt8LgQdprw%40mail.gmail.com?utm_medium=email_source=footer
>> >.
>>
>> --
>> Cedric Viou 
>>
>> Ingénieur de recherche
>>
>> Station de Radioastronomie de Nançay,
>> Observatoire de Paris, PSL Research University, CNRS, Univ. Orléans,
>> OSUC,
>> 18330 Nançay, France
>> http://www.obs-nancay.fr/
>>
>> phone : +33 (0) 248 51 8609
>> fax   : +33 (0) 248 51 8318
>>
>> www.openstreetmap.org/?mlat=47.381848=2.194415=18
>>
>> --
>> You received this message because you are subscribed to the Google Groups
>> "casper@lists.berkeley.edu" group.
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>> email to casper+unsubscr...@lists.berkeley.edu.
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>> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/68a23cbf-5320-8b50-7a4f-52379c4a2ad7%40obs-nancay.fr
>> .
>>
>
>
> --
>
> *Dr Colm Bracken*
> Lecturer
> Maynooth University Experimental Physics
>
>
> Maynooth University, Maynooth, Co. Kildare, Ireland.
>
> T: +353 1 708 3641
> E: colm.brac...@mu.ie W: www.maynoothuniversity.ie
>
> Follow my work on https://nuim.academia.edu/ColmBracken
>
>
>
> And
>
>
> Research Associate
>
> Astronomy & Astrophysics Section
> School of Cosmic Physics
> Dublin Institute for Advanced Studies
> 31 Fitzwilliam Place
> 

Re: [casper] Compiling design

[James Smith]

Hello Heystek,

Somewhere in your design, you are trying to use a Xilinx block as an input.
Replace it with one of the yellow blocks from the Casper tools, and you
should be okay. (Usually this will be a software register or a BRAM block.)

Regards,
James


On Tue, Aug 11, 2020 at 12:54 PM Heystek Grobler 
wrote:

> Good day everyone
>
> I am compiling a design for Roach2. I can into this error when running
> casper_xps:
>
> "xilinx input gateways cannot be used in a design. Only gpio blocks”
>
> How can I solve this or am I doing something stupid?
>
> Thanks for the help
>
> Heystek
>
> --
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> 
> .
>

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Re: [casper] Compiling design

[James Smith]

Send a screen snip of what you've got, Heystek?

On Tue, Aug 11, 2020 at 1:22 PM Heystek Grobler 
wrote:

> Hey James and Mugundhan
>
> Thank you for your emails.
>
> Yes, I have a Shared BRAM block in my design. The BRAM block is from the
> casper blockset. So I should rather use something else for the design?
>
> On 11 Aug 2020, at 15:03, James Smith  wrote:
>
> Hello Heystek,
>
> Somewhere in your design, you are trying to use a Xilinx block as an
> input. Replace it with one of the yellow blocks from the Casper tools, and
> you should be okay. (Usually this will be a software register or a BRAM
> block.)
>
> Regards,
> James
>
>
> On Tue, Aug 11, 2020 at 12:54 PM Heystek Grobler 
> wrote:
>
>> Good day everyone
>>
>> I am compiling a design for Roach2. I can into this error when running
>> casper_xps:
>>
>> "xilinx input gateways cannot be used in a design. Only gpio blocks”
>>
>> How can I solve this or am I doing something stupid?
>>
>> Thanks for the help
>>
>> Heystek
>>
>> --
>> You received this message because you are subscribed to the Google Groups
>> "casper@lists.berkeley.edu" group.
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>> email to casper+unsubscr...@lists.berkeley.edu.
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>> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/7A801B91-ED60-4D83-A14A-3B0B1D8D4E8E%40gmail.com
>> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/7A801B91-ED60-4D83-A14A-3B0B1D8D4E8E%40gmail.com?utm_medium=email_source=footer>
>> .
>>
>
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Re: [casper] Wideband FFT using Xilinx blocks as primitives

[James Smith]

Hello Morag,

AFAIK, Xilinx's FFT IP block only accepts a single block at a time. I think
that was a large part of the reason why there's a CASPER FFT in the first
place - because we needed multiple samples at once.

We have used the Xilinx core in narrowband designs in the past - KAT-7's
narrowband modes were done that way, after a first "coarse" channelisation
stage using a Casper PFB, and an async pfb_fir followed by the Xilinx FFT
block. If you want to pick them apart, they are in here:
https://github.com/ska-sa/kat7_fpga/tree/master/fengine_oh (warning: newer
versions of Matlab / mlib_devel may struggle with these old files. AVN's
narrowband R2 design is somewhat more modern if you have a R2 setup handy,
they are based on similar principles:
https://github.com/ska-sa/AVNRoachGateware/tree/devel/source/NarrowBandSpectrometer
)

Regards,
James


On Wed, Nov 18, 2020 at 5:53 PM Morag Brown  wrote:

> Hi all,
>
> Has anyone ever put together a wideband FFT (i.e an FFT that accepts
> multiple demuxed samples per FPGA clock cycle) using the Xilinx sysgen FFT
> block? Looking at the docs, it seems the IP core can't be configured to
> accept multiple parallel inputs (but I could be wrong), so one would need
> to construct the 2D decomposition of the 1D FFT using Xilinx FFT blocks as
> primitives.
>
> I'm doing some FFT comparisons for my MSc, and would like to include the
> Xilinx core. I thought it'd be good to check if anyone's already
> implemented this before embarking on the adventure myself...
>
> Morag Brown
> SARAO
>
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> 
> .
>

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Re: [casper] Timing issue with System Generator

[James Smith]

Hello Idir,

It's been a while since I've played around with this, but it looks as
though you've chosen some fairly strange settings there.

We don't usually manipulate the settings in the Xilinx Sysgen block
directly - it's usually done through one of the CASPER yellow blocks -
depending on what FPGA platform we are using. Are you using the CASPER
tools at all? Or SysGen directly?

Generally you have to consider one FPGA clock as one "tick" in Simulink. So
you'll have to scale your X-axis appropriately for your simulated output.

It looks as though you've got a clock period set of 50 million nanosecons -
or about 20 Hz if my maths isn't totally wrong? No FPGA that I know of will
clock itself that low - I'm not sure how smart Sysgen is, but it might be
ignoring the value you've set as out of range and going with some default.

Regards,
James


On Fri, Nov 6, 2020 at 3:00 PM Idir Mellal  wrote:

> Hi Fulks,
>
> I want to implement a complex neuronal model, biological neurons, using
> the Xilinx System Generator. I developed a Matlab model and did the
> simulations for 2 s to validate it. After that, I realized a hardware
> architecture using SysGen.
>
> The problem I am facing is the results are not correlated in terms of
> timing, I don't know the appropriate setting to simulate 2s on the FPGA!
> I summarized the model in the attached file.
>
> Please let me know if you have any solution or suggestion.
> I really appreciate your help.
>
> Best regards,
> Idir.
>
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> .
>

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Re: [casper] Timing issue with System Generator

[James Smith]

Hello Idir,

Do you have the SLX file? Can you share which version of matlab that you're
using? I can possibly take a look tomorrow.  (Email me directly if you
don't want to share it in a public space.)

Regards,
James


On Mon, Nov 9, 2020 at 5:49 PM Idir Mellal  wrote:

> Hi James,
>
> Thanks for your answer.
>
> I do not use a CASPER. I am using a ZCU102 platform.
> For the frequency, you're right. The initial period was 10ns, but I
> didn't get the expected response. So I started changing the frequency.
>
> Please do not hesitate if you have any other suggestions.
>
> Best regards,
> idir.
>
> On Sun, Nov 8, 2020 at 11:36 PM James Smith  wrote:
>
>> Hello Idir,
>>
>> It's been a while since I've played around with this, but it looks as
>> though you've chosen some fairly strange settings there.
>>
>> We don't usually manipulate the settings in the Xilinx Sysgen block
>> directly - it's usually done through one of the CASPER yellow blocks -
>> depending on what FPGA platform we are using. Are you using the CASPER
>> tools at all? Or SysGen directly?
>>
>> Generally you have to consider one FPGA clock as one "tick" in Simulink.
>> So you'll have to scale your X-axis appropriately for your simulated output.
>>
>> It looks as though you've got a clock period set of 50 million nanosecons
>> - or about 20 Hz if my maths isn't totally wrong? No FPGA that I know of
>> will clock itself that low - I'm not sure how smart Sysgen is, but it might
>> be ignoring the value you've set as out of range and going with some
>> default.
>>
>> Regards,
>> James
>>
>>
>> On Fri, Nov 6, 2020 at 3:00 PM Idir Mellal  wrote:
>>
>>> Hi Fulks,
>>>
>>> I want to implement a complex neuronal model, biological neurons, using
>>> the Xilinx System Generator. I developed a Matlab model and did the
>>> simulations for 2 s to validate it. After that, I realized a hardware
>>> architecture using SysGen.
>>>
>>> The problem I am facing is the results are not correlated in terms of
>>> timing, I don't know the appropriate setting to simulate 2s on the FPGA!
>>> I summarized the model in the attached file.
>>>
>>> Please let me know if you have any solution or suggestion.
>>> I really appreciate your help.
>>>
>>> Best regards,
>>> Idir.
>>>
>>> --
>>> You received this message because you are subscribed to the Google
>>> Groups "casper@lists.berkeley.edu" group.
>>> To unsubscribe from this group and stop receiving emails from it, send
>>> an email to casper+unsubscr...@lists.berkeley.edu.
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>>> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/91986729-0999-4f1d-ba68-3c1cded8b25dn%40lists.berkeley.edu
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>>> .
>>>
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Re: [casper] Problem with casperfpga

[James Smith]

Hi Guillermo,

Progska is needed for programming of SKARABs. I guess the way the module is
structured though, is it'll fail to import if progska isn't there.

I think try going into the progska directory, `make && make install` then
try again? It's been a while since I've done this.

The instructions might need to be updated, I think...

Regards,
James


On Thu, Feb 11, 2021 at 7:02 PM Guillermo Gancio  wrote:

> Hi all,
> I'm having a silly error that I Can't figure out.
> I'm installing casperfpga on a Ubuntu 18.04, python 2.7 and I get the
> error,
>
> ImportError: No module named progska
>
> I followed the steps from
> https://github.com/casper-astro/casperfpga#installation with no apparent
> errors...
>
> Thanks!
>
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