What is the current state fo the devices? Issue a CQUERY.
Peter Hunkeler
CREDIT SUISSE
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I'm thinking it is most likely either an installation or
configuration problem.
REGION size?
Peter Hunkeler
CREDIT SUISSE
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Hi,
*** posted in the IMS-L listserver, but no reaction. Hence cross posted in
IBM-MAIN RACF-L ***
We are currently using IMS V9 and Web Application Servers on Unix that
connect to IMS Connect. To ensure that only
Through the ISPVCALL STATUS function, I found that the system I'm
on is a zArch 2064 with 4 CPUs; however, is there a way I can
retrieve
[snip]
All that being said it could be a 2064-104, 2064-1C4, or a 2064-2C4
depending on features. You can use the command
D M=CPU to find your model number.
I don't suppose the attendants will carry their shops to Baltimore,
that's what William asked...
(could't resist).
Kees.
Tom Schmidt [EMAIL PROTECTED] wrote in message
news:[EMAIL PROTECTED]...
On Wed, 19 Jul 2006 09:54:59 -0700, George, William (DHS-ITSD) wrote:
My wife and I are looking
Thanks guys, I feel so much better. That's why i couldn't remember the
command, there isn't one.
There are tons of these at our site and they are all left over from many
many moons ago.
IE.
The one in deferred rollin state is G0049V00
whereas the (say) 2 entries are G0934V00 and G0935V00
Rugel José wrote:
Hi:
I have this problem with a new tape 3590E k ( green one ) :
CBR4105I No MEDIA3 scratch volumes available in library LIB3494.
CBR4196D Job ZAVAZ169, drive 0D02, volser SCRTCH, error code 140169.
The code 69 indicates there is no scratch volume MEDIA3,
- Original Message
Hi,
Would anyone have a project plan for doing the above or any pointers to
documentation
that I would find useful when embarking on such a task?
Kind Regards
Mark
Mark,
I found the 'JES3 White Paper' from E.Jaffe very useful to understand the
functionalities of
It's an interpreted language.
And its an OO language which has somewhat more overhead than
traditional non-OO languages.
Peter Hunkeler
CREDIT SUISSE
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Bruce Black wrote:
Can't remember the command to remove the entry from the base but keep
the dataset or, for another example get rid altogether.
a DEFERRED generation is not really part of the base. In the catalog,
there is a GDG sphere record for the base, with all the generations
Then the question becomes: Does the JVM tell the z/OS dispatcher
move the work from the zAAP to a general CPU while doing a JNI
call? Or does it leave it on the zAAP?
The JVM marks the task as being zAAP eligible or non-eligible.
The dispatcher puts zAAP eligible tasks on the zAAP work unit
Walter Marguccio wrote:
I found the 'JES3 White Paper' from E.Jaffe very useful to understand the
functionalities of both JES, and to see if such migration is worth. I did a
presentation some years ago at a customer site here in Germany who wanted to
migrate to JES2, too. Eventually, they
Walter Marguccio wrote:
I found the 'JES3 White Paper' from E.Jaffe very useful to understand
the functionalities of both JES, and to see if such migration is
worth. I did a presentation some years ago at a customer site here in
Germany who wanted to migrate to JES2, too. Eventually, they
Interesting. IBM-MAIN postings probably follow this rule.
http://technology.guardian.co.uk/weekly/story/0,,1823959,00.html
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Hi, Peter
Attached is the command output of CQUERY and D M=DEV(). Please take a
look! Much appreciate it in advance.
JC
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Joe,
IE.
The one in deferred rollin state is G0049V00
whereas the (say) 2 entries are G0934V00 and G0935V00
This could happen if G0049V00 was restored by DFSMSdss
after it had rolled out of the GDG and the number of
generations was already at the limit or the TGTGDS
parameter was set or allowed
On 20 Jul 2006 01:38:32 -0700, in bit.listserv.ibm-main you wrote:
- Original Message
Hi,
Would anyone have a project plan for doing the above or any pointers to
documentation
that I would find useful when embarking on such a task?
Kind Regards
Mark
Mark,
I found the 'JES3 White
Clark Morris wrote:
Yesterday, I read that a new NJE function will be available only in
JES2. The JES3 folks have yet to learn that if they are going to
justify their higher cost, they have to provide virtually all of the
function JES2 does plus the unique JES3 function. I like a lot of the
Tom,
However, there is a flag in the NVR that says I am a deferred
generation (probably in the catalog as well) and I don't know what
trouble that might cause later.
Wouldn't that be the same flag, Bruce? As I understand it, the BCS just
points to the volume and everything else is kept in
Radoslaw writes
The memory is not unique design. There are regular DIMMs inside the
book. High quality, ECC, good brand, but still same technology as in
PC.
Memory controllers are probably completely different, but the
back-end
(DIMMs) are not.
The PARTS that are used in the box are pretty
JC, I may be missing something but your inital question was about
device C5A9 and your CQUERY is for device D7FB.
Peter Hunkeler
CREDIT SUISSE
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Craddock, Chris wrote:
Radoslaw writes
The memory is not unique design. There are regular DIMMs inside the
book. High quality, ECC, good brand, but still same technology as in
PC.
Memory controllers are probably completely different, but the
back-end
(DIMMs) are not.
The PARTS
What follows is taken from discussion of the MVCL instruction in the current
Principles of Operation:
|
| As part of the execution of the instruction, the values
| of the two length fields are compared for the setting
| of the condition code, and a check is made for
| destructive overlap of the
-Original Message-
From: IBM Mainframe Discussion List
[mailto:[EMAIL PROTECTED] On Behalf Of john gilmore
Sent: Thursday, July 20, 2006 9:15 AM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: Why is z series so CPU poor?
snip
Architectures are extraordinarily difficult to compare unless
Somethings, like the SMS classes are stored in BOTH the catalog and
VVDS. I don't recall if the GDG flag is among them (I'm at home now,
no references)
now that I am at the office, I verified that there is an attribute byte
that is both in the catalog and the NVR (if it is SMS) for GDGs. It
There are quite a few reasons, rather than just one single one. The
biggie IMO is that z architecture is demonically complex to implement in
silicon.
It has always amazed me that IBM is able to put out a new processor
every year or two with little or no hardware logic errors. I know from
What is bizzare is that the ANTP0102I message is clearly documented to
apply to MODE(RESYNC) which requires that the pair be in SUSPEND state,
but you clearly specified MODE(COPY).Sounds like an IBM bug, either
the message is issued incorrectly or it has another undocumented
meaning. I
How do we know the number of hardware design errors? With IA32, it's easier to
discover these problems because the CPU is used by many people under many
operating systems. IBM designs the OS and CPU, making it much easier to cover
up any problems that do exist.
-Original Message-
I have an LPALST concatenation
PRODUCT.LPALIB
SYS1.LPALIB
In PRODUCT.LPALIB is MODULE1 (no alias)
In SYS1.LPALIB is MODULE1 with alias ALIAS1
After IPL (with CLPA of course) I can get to MODULE1 but not to ALIAS1.
Because MODULE1 is a duplicate I expect to get it from
I'm hoping Mark Thomen is monitoring the list this morning! :-)
I need to resurrect an old post. I'm running FINDIMBD and am seeing
something somewhat disturbing. I'm looking for catalogs that have the
IMBED parameter on them. Here is the JCL I'm running.
// EXEC PGM=FINDIMBD
===
-Original Message-
From: McKown, John [EMAIL PROTECTED]
Sent: 7/20/2006 9:13 AM
To: IBM-MAIN@BAMA.UA.EDU IBM-MAIN@BAMA.UA.EDU
Subject: Re: Why is zSeries so CPU poor?
-Original Message-
From: IBM Mainframe Discussion List
Michael Kuredjian writes
| How do we know the number of hardware design errors? With IA32, it's
easier to
| discover these problems because the CPU is used by many people under many
| operating systems. IBM designs the OS and CPU, making it much easier to
cover up
| any problems that do
But would the system even load MODULE1 from SYS1.LPALIB into the LPA
being that the module is there from the PRODUCT library? My guess is
no. If that is the case, no module, by extension, no alias to the
module because there wouldn't be a module for it to alias to.
Just a guess.
Rex
How do we know the number of hardware design errors? With IA32, it's easier to discover these problems because the CPU is used by many people under many operating systems. IBM designs the OS and CPU, making it much easier to cover up any problems that do exist.
IA32???
Nothing in the OS is
I'm wondering if anyone has any insight into this issue of MP effect
differences with the z/990 z/9 book designs. In particular, it is well known
that there is a cost associated with adding CP's because of the additional
communication/coordination overhead, however ... how has this changed
I guess the question could be rephrased as
Are the alias(s) only loaded with the base module and an alias entry
itself ignored?
-Original Message-
Pommier, Rex R.
But would the system even load MODULE1 from SYS1.LPALIB into the LPA
being that the module is there from the PRODUCT
berwatt wrote:
With idcams/dollect, i use :
SORT FIELDS=COPY
INCLUDE COND=(9,2,CH,EQ,C'D ')
OUTREC IFTHEN=(WHEN=(79,1,BI,EQ,B'1...'),
BUILD=(1,4,29,44,C'IS',121,6)),
IFTHEN=(WHEN=(79,1,BI,EQ,B'.1..'),
BUILD=(1,4,29,44,C'PS',121,6)),
Where is the content of
the BCS documented?
Unfortunately, nowhere. There was the infamous Catalog Diagnosis
Reference which had catalog and VVDS layouts but the last version was
for MVS/XA many years ago, before SMS.
I believe that the SMS class names and this SMS attribute byte are the
I didn't see much cynicism in my comment, although that may be the result of
being jaded by my experience with PC manufacturers and their reluctance to
admit and correct problems. I'm very used to both hardware and software
manufacturers ignoring obvious problems in their products.
I may have
Kuredjian, Michael wrote:
I may have mis-used the term cover-up. What I meant was that they[IBM] could
release software patches that specifically avoid making use of broken circuits in
silicon. However, I wasn't aware that mainframe developers routinely make use of
micro-assembly
I have been using this for the last 4-5 weeks on 5 different z/OS 1.7
systems with no problems at all.
I use to get all the service I want or just a PTF. Feel free to contact on
the address below, but remember I am in the UK.
Crispin Hugo
Systems Programmer, Macro 4
http://www.macro4.com/
Macro 4
Actually the terminology is much more ambiguous than that. Register
size, address size, bus size within CPU, bus size to memory, bus size to
peripherals, could all be different bit widths, and physical hardware
register sizes don't have to match the register sizes of the hardware
Has anyone used internet delivery for a zOS ServerPac? I've downloaded the
CustomPac Dialog and am trying to receive my order. The GIMGTPKG will
transfer a few datasets but croaks in the middle. I restart the job and
it xfers a few more and croaks... Always croaks with
TYPE
I
Use BIG region, like 256M. Make sure your exits allow you to really get
it.
If you STEPLIB, make sure the HFS/ZFS parts are at the same SMP/E level,
it won't run out of MIGLIB with mixed levels, but everything else I
trided WILL run out of MIGLIB as before.
Add a SYSPRINT DD and look for
Leif Rundberget (as quoted by Joel C. Ewing) wrote:
| Be careful with like terms between the PC(intel) world and the mainframe
| world. When someone says they have a 64-bit Intel server (Intel,
| Solaris, AMD, etc.), it does not mean that the server can access an
| address 64-bits long, the
What level of SMP are you using?
I do not steplib.
The region size did not help.
Thanks, BK
From: Rugen, Len [EMAIL PROTECTED]
Reply-To: IBM Mainframe Discussion List IBM-MAIN@BAMA.UA.EDU
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: Internet Service Retrieval
Date: Thu, 20 Jul 2006 13:08:14 -0500
34.07
-Original Message-
From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On
Behalf Of B Sysprog
Sent: Thursday, July 20, 2006 1:34 PM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: Internet Service Retrieval
What level of SMP are you using?
I do not steplib.
The region size did
On Thu, 20 Jul 2006 14:33:34 -0400, B Sysprog [EMAIL PROTECTED] wrote:
What level of SMP are you using?
I do not steplib.
The region size did not help.
Thanks, BK
I am at 34.10.Did you review the PSP buckets when you
installed SMP/E 3.4?
Mark
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Mark Zelden
Sr. Software and Systems
Hello List,
My current environment is Z/OS V 1.7 and DB2 V 7.1
I am migrating from Tivoli Decision Support for Z/OS Version 1.5.1 to TDS
1.6.0.
My problem is when I run data collection job I get a -407 abend . SQLSTATE is
23502
(An insert or update value is null, but the column cannot
The mainframe is very different from the PC in this regard. You might find
the chapter on Machine Check Handling in the POO to be interesting.
Mainframes are designed with extensive error detection and recovery
capabilities. z/OS records error information to LOGREC to assist in fixing
On Thu, 20 Jul 2006 10:45:37 -0400, Bruce Black [EMAIL PROTECTED]
wrote:
There are quite a few reasons, rather than just one single one. The
biggie IMO is that z architecture is demonically complex to implement in
silicon.
It has always amazed me that IBM is able to put out a new processor
On Thu, 20 Jul 2006 18:29:48 +, john gilmore [EMAIL PROTECTED]
wrote:
Higher fetch width is good, but it can have odd side effects. There were
System/360 models for which Load Halfword (LH) was slower than Load (L) not
just because of sign propagation but also because LH fetched four or
I don't think so, but I will probably try adjusting the REGION size to make
sure.
Jon
snip
I'm thinking it is most likely either an installation or
configuration problem.
REGION size?
/snip
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Over 100,000 pageviews on my site in the last 12 months and just five emails
about it.
The lurker/poster ratio is well known to anyone who's been a sysop, moderator
or administrator
on a public forum. 100:1 is pretty good - it's usually worse than that.
CompuServe was fun because you could
I clearly remember the first (L faster than LH on some machines) but can't
comment on the second (64 v. 32).
Charles
-Original Message-
From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On Behalf
Of Tom Marchant
Sent: Thursday, July 20, 2006 12:22 PM
To: IBM-MAIN@BAMA.UA.EDU
Hello all, I have a question. I have 2 lpars that are sharing the crypto
processors in the cpu. Usage domain is 1 and 0 respectively. Is there
any reason why only 3 come up on the z/os lpar and 4 come up on the
z/OS.e lpar? There are no start up errors on either system that I can
see and it has me
Check the crypto config on the image profile. I would guess that you don't
have 0 checked on the candidate list and/or online list. If the candidate
list
is not checked, I think you have to reactivate the LPAR to add it.
Richard
Ward, Mike S wrote:
Hello all, I have a question. I have 2 lpars
On Wed, 19 Jul 2006 13:09:25 -0400, Jon Brock [EMAIL PROTECTED] wrote:
I have a copy of the stack trace from the Tomcat issue, and I am taking
it up with some people who should be able to point me in the right
direction. I'm thinking it is most likely either an installation or
configuration
==
-Original Message-
From: Gerhard Postpischil [EMAIL PROTECTED]
Sent: 7/20/2006 3:53 PM
To: IBM-MAIN@BAMA.UA.EDU IBM-MAIN@BAMA.UA.EDU
Subject: Re: Why is zSeries so CPU poor?
Jeffrey D. Smith wrote:
When TRAP2/TRAP4 was first
Thanks,
That was the original question. Most of our clients use PKZIP so
(originally) it was a question of whether or not it was a problem with the
INFO-ZIP software or the installation or the method of transfer. In this
case, it turned out to be that we were trying to take a DASD volume
John,
Up there is probably Delaware.. the Credit card company(s) all seem
to like the legal system there.
Ed
On Jul 20, 2006, at 7:20 AM, Chase, John wrote:
-Original Message-
From: IBM Mainframe Discussion List On Behalf Of Shane
On Wed, 2006-07-19 at 09:54 -0700, George,
I think you mis-interpreted John's remarks. He didn't say anything
about mainframe developers extensively writing and testing microcode
instructions (which is not a documented user interface), but instead
extensively writing and testing z-Architecture assembler code (with the
High Level
Greetings,
What is the earliest z/OS level that will tolerate
ETCRE (Entry Table Create) that has the extended
addressing mode (ETDEAM) bit set?
Thanks in advance
Jeffrey D. Smith
Farsight Systems Corporation
24 BURLINGTON DR
LONGMONT, CO 80501
303-774-9381 direct
303-709-8153 cell
303-484-6170
The greater Washington, D.C., area should probably get a nomination as
well. Yes, many people include Baltimore in that equation. :-)
- - - - -
Timothy F. Sipples
Consulting Enterprise Software Architect, z9/zSeries
Tokyo (Serving IBM Japan and IBM Asia-Pacific)
E-Mail: [EMAIL PROTECTED]
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