Hi,

I don't think you can overestimate the logic requirements. Even if you can
fit in every feature so far, people will want the room to experiment.

A bigger FPGA would give it a lot more value. I know some people will want
to use it for things like (real-time) ray-tracing, testing new GPU
architectures, rendering voxels, etc. Sales will be proportional to spare
logic area. Also, a bigger chip allows to do more processing in parallel and
get some useful performance out of it. Seriously, there's no such thing as
too much die space.

It might even already be challenging to fit the basic design on the bigger
FPGA if you want to do it 'right'...

Kind regards,

Nicolas
 

-----Oorspronkelijk bericht-----
Van: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] Namens Timothy Miller
Verzonden: Tuesday, June 20, 2006 17:21
Aan: ogml
Onderwerp: [Open-graphics] Public debate on the possible switch-over to
3S4000

Perhaps I made my announcement prematurely, so I'd like to go into
some more detail about what we did, with our assumptions, and see what
everyone else thinks.

First of all, we do not want to switch parts if we can avoid it.
Using the ECP2-50 has advantages in price, saves us two weeks on OGD1,
and if we can cram a good 3D design into it, that saves us on die area
and therefore cost on the ASIC.

Our approach to judging the fitness of the ECP2-50 was to take some
pieces of other designs and see how well they fit.  One part is a
wider but simpler 2D graphics engine.  The other part is some video
backend processing logic.  Add to those various pieces of support
logic like memory controller, etc., and you have what should be a good
estimate for a graphics chip.  We didn't try to put them together into
an actual design; rather, we synthesized them separately and summed up
the utilization.  The gate count actually fit into the ECP2-50 with
reasonable margin.  But the block-RAM utilization was much too high,
and if we were to make those into distributed RAMs, we'd probably blow
the gate count.


Here's one of the practical issues we're dealing with:

We want two independent video heads.  They need to be (internally) 64
bits wide.  That's two block RAMs each, for a total of four.  The
thing is, the memory bus is (effectively) 256 bits wide.  Although the
fifos would be emptied simultaneously, they would be filled one at a
time.  It's out of the question to try to read video words from memory
every 4th cycle, so we need something that's 256 bits wide to take
data coming out of memory.  We can't have both fifos 256 bits wide
(That's 16 RAM blocks).

One option is to use a distributed RAM FIFO that's 32 words deep
(using 512 LUTs, which is a LOT).  Unfortunately, we wouldn't be able
to read video in very long bursts (about 32 words), giving us less
than 80% efficiency on memory bandwidth.

Another option is to use eight block rams as a front-end fifo, dumping
quarter-rate into the appropriate output fifos.  That's 12 block RAMs.

Keep in mind that the ECP2-50 has only 21 block RAMs, and they're not
fully dual-ported.

Some other things that block RAMs will be used for:

- Engine command fifo (1)
- Video color LUTs (6)
- Cursor glyphs (1 or 2)
- Video display lists (2)

And we haven't even thought of everything.  Depending on how we do it,
we're either using gobs of distributed memory, or we need at least one
more block RAM than we need.  The designs we put together used even
more than these, and for good reason, so we cannot look at this and
say that we've accounted for everything.

With FPGAs, you cannot achieve 100% utilization.  It's impossible.
We're looking at this and saying that if our sums come up to just over
100%, there's no way we're going to be able to do the maximum
recommended 80%, let alone the usual 60% you want to shoot for to get
a design that runs at any reasonable clock rate.

Still, we could be making bad assumptions.  If I had time, I'd look
though the OGA model and try to estimate its needs.  Perhaps I can get
some other people to help with this.

An option we have is to produce an ECP2-50 board now and then switch
to the ECP2-70 in 2007.  The risk we take there is that some people
will put off buying OGD1 boards for that reason, which will kill us.
We need to sell them NOW.  A trade-in deal is possible, but every
trade-in will be a financial loss, unless we can sell used -50
versions at a discount that makes up for the loss.

And this whole debate could be for nothing if it turns out that we're
way overestimating the logic requirements.

The most critical thing is that we need to answer this question NOW.
I'm bringing this up for public debate so that Traversal aren't the
only people trying to figure this out.  We can estimate based on past
designs (which are quite different).  But estimating OGA's
requirements is something that we could use some help with.
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