On Tuesday 20 June 2006 16:20, Timothy Miller wrote: > First of all, we do not want to switch parts if we can avoid it. > Using the ECP2-50 has advantages in price, saves us two weeks on OGD1, > and if we can cram a good 3D design into it, that saves us on die area > and therefore cost on the ASIC. > > Our approach to judging the fitness of the ECP2-50 was to take some > pieces of other designs and see how well they fit. One part is a > wider but simpler 2D graphics engine. The other part is some video > backend processing logic. Add to those various pieces of support > logic like memory controller, etc., and you have what should be a good > estimate for a graphics chip. We didn't try to put them together into > an actual design; rather, we synthesized them separately and summed up > the utilization. The gate count actually fit into the ECP2-50 with > reasonable margin. But the block-RAM utilization was much too high, > and if we were to make those into distributed RAMs, we'd probably blow > the gate count.
I believe I said early on in the project's development that you'd want an XC3S4000 with the option of switching to the 5000. :P Three points: (1) I think we'd all agree that we want to have our RTL developers spending their time working on features and bug-squashing than desperately playing with P&R in an attempt to reach the mythical 90% utilisation, so in that respect a bigger FPGA would be better. (2) The lack of WebPack support for the biggest XC3S devices could be a major hurdle in getting acceptance from hobbyists. (3) The XC3S4000 actually has _less_ LE than the EC2-50 as far as I can tell? I assume the fact it has more BRAM (and has more flexible RAM configuration options) makes up for that? Peter -- Fisher Society publicity officer http://tinyurl.com/o39w2 CUSBC novices, match and league secretary http://tinyurl.com/mwrc9 Quake II build tools maintainer http://tinyurl.com/fkldd v2sw6YShw7$ln5pr6ck3ma8u6/8Lw3+2m0l7Ci6e4+8t4Eb8Aen5+6g6Pa2Xs5MSr5p4 hackerkey.com
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