On 8/16/07, Mark <[EMAIL PROTECTED]> wrote: > > Sorry if this has already been described somewhere, but i was wondering > > how that is done as well. the IOBs mess up my timing analysis a lot. > I know with Xilinx's tools, you can use synthesis attributes in the HDL, > XST command-line options, or constraints in the UCF to prevent flops > from getting packed into IOBs. You can also apply constraints in the > UCF to ignore timing on certain paths (say, from pins to flops). It's > documented in the constraints guide (the IOB and TIG constraints, I > think) and the XST manual.
You want to avoid not just the IOBs, but also the routing delays to get from the pins to your logic and back to the pins. Your approach of adding flops on inputs and outputs is the right thing to do, but sometimes, you end up having to add another layer. IOBs, block RAMs, and multipliers are on the fringes, and whether you're trying to avoid them (like in this case) or actually use them for normal purposes, a common challenge is dealing with the fact that your logic may be quite far away from the dedicated modules. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
