Farhan Mohamed Ali wrote:
On Thu, August 16, 2007 8:54 am, Timothy Normand Miller said:
Also, how are you ensuring that I/O buffers are not being inferred and
considered in the static timing analysis?
I'm not doing anything to ensure that I/O buffers aren't inferred. As
for not considering I/O delays, I've tried to isolate that by placing
flops at the inputs & outputs of the multiplier. It's not rigorous, but
my intention was just to get very rough timing & area numbers on the
target device. The critical path is indeed flop -> mult -> flop, for
what it's worth. It looks to me like like the input flops are getting
packed into the IO blocks but the output flops are in slices. I've only
been using the Lattice tools for a couple days and I've not read much
documentation -- just doing what I can as quickly as I can.
Sorry if this has already been described somewhere, but i was wondering
how that is done as well. the IOBs mess up my timing analysis a lot.
I know with Xilinx's tools, you can use synthesis attributes in the HDL,
XST command-line options, or constraints in the UCF to prevent flops
from getting packed into IOBs. You can also apply constraints in the
UCF to ignore timing on certain paths (say, from pins to flops). It's
documented in the constraints guide (the IOB and TIG constraints, I
think) and the XST manual.
_______________________________________________
Open-graphics mailing list
[email protected]
http://lists.duskglow.com/mailman/listinfo/open-graphics
List service provided by Duskglow Consulting, LLC (www.duskglow.com)
