Mike,
re-reading your original post a couple of times, and this new
message, I am still a little confused about not what you are spec'ing but
the possible variations one could see in circuit performance.
I am pretty sure I now understand exactly what you are spec'ing and
'your' reasons for doing such. Then my thoughts immediately flash to the
possible variation in your build-up and the possible electrical
ramifications of that methodology. I may be wrong because of the sensitivity
of our company's circuits but I would think that somewhere your method could
be a disaster for the unwary. And on that note, it is my belief that most
design shops do not do 'any' signal integrity simulation, especially across
such a possible wide variation of build up profiles.
Well I look forward to your article in PCD. I am betting it will
probably be a useful article, rather then the usual articles telling us
everything that we already knew or didn't know, in general terms and not
really supplying any useful knowledge or techniques.
Mike, do you know it will be published, or is this a hopeful
submission?
Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com
> -----Original Message-----
> From: Michael Reagan [mailto:[EMAIL PROTECTED]]
> Sent: Monday, July 09, 2001 2:41 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Layer Stackup Info.
>
>
> Abdul and Brad,
> If your design is critical to a particular thickness, then
> yes you must
> specify it. no doubt, however if it aint, specify the min
> acceptable and
> give your design house the latitude to build up. Funny we
> are all on this
> subject, I plan to submit a paper to PCD magazine, about
> board specification
> and fab notes later this month or early next month.
>
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